Abstract: A current limiter (15) is formed between a silicon substrate (10) and a source region (17) by a channel implant region (20). The channel implant region (20) is not modulated by a gate structure so the maximum voltage that can flow between the silicon substrate (10) and the source region (17) is determined by the doping profile of the ever-present channel implant region (20). A pinch-off structure (12) is used to form a depletion region which can support a large voltage potential between the silicon substrate (10) and the source region (17). In an alternate embodiment, a bipolar device is formed such that a limited current flow can be directed into a base region (32) which is used to modulate a current flow between silicon substrate (30) and an emitter region (38). Using the current limiters (15, 35) it is possible to form an AC current limiter (50) that will limit the current flow regardless of the polarity of the voltage placed across two terminals (51, 52).

Abstract: A bidirectional current blocking lateral power MOSFET including a source and a drain which are not shorted to a substrate, and voltages that are applied to the source and drain are both higher than the voltage at which the body is maintained (for an N-channel MOSFET) or lower than the voltage at which the body is maintained (for a P-channel MOSFET). The on-resistance of the MOSFET is improved by decreasing the conductance of the epi region and disposing a thin threshold adjust layer on the surface of the substrate between the source and drain regions. An optional second punchthrough preventing implant is disposed on the substrate surface.

Abstract: A process for forming low threshold voltage P-channel MOS transistors in semiconductor integrated circuits for analog applications, said circuits including high resistivity resistors formed in a layer of polycrystalline silicon and N-channel MOS transistors having active areas which have been obtained by implantation in a P-type well, comprises the steps of,providing a first mask over both said resistors and the semiconductor regions where the low threshold voltage P-channel transistors are to be formed,doping the polycrystalline layer uncovered by said first mask,providing a second mask for protecting the resistors and the semiconductor regions where said low threshold voltage P-channel transistors are to be formed, andN+ implanting the active areas of the N-channel transistors.

Abstract: An object of the present invention is to ease the dielectric strength requirements for transistors forming power supply circuits or the like. A nonvolatile semiconductor memory of the present invention includes a plurality of memory cells, each of which is composed of a floating gate, a control gate, a drain, and a source, and a negative voltage generating means whose generated negative voltage is applied to the control gate for drawing a charge stored in the floating gate into a channel or the source when stored data is erased electrically. The nonvolatile memory of the present invention further includes positive erasure voltage generating means, and a positive voltage higher than a conventional supply voltage generated by the positive erasure voltage generating means is applied to the channel or the source.

Abstract: In accordance with the invention, a double poly process is used to double the memory density of a buried bit line ROM on the same silicon area. In particular the word-line pitch is decreased to increase the cell density in a direction perpendicular to the word lines. The invention uses a self-aligned method for ROM code implantation and a polyplanarization by chemical-mechanical polishing (CMP) to achieve a self aligned double poly word line structure.

Abstract: A ROM is formed by depositing a first layer composed of a material selected from polysilicon and polycide on the substrate, patterning the first layer by masking and etching, depositing a dielectric layer over the first layer and patterning the dielectric layer and the first layer into the pattern of first conductor lines, forming a contact window through the dielectric layer down to the substrate, depositing a second layer composed of a material selected from polysilicon and polycide on the device and forming second conductor lines directed orthogonally to the first conductor lines formed from the first layer, and ion implanting into the substrate through the second layer to form a contact region electrically connected to the second conductor lines of the second layer.

Abstract: A dynamic threshold voltage IGFET such as a MOSFET is operable at voltages of 0.6 volt or less. The threshold voltage of the transistor is reduced to zero volt or less by interconnecting the gate contact and the device body in which the voltage controlled channel is located. Several efficient connections using through hole plating or polycrystalline silicon gate extension are disclosed. A higher power supply voltage can be used by interconnecting the gate and device body through a smaller MOSFET.

Abstract: A semiconductor element including a silicon substrate, a silicon oxide film formed on the silicon substrate, and a top electrode formed on the silicon oxide film, wherein chromium is included only in a region of the silicon oxide film, the region including the interface between the silicon oxide film and the top electrode and the vicinity of the interface, and the method of manufacturing the same.

Abstract: AMOS transistor with enhanced electrical characteristics and a method for manufacturing the same. In the channel region, a first impurity region is provided for adjusting a threshold voltage, a second impurity region is provided which serves as a diffusion barrier, and a third impurity region is provided for preventing a punchthrough. These regions are formed sequentially at subsequently shallower depths in the substrate. The disclosed transistor minimizes short-channel effects and punchthrough without reducing the current driving capability of the device.

Abstract: Upward and downward variation of a threshold voltage of a TFT is effectively suppressed by a semiconductor device and a method of manufacturing the same. In the semiconductor device, a conductive layer is formed on the substantially same plane as a semiconductor layer forming a channel region and source/drain regions of the TFT, and is spaced from the semiconductor layer by a predetermined distance. A predetermined potential is applied to the conductive layer. Thereby, an electric field is applied from the conductive layer to the channel region of the TFT, so that variation of the threshold voltage of the TFT is effectively prevented.

Abstract: An N-channel and P-channel MOSFET include counterdoping of a threshold voltage (V.sub.T) ion implant for reducing substrate sensitivity and source/drain junction capacitance. An arsenic (As) compensated boron (B) implant is provided in the N-channel MOSFET. A boron (B) compensated arsenic (As) implant is provided in the P-channel MOSFET.

Abstract: A semiconductor device includes a semiconductor substrate doped with a first conductivity type. The substrate has a surface, with a parallel array of word lines ion implanted as regions in the surface of said substrate. The N+ word lines are of the opposite conductivity type from the P- substrate. A dielectric layer, formed on the substrate above the word lines, is covered with a polysilicon layer doped with a P- conductivity type. A second dielectric layer covers the polysilicon layer. A parallel array of N+ conductivity regions form doped N+ bit lines in the polysilicon layer. Above the N+ bit lines are formed alternating strips of planarized silicon nitride separated by silicon dioxide strips which are covered by a BPSG layer. An etched code pattern is formed extending through the polysilicon layer in a predetermined region providing an encoded RON.

Abstract: A bidirectional current blocking switch is disclosed. The switch includes a four-terminal MOSFET in which there is no source-body short. The voltages applied to the source and drain terminals are both higher than the voltage applied to the body terminal (for an N-channel) device so that the source-body and drain-body junction of the MOSFET never become forward-biased. The switch of this invention is particularly useful for switching a cascaded set of batteries in a portable computer.

Abstract: Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implantation of the first ions into the protective circuit region.

Abstract: A non-volatile random access memory (NVRAM) cell that utilizes a simple, single-transistor DRAM cell configuration. The present NVRAM employs an enhancement mode nMOS transistor made as an accumulation mode transistor. The transistor has an n-type silicon carbide channel layer on a p-type silicon carbide buffer layer, with the channel and buffer layers being on a highly resistive silicon carbide substrate. The transistor also has n+ source and drain contact regions on the channel layer. A polysilicon/oxide/metal capacitor is preferably used which has a very low leakage current. Furthermore, this type of capacitor can be stacked on top of the transistor to save area and achieve high cell density. It is preferred to use a non-reentrant (edgeless) gate transistor structure to further reduce edge effects.

Abstract: A MOS random access memory device includes a semiconductor substrate having a trench formed therein, and an array of memory cells on the substrate. Each of the memory cells includes a 1-bit data-storage capacitor and a transfer-gate MOS transistor. The capacitor includes an insulated layer buried in the trench, which serves as a storage node. An island-shaped semiconductor layer covers the storage-node layer at least partially on the substrate, and is coupled thereto. The transistor has a source and a drain defining a channel region therebetween in the substrate, and an insulated gate overlying the channel region. One of the source and drain is directly coupled to the island-shaped layer, while the other of them is contacted with a corresponding data-transfer line (bit line) associated therewith.

Abstract: A MOSFET having a nonuniform doping channel and a method for fabricating the same.The MOS transistor having a nonuniform doping channel is comprised of: a gate oxide film formed on a semiconductor substrate provided with a trench; a gate electrode of some size formed on the gate oxide film atop the trench and its surroundings, the gate electrode having a portion longer than any other portion and thus, being asymmetrical with regard to the axis passing the center of the trench; a source region formed in a predetermined portion of the semiconductor substrate neighboring a short portion of the gate electrode; a high density channel region formed by doping impurities having the same type with the semiconductor substrate in a predetermined portion of the semiconductor substrate below a longer portion of the gate electrode; and a drain region formed in a predetermined portion of the semiconductor substrate neighboring the high density channel region.

Abstract: A method of forming ROM transistor memory cell including not forming lightly doped regions in the semiconductor substrate for some of the memory cells so as to form one type of memory cell and forming the lightly doped regions in another type of memory cell.

Abstract: A semiconductor device has a first P type well region (11) formed on an N type semiconductor substrate (10) and a second N type well region (12) formed so as to enclose the first well region. A third N type well region (13) formed on the semiconductor substrate is enclosed by a fourth P type well region (14). The first well region adjoins and is electrically connected to the fourth well region. Contact regions (15, 16) are formed on the first and third well regions to apply a bias voltage to the PN junction between the first and third well regions. An NMOS FET is formed in the first well region and a PMOS FET is formed in the third well region. The drain currents of the NMOS FET and PMOS FET are controlled by changing the reverse bias voltage applied to the two contact regions (15, 16). The depth of the first well region (11) is such that a depletion layer extending below the NMOS FET gate electrode (50) can be connected to a depletion layer formed at an interface between the first and second well regions.

Abstract: A pair of vertical DMOS transistors include a threshold adjust implant which extends across the sources and body regions and into a common drain region of the devices, the threshold adjust implant having a peak dopant concentration whose depth into the semiconductor body is non-uniform laterally across the devices. A process for fabricating the transistors includes a high temperature, long diffusion subsequent to deposition of the polysilicon gates for forming body regions. The threshold voltage of the VDMOS devices is adjusted subsequent to both gate formation and the high temperature, long duration body diffusion by implanting a suitable p-type dopant into the VDMOS channels through the insulated gates, after formation thereof. Since the gates are formed prior to threshold adjust, high temperature processing and long duration diffusions requiring the presence of the gate may be completed prior to threshold adjust, without risk to the adjusted device threshold.

Abstract: A semiconductor integrated circuit of a read-only memory device having steep trenches is disclosed. The memory device includes a substrate that has a plurality of interwoven chessboard-like trenches, each trench including opposing and sloping side walls. The memory device also includes a plurality of drain/source regions formed on the substrate. Neighboring drain/source regions are positioned, in conformity with the presence of mesas and bottoms of the trenches, in a high and low interwoven manner in a first direction along the plane of the substrate at an altitude relative to the plane of the substrate, thereby forming a generally vertical drain/source channel between each pair of neighboring drain/source regions. The memory device further includes a gate oxide layer formed on the substrate, and a plurality of gate regions formed on the surface of the gate oxide layer.

Abstract: A bidirectional current blocking lateral power MOSFET including a source and a drain which are not shorted to a substrate, and voltages that are applied to the source and drain are both higher than the voltage at which the body is maintained (for an N-channel MOSFET) or lower than the voltage at which the body is maintained (for a P-channel MOSFET). The on-resistance of the MOSFET is improved by decreasing the conductance of the epi region and disposing a thin threshold adjust layer on the surface of the substrate between the source and drain regions. An optional second punchthrough preventing implant is disposed on the substrate surface.

Abstract: A micro MIS type FET comprises first conductivity type source/drain regions formed in a surface of a semiconductor layer mutually spaced apart by a distance of less than 2 .mu.m, a second conductivity type channel layer having an impurity concentration of less than 1.times.10.sup.16 /cm.sup.3 formed between the source/drain regions to have a depth less than depths of the source/drain regions, and a second conductivity type threshold voltage control region having an impurity concentration of more than 1.times.10.sup.17 /cm.sup.3 beneath the channel layer.

Abstract: In a semiconductor device having a gate electrode and an insulating film covering the gate electrode on a compound semiconductor substrate, the stress in the gate metal and the stress produced by the insulating film on the gate electrode cancel so that threshold voltage is not a function of gate orientation relative to the crystalline directions of the substrate.

Abstract: Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region.

Abstract: Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region.

Abstract: The present invention is directed to a charge transfer apparatus. A reset gate (RG) is formed of an N-channel MOSFET of depletion type in which a carrier concentration of a channel region is set in a range from 10.sup.15 to 5.times.10.sup.16 cm.sup.-3. Also, a circuit for generating a reset pulse that is supplied to the reset gate (RG) is constructed as follows. A drain voltage source (12) and a drain of a transistor (Tr) are connected via a junction (a), and two resistors (R1) and (R2) are connected in series between the anode of the drain voltage source (12) and the ground. A junction (b) between the resistors (R1) and (R2) and the reset gate (RG) are connected together via an input line (13) and a high resistance (Rh) is inserted into the input line (13). Further, a coupling capacitor (Cc) is connected between a clock pulse input terminal (.phi.in) and the input line (13).

Abstract: A field effect transistor includes a source electrode and a drain electrode disposed on a compound semiconductor substrate, a gate electrode having a T-shaped cross-section, and a gate pad having a T-shaped cross-section disposed at one side of the gate electrode, the gate electrode and the gate pad having a reinforcing thin metal film reinforcing the gate electrode on the rear surface of an overhanging portion of the head of the gate electrode and gate pad. Therefore, the head of the gate electrode is hardly ever separated from the leg of the gate electrode and a highly reliable T-shaped gate electrode is obtained. The gate electrode leg is produced using a thin film to which a pattern of the gate electrode is transcribed as a mask, thereby reducing the length of the head of the gate electrode. Accordingly, a T-shaped gate electrode is located in a deeper gate recess than ever without causing deterioration in the repeatability of its production.

Abstract: The breakdown voltage of a VDMOS transistor is markedly increased without depressing other electrical characteristics of the device by tying the potential of a field-isolation diffusion, formed under the edge portion of a strip of field oxide separating a matrix of source cells from a drain diffusion, to the source potential of the transistor. This may be achieved by extending a body region of a peripheral source cell every given number of peripheral cells facing the strip of field-isolation structure until it intersects said field-isolation diffusion. By so connecting one peripheral source cell every given number of cells, the actual decrement of the overall channel width of the integrated transistor is negligible, thus leaving unaltered the electrical characteristics of the power transistor.

Abstract: A nonvolatile semiconductor memory, which includes an array of programmable transistor cells, such as EPROM or EEPROM cells, provides electrical isolation without the use of field oxide islands. The cells are arranged in X number of rows and Y number of columns with the cells in at least two of the rows being designated as select cells and the remaining cells being designated as memory cells. Control circuitry is provided for causing the select cells to supply programming voltages to selected ones of the memory cells. Alternate ones of the select cells are formed as implanted-channel select cells to provide electrical isolation for adjacent select cells which remain in the low threshold (active) state. The implanted-channel select cells are formed by implanting a material into the channel region of each of the implanted-channel select cells to increase the threshold voltage of the cells, thereby preventing the implanted channel select cells from conducting when normal operational voltages are applied.

Abstract: An MOS transistor wherein the channel between the source and drain is formed with two regions having different dopant concentrations. The region adjacent the source has a normal concentration, while that adjacent the drain has a reduced dopant concentration. This reduces the degrading effects of hot carrier injection, thereby extending the life of the transistor.

Abstract: A bidirectional current blocking lateral power MOSFET including a source and a drain which are not shorted to a substrate, and voltages that are applied to the source and drain are both higher than the voltage at which the body is maintained (for an N-channel MOSFET) or lower than the voltage at which the body is maintained (for a P-channel MOSFET). The on-resistance of the MOSFET is improved by decreasing the conductance of the epi region and disposing a thin threshold adjust layer on the surface of the substrate between the source and drain regions. An optional second punchthrough preventing implant is disposed on the substrate surface.

Abstract: A gate electrode comprises a N.sup.+ type polysilicon film and N.sup.- type polysilicon films directly contacted with side of the N.sup.+ type polysilicon film. Under the N.sup.+ type polysilicon films, N.sup.- type source.drain regions are provided in a P type silicon substrate to be coplanar with the main surface thereof.

Abstract: A nonvolatile semiconductor memory is comprised of a semiconductor substrate composed of N-type silicon, a pair of source and drain regions having opposite electroconductivity to that of the semiconductor substrate and being formed in a surface region of the semiconductor substrate in spaced relation to each other to define therebetween a channel region, a gate insulating film formed on the channel region, a floating gate electrode formed on the gate insulating film over the channel region and composed of N-type polysilicon, and an insulating layer formed to cover the floating gate electrode. The floating gate electrode is composed of the N-type polysilicon effective to reduce the thickness of adjacent gate insulating film below 500 .ANG. to thereby significantly micronize the dimension of memory.

Abstract: A structure and its fabrication method of an integrated semiconductor device including circuit elements such as MOSFETs. A well is formed in the semiconductor substrate within windows of a field oxide layer. A lightly-doped semiconductor layer is selectively formed on the exposed surface of the well. A channel region and a pair of source and drain regions of a MOSFET are formed in the lightly-doped semiconductor layer. The highly-doped buried semiconductor layer of the same conductivity type as that of the lightly-doped semiconductor layer is formed under the channel region in the lightly-doped semiconductor layer. The structural features and fabrication method provides a great degree of freedom in designing a MOSFET having a further shorter-channel length without deteriorating its drivability and punch-through breakdown voltage.

Abstract: This invention relates to a process for fabricating a metal-oxide-semiconductor device and to the semiconductor device which has enhanced charge mobility due to the inclusion of a thin layer of intrinsic semiconductor which provides a "fast track" charge channel directly at the accumulated inversion layer. The particular semiconductor device described is the enhanced mobility metal-oxide-semiconductor field effect transistor EMMOSFET having the intrinsic layer from about 100 .ANG. to about 1000 .ANG. thick. The intrinsic layer provides a low resistivity channel between the source and drain of the EMMOSFET resulting in an increase in device speed and a decrease in device heat generation.

Abstract: In a semiconductor device having a gate electrode and an insulating film covering the gate electrode on a compound semiconductor substrate, the vector sum of the stress in the gate metal and the stress produced by the insulating film on the gate electrode is zero. A production method of a semiconductor device includes producing a gate electrode having the same but opposite stress of an insulating film by sputtering under an adjusted gas pressure a target of WSi.sub.x and depositing an insulating film covering the gate electrode.

Abstract: A field effect transistor signal switching device includes a semiconductor substrate including an active region; an input electrode disposed on the substrate and including a source electrode disposed on the active region and a source pad; first and second output electrodes respectively including first and second drain electrodes disposed on the active region; and first and second control electrodes disposed on the substrate for controlling the selective transmission of an input signal applied to the input electrode to the first and second output electrodes, the first and second control electrodes respectively including first and second gate electrodes disposed on the active region between the source electrode and the first and second drain electrodes, respectively, first and second gate pads, and first and second connecting portions disposed on the substrate respectively electrically connecting the first and second gate electrodes to the first and second gate pads.

Abstract: In a mask ROM device, a plurality of recesses extending parallel to each other are formed in a memory cell array region on the surface of a silicon substrate. In the direction intersecting the recesses, first and second transistor trains are formed in which select transistors and memory transistors are connected in series. The MOS transistors of the transistor trains have the sidewall of recess 5 formed as a channel region. A depletion implantation layer corresponding to data to be stored is formed on the sidewall of the recess. The first transistor train and the second transistor train are insulated and isolated from each other by an LOCOS isolation film.

Abstract: Disclosed is a semiconductor device having an internal circuit protected by an electrostatoc protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region.

Abstract: Described is an E.sup.2 PROM design comprising a channel region and a floating gate comprising P-type polycrystalline silicon. The work function difference between P-type material effectively increases the threshold voltage of the transistor. This alleviates the need for a boron V.sub.T adjust implant. Implants of material such as boron to set the threshold voltage are known to correlate with problems such as implant ionization and junction (avalanche) breakdown. These two undesired effects can be decreased or eliminated in devices comprising the invention. An optional phosphorous implant into the substrate would allow the lowering of V.sub.T to a desired level.

Abstract: A depletion operation is realized by using a depletion type MOSFET even at the room temperature or the liquid nitrogen temperature without doping the channel portion below the gate electrode with impurities having a conductivity type, which is opposite to the conductivity type of the semiconductor substrate. Further this FET can construct an inverter together with an enhancement type FET and these can be integrated on one substrate.

Abstract: An electrically programmable and electrically erasable memory cell (EEPROM) formed in a silicon body is described. The cell includes a silicon body or substrate with shallow trench isolation regions disposed therein. First and second spaced-apart source and drain regions of a first conductivity type are provided with a channel region in between. A first gate member, a floating gate, which is completely surrounded by insulation extends from at least the edge of the source region, over the channel region to at least the edge of the drain region. A second gate member, a control gate, includes a portion which extends over the floating gate. The control gate extends from at least the edge of the source region, over the channel region to at least the edge of the drain region. The channel region beneath the floating gate has both a highly doped portion and a lightly doped portion.

Abstract: A semiconductor device which includes a MOS type transistor has impurity ion implanted regions (4) of the same conductivity type as that of the semiconductor substrate (1) for controlling a threshold voltage of a channel region, at least in the vicinity of a channel region provided between the source/drain regions (6, 8) on the surface of the semiconductor substrate (1). In the device the concentration distribution in the impurity ion-implanted regions (4) is higher in the vicinity of opposite ends of the channel region and lower in a central portion of the channel region. By employing the structure of this semiconductor device, while holding a suitable threshold voltage, a high potential barrier is formed at both ends of the channel region, so that insulating breakdown voltage of the source/drain regions (6, 8) is increased.

Abstract: The present invention provides a semiconductor device having a well, formed in a semiconductor substrate by using a mask in which a mask pattern width of a portion corresponding to an opening diameter is equal to or less than twice the diffusion depth of the well layer, and a gate electrode formed to have the well layer as a channel region of a MOS transistor. The well formed in this manner has a substantially semi-circular section to facilitate impurity concentration control in the substrate surface. When a plurality of types of opening patterns having small pattern widths are formed in a single mask, MOS transistors having different threshold voltages can be formed in a single process.

Abstract: A base resistance controlled thyristor with single-polarity and dual-polarity turn-on and turn-off control includes a turn-off device provided between the second base region and the cathode of a thyristor. Controlled turn-off is provided by either a near-zero positive bias or a negative bias being applied to the turn-off device. In the preferred embodiment, the turn-off device is a P-channel depletion-mode MOSFET in the surface of a semiconductor substrate. Accordingly, an accumulation-layer channel can be formed between the second base region and the cathode in response to a negative bias. Alternatively, if single-polarity control is desired, the P-type channel is provided to turn-off the device in response to a near-zero positive bias. In either type of operation, however, advantages are obtained over conventional turn-off devices wherein inversion-layer channels are used.

Abstract: An MOS semiconductor device has n.sup.30 -type source and drain regions in the main surface of a p.sup.30 -type monocrystalline silicon substrate. A p.sup.30 -type channel region is formed between the source and drain regions. A gate oxide film is provided on the main surface of the channel region, and a gate electrode is formed on the gate oxide film. In the portion of the monocrystalline silicon substrate between the source and drain regions, an inversion layer control region having an impurity concentration lower than that of the substrate is buried adjacent to the drain region. When a voltage is applied between the source and drain regions, the inversion layer control region maintains up to a high voltage an n-type inversion layer formed in the channel region.

Abstract: A submicrometer, near-intrinsic, thin-film, SOI complementary filed effect transistor structure is disclosed. The device is characterized by having a gate comprising material having a work function which approximates its Fermi level to the middle of the band gap of the channel material. Such devices display desirable transconductance, subthreshold slope and punch-through resistance.