Abstract: A method for manufacturing a semiconductor device that includes dual gate oxide layers made of two dielectric layers of varying thickness on a single wafer. In an example embodiment, a semiconductor structure is fabricated by providing a first layer of a dielectric over a semiconductor material and covering the first layer with a protective second dielectric layer adapted to mask the first layer. The first and second layers are then removed over a region of the semiconductor material while the second layer is used to protect the first layer, therein leaving the region of semiconductor material substantially exposed. A third layer of dielectric material is formed over the first and second layers and the adjacent exposed semiconductor material region; a gate material is then formed over the third dielectric layer. Finally, an etching step etches through the gate material and underlying layers to the semiconductor material to form a thick gate region and a thin gate region.

Abstract: The present invention is directed to a method of manufacturing a semiconductor device having a triple-well structure, comprising the steps of: forming a first pattern of a semiconductor substrate having a first N-well forming area, a R-well forming area, a second N-well forming area and a P-well forming area; forming a first layer within the substrate at a predetermining depth by implanting a N-type impurity ion using the first pattern as a mask; forming a bottom N-well within the substrate at a predetermined depth by implanting a N-type impurity ion using the first pattern as a mask; removing the first pattern; forming a second pattern on the substrate; forming a first lateral N-well and a second lateral N-well by implanting a N-type impurity ion using the second pattern as a mask, and portions of the first and second lateral N-wells overlap with opposite edge portions of the bottom N-well, thereby forming a N-well; removing the second pattern; forming a third pattern on the substrate; forming a second defec

Abstract: The present invention provides novel structures of MOS field effect transistor which operate with high speed and low power consumption. This has been achieved through providing epitaxial growth layers on a substrate of high impurity doping concentration in which the thickness of epitaxial growth layers is controlled with a degree of accuracy on the order of a single atom layer.

Abstract: A nonvolatile semiconductor memory has memory cells (1) each having an insulated-gate FET that has an information storage part. A semiconductor region (27) is formed at the surface of a channel region of each memory cell. The semiconductor region has the same conductivity type as a channel conductivity type and functions to decrease the strength of an electric field at the surface of the channel region. If the insulated-gate FET is of an n-channel type, the semiconductor region is of an n-type. The semiconductor region suppresses threshold voltage variations among the insulated-gate FETs of the memory cells and prevents soft-writing in the memory cells.

Abstract: A logical circuit device has a MOS transistor having a source region, a drain region, a channel region defined between the source region and the drain region, and a gate electrode formed above the channel region, respectively formed on a semiconductor substrate. The amplitude of a voltage applied to the gate electrode necessary for making the channel region conductive is not level throughout the channel region in the width direction. Using such a logical circuit device, flip-flop circuits and storage circuits of a multivalued logic type can be realized.

Abstract: Dot-pattern-like impurity regions 104 are artificially and locally formed on a channel forming region 103. The impurity regions 104 restrain the expansion of a drain side depletion layer toward the channel forming region 103 to prevent the short channel effect. The impurity regions 104 allow a channel width W to be substantially fined, and the resultant narrow channel effect releases the lowering of a threshold value voltage which is caused by the short channel effect.

Abstract: A semiconductor device according to the invention is constructed as below. A charge accumulating layer which contains a magnetic substance is formed directly on a semiconductor substrate, and a gate insulating film is formed on the charge accumulating layer. Further, a gate electrode is formed on the gate insulating film, and source and drain regions formed in surface portions of the semiconductor substrate such that the gate electrode is interposed therebetween. Another semiconductor device according to the invention is constructed as below. A first gate insulating film formed on a semiconductor substrate, and a charge accumulating layer which contains a magnetic substance is formed on the first gate insulating film. Further, a second gate insulating film is formed on the charge accumulating layer, and a gate electrode is formed on the second gate insulating film. Source and drain regions formed in surface portions of the semiconductor substrate such that the gate electrode is interposed therebetween.

Abstract: High voltage and low voltage devices are provided on a common semiconductor substrate. An integrated semiconductor circuit includes a semiconductor substrate of a first conductivity type. Well regions of a first conductivity type and well regions of a second conductivity type are formed in the substrate. Low voltage devices are formed in well regions of the first conductivity type. A high voltage device includes source/drain regions of the second conductivity type formed, respectively, in well regions of the second conductivity type, an oxide region disposed on a surface of the substrate located above a region of the substrate that serves as a channel for the high voltage device, and a gate region disposed on the oxide region.

Abstract: A depletion mode MOSFET and resistor are fabricated as a silicon carbide (SiC) integrated circuit (IC). The SiC IC includes a first SiC layer doped to a first conductivity type and a second SiC layer overlaid on the first SiC layer and doped to a second conductivity type. The second SiC layer includes at least four more heavily doped regions of the second conductivity type, with two of such regions comprising MOSFET source and drain electrodes and two other of such regions comprising resistor electrodes. The second SiC layer includes an isolation trench between the MOSFET electrodes and the resistor electrodes. At least two electrically conductive contacts are provided as MOSFET electrode contacts, each being positioned over at least a portion of a respective MOSFET electrode and two other electrically conductive contacts are provided as resistor electrode contacts, each being positioned over at least a portion of a respective resistor electrode.

Abstract: An object of the invention is to reduce an offset voltage to realize a small occupying area in a comparator using MOS type transistors. The invention is characterized in that impurities are introduced into channel areas of MOS type transistors, and mobility of the MOS type transistor on a load side is smaller than mobility of the MOS type transistor on a differential side, and a mutual conductance gm of the MOS type transistor on the load side is smaller than a mutual conductance gm of the MOS type transistor on the differential side.

Abstract: An integrated circuit includes a substrate pump circuit developing an internal back-bias voltage on an output, and an external terminal adapted to receive an external back-bias voltage. A semiconductor substrate is coupled to the external terminal and to the output of the substrate pump circuit. The semiconductor substrate includes at least one transistor formed in the semiconductor substrate which has a first threshold voltage when the internal back-bias voltage is applied to the substrate. The at least one transistor has a second threshold voltage greater than the first threshold voltage when the external back-bias voltage is received on the external terminal.

Abstract: A method for programming a read-only memory cell including a transistor whose source and drain, which have a second type of doping, are formed in a semiconductor substrate with a first type of doping, includes a step of carrying out a contradoping in a region of the source, the region being adjacent to the conduction channel 4, to make it a region with the first type of doping so as to prevent a transistor effect from occurring.

Abstract: Methods of forming field effect transistors and resultant field effect transistor circuitry are described. In one embodiment, a semiconductive substrate includes a field effect transistor having a body. A first resistive element is received by the substrate and connected between the transistor's gate and the body. A second resistive element is received by the substrate and connected between the body and a reference voltage node. The first and second resistive elements form a voltage divider which is configured to selectively change threshold voltages of the field effect transistor with state changes in the gate voltage. In a preferred embodiment, first and second diode assemblies are positioned over the substrate and connected between the gate and body, and the body and a reference voltage node to provide the voltage divider.

Abstract: A triple well structure for an embedded dynamic random access memory uses an ion implantation performed on a portion of the first conductive type substrate between a second conductive type source and a second conductive type deep well. A first conductive type block region is formed between the second conductive type source and the second conductive type deep well.

Abstract: A static self-locking micro-circuit-breaker includes a first MOS depletion transistor of a first type connected by its drain to a first main terminal and by its gate to a second main terminal, a second MOS depletion transistor of second type connected by its drain to the second main terminal and by its source to the source of the first transistor, a third MOS depletion transistor of the first type connected by its drain to the first main terminal, by its gate to the second main terminal, and by its source to the gate of the second transistor.

Abstract: MOS devices are formed on a wafer having a thick silicon layer 3a and a thin silicon layer 3b formed on a buried oxide film. The MOS device formed in the thick silicon layer 3a is activated in a partial depletion type mode. Further, the MOS device formed in the thick silicon layer 3b is activated in a perfect depletion type mode. Therefore, a low leakage current and a high-speed operation can be achieved simultaneously. It is thus possible to solve problems that an integrated circuit must be formed by either one of the partial depletion type device and the perfect depletion type device, and the low leakage current and the high-speed operation are hard to come to fruition simultaneously.

Abstract: A process for manufacturing a high performance transistor with self-aligned dopant profile. The process involves forming a source/drain mask pattern on a substrate. With a first implant material, unmasked portions of the substrate are doped to form source/drain regions of the substrate. The source-drain mask is removed and an oxidation layer is grown, where portions of the oxidation layer formed from doped regions of the substrate have heights that are greater than heights of portions of the oxidation layer formed from un-doped regions of the substrate, thereby forming a gate mask. The doped portions of the substrate are self-aligned with gate regions of the substrate. The gate regions are doped, and gate electrodes are formed. The gate mask is removed to expose source/drain regions of the substrate for further fabrication.

Abstract: There is provided a MOS device with self-compensating threshold implant regions and a method of manufacturing the same which includes a semiconductor substrate, a partial first threshold implant forming a higher concentration layer, a gate oxide formed on the surface of the higher concentration layer, and a gate formed on a surface of the gate oxide. The MOS device further includes a second threshold implant for forming self-compensating implant regions in the substrate which is subsequently heated to define pockets. A third implant is performed to create lightly-doped source/drain regions. A sidewall spacer is formed on each side of the gate. A fourth implant is performed to create highly-doped source/drain regions between the lightly-doped source/drain regions and the pockets.

Abstract: A diode device with a low or negligible threshold voltage includes at least one field effect transistor, the gate of the field effect transistor being connected to the drain of the field effect transistor. The threshold voltage of the diode device is approximately of the same magnitude as the potential of the gate of the field effect transistor forming part of the diode device.

Abstract: A CMOS device includes first and second wells formed in first and second regions of a semiconductor substrate, respectively. First and second transistors are formed in the respective wells. A third transistor is formed in a third region of the semiconductor substrate outside of the wells. A first impurity layer is formed in the vicinity of the depletion region of at least one but not more than two of the first, second, and third regions, and a second impurity layer, deeper than the first impurity layer, is formed in the region(s) of the substrate in which the first impurity layer is not formed. A method for manufacturing such a CMOS device enables the punch-through voltage characteristics of the first, second, and third transistors to be optimally different, without requiring any additional, separate mask processing steps.

Abstract: A method for making a memory cell (10) in a process in which both an n-channel MOS transistors (12) and a p-channel transistor (44) are formed in a semiconductor substrate (30) is presented. The method includes implanting an impurity (40) into a region of the substrate (30) to form a part of a depletion NMOS memory capacitor (21) to be associated with the n-channel MOS memory transistor (12). The implant is performed concurrently with a patterned implant with the same impurity to adjust the threshold and punch-through of the p-channel transistor (44).

Abstract: A two-terminal current limiting component, includes a substrate of a first conductivity type; separated wells of the second conductivity type; a first annular region of the first conductivity type in each well; a second annular region of the first conductivity type having a low doping level between the periphery of each first annular region and the periphery of each well; an insulating layer over the second annular region and the surface portions of the substrate; a first metallization coating the upper surface of the component; and a second metallization coating the lower surface of the component.

Abstract: Impurity regions 110 that can form an energy barrier are artificially and locally disposed in a channel formation region 111. The impurity regions 110 restrain a depletion layer that extends from a drift region 102 toward a channel formation region 111, and prevents a short channel effect caused by the depletion layer, with the result that an insulated gate semiconductor device high in withstand voltage can be manufactured without lowering the operation speed.

Abstract: The thin film transistor of this invention is formed on a substrate and includes an active layer and a first insulating film and a second insulating film sandwiching the active layer, wherein the overall polarity of fixed charges contained in the first insulating film is the reverse of the overall polarity of fixed charges contained in the second insulating film.

Abstract: A semiconductor processing method of forming a static random access memory cell having an n-channel access transistor includes, providing a bulk semiconductor substrate; patterning the substrate for definition of field oxide regions and active area regions for the n-channel access transistor; subjecting the patterned substrate to oxidizing conditions to form a pair of field oxide regions and an intervening n-channel access transistor active area therebetween, the field oxide regions having respective bird's beak regions extending into the n-channel access transistor active area, the n-channel access transistor active area defining a central region away from the bird's beak regions; and conducting a p-type V.sub.T ion implant into the n-channel active area using the field oxide bird's beak regions as an implant mask to concentrate the V.sub.T implant in the central region of the active area.

Abstract: A depletion type transistor formed on a semiconductor substrate includes a drain region and a source region formed in distinct areas on the substrate. An inversion layer is formed in the surface area between the drain and the source regions. The transistor further includes two insulated gates: a floating gate located above the substrate and insulated from the inversion layer by an insulating layer in such a way as to cover the inversion layer, and a control gate provided above the floating gate and insulated from the floating gate by the insulating layer.

Abstract: Disclosed herein is a semiconductor device comprising a semiconductor substrate, a well region provided in the surface of the substrate, a plurality of MOSFETs provided in the well region. The well region has parts having a low surface impurity concentration. Some of the MOSFETs have their channel regions provided in those parts of the well region which have the low surface impurity concentration. The other MOSFETs have their channel regions provided in other parts of the well region.

Abstract: An integrated circuit chip having circuitry to adjust its threshold voltage between a plurality of threshold voltages for interfacing to integrated circuit chips having different supply voltages. The integrated circuit chip also includes circuitry for communicating its threshold voltage level to a second integrated circuit such that the second integrated circuit may set its threshold voltage prior to receiving logic communications from the integrated circuit. The present invention also discloses an integrated circuit that detects the logic level of incoming logic communications and adjusts its threshold voltage accordingly.

Abstract: A semiconductor device to which two kinds of electric voltage can be supplied comprises: a first MOS transistor formed in the first well having a first conduction type and being fixed to a first electric potential, a second MOS transistor formed in a second well having a second conduction type different from the first one and being fixed to a second electric potential higher than the first electric potential, and a third well formed between the first and second wells having the second conduction type and being fixed to a ground electric potential. The first MOS transistor comprises a first gate oxide film having a prescribed thickness and a first gate electrode having a prescribed gate length, while the second MOS transistor comprises a second gate oxide film having a thickness larger than the prescribed thickness of the first gate oxide film and a second gate electrode having a gate length longer than the prescribed thickness of the first gate length.

Abstract: A process for producing a radiation resistant power MOSFET is disclosed. The gate oxide is formed toward the end of the processing and is not exposed to substantial thermal cycling. The gate oxide thickness is increased to more than 1250 .ANG. for a device with a reverse voltage rating of 250 volts and the channel concentration is reduced to maintain a low threshold voltage. The thicker oxide prevents single event damage under reverse bias voltage.

Abstract: An bipolar transistor of BiCMOS is provided to improve the breakdown voltage between a collector and a base. A low concentration diffusion layer is provided at a main surface of a semiconductor substrate at a boundary between an outer perimeter of an external base layer and an end portion of a field oxide film. The low concentration diffusion layer expands from the main surface of the semiconductor substrate toward the inside of the substrate and has a concentration lower than the impurity concentration of the external base layer.

Abstract: A depletion mode power MOSFET has a gate electrode formed of material that is refractory, or resistant, to high temperature encountered during device fabrication. A depletion channel region which is formed in a base region of a MOSFET and which interconnects the source and drain regions is formed after a high temperature drive to form the base region, but before a gate oxide and gate and source electrodes are formed at lower temperatures. The depletion channel region is thus subjected to reduced temperatures and grows only slightly in thickness, so that it can be easily depleted. The gate oxide, similarly, is subjected to reduced temperatures, and, particularly when made thin, exhibits high insensitivity to radiation exposure.

Abstract: To obtain an extremely small constant current with high accuracy, a constant current circuit comprises a first constant-current source for producing a first constant current, a second constant-current source connected to the first constant-current source for producing a second constant current having a different value from that of the first current, and an output terminal from which a third constant current equal to the difference between the first and second constant currents is output, such that the third constant current having an extremely small value may be produced without the use of a constant current source capable of producing an extremely small constant current value. The first and second constant current sources may be connected in series with the output terminal connected therebetween, or in parallel through a current mirror circuit. In addition, the constant current circuit can be provided in a timer circuit to produce a very long constant time signal with great stability.

Abstract: The invention relates to a field effect transistor that ensures that a threshold voltage does not increase even if a breakdown voltage is increased.

Abstract: An adjustable threshold voltage MOS device having an asymmetric pocket region is disclosed herein. The pocket region abuts one of a source or drain proximate the device's channel region. The pocket region has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. An MOS device having such pocket region may have its threshold voltage adjusted by applying a potential directly to its pocket region. This capability is realized by providing a contact or conductive tie electrically coupled to the pocket region. This "pocket tie" is also electrically coupled to a metallization line (external to the device) which can be held at a specified potential corresponding to a potential required to back-bias the device by a specified amount.

Abstract: A semiconductor processing method of forming a static random access memory cell having an n-channel access transistor includes providing a bulk semiconductor substrate; patterning the substrate for definition of field oxide regions and active area regions for the n-channel access transistor; subjecting the patterned substrate to oxidizing conditions to form a pair of field oxide regions and an intervening n-channel access transistor active area therebetween, the field oxide regions having respective bird's beak regions extending into the n-channel access transistor active area, the n-channel access transistor active area defining a central region away from the bird's beak regions; and conducting a p-type V.sub.T ion implant into the n-channel active area using the field oxide bird's beak regions as an implant mask to concentrate the V.sub.T implant in the central region of the active area.

Abstract: A current limiter (15) is formed between a silicon substrate (10) and a source region (17) by a channel implant region (20). The channel implant region (20) is not modulated by a gate structure so the maximum voltage that can flow between the silicon substrate (10) and the source region (17) is determined by the doping profile of the ever-present channel implant region (20). A pinch-off structure (12) is used to form a depletion region which can support a large voltage potential between the silicon substrate (10) and the source region (17). In an alternate embodiment, a bipolar device is formed such that a limited current flow can be directed into a base region (32) which is used to modulate a current flow between silicon substrate (30) and an emitter region (38). Using the current limiters (15,35) it is possible to form an AC current limiter (50) that will limit the current flow regardless of the polarity of the voltage placed across two terminals (51,52).

Abstract: A bidirectional current blocking switch is disclosed. The switch includes a four-terminal MOSFET in which there is no source-body short. The voltages applied to the source and drain terminals are both higher than the voltage applied to the body terminal (for an N-channel) device so that the source-body and drain-body junction of the MOSFET never become forward-biased. The switch of this invention is particularly useful for switching a cascaded set of batteries in a portable computer.

Abstract: A semiconductor device including a CMOSFET having first and second channel type MOSFETs, respectively formed in a first semiconductor region of a first conductivity type and in a second semiconductor region of a second conductivity type. The first channel type MOSFET has a first gate electrode insulatively formed on the first region, made of a first conductivity type semiconductor, and having a gate length of 0.2 .mu.m or less, first source/drain regions of the second conductivity type respectively formed in the first region and having a LDD structure, and a buried channel region of the second conductivity type formed just below the first gate electrode. The second channel type MOSFET has a second gate electrode insulatively formed on the second region, made of a first conductivity type semiconductor, and having a gate length of 0.2 .mu.m or less, second source/drain regions of the first conductivity type respectively formed in the second region and having a LDD structure.

Abstract: An insulated gate field effect transistor (IGFET) structure (10) includes a source region (14) and a drain region (16) formed in an impurity well (13). A channel region (18) separates the source region (14) from the drain region (16). In one embodiment, a unilateral extension region (17) is formed adjacent the source region (14) only and extends into the channel region (18). The unilateral extension region (17) has a peak dopant concentration at a depth (23) and a lateral distance (24) to provide punchthrough resistance. The IGFET structure (10) is suitable for low (i.e., 0.2-0.3 volts) to medium (0.5-0.6 volts) threshold voltage reduced channel length applications.

Abstract: A process for fabricating both CMOS and LDMOS transistors includes a high temperature, long diffusion subsequent to deposition of the polysilicon gate for forming MOSFET body regions. Similarly, a process for fabricating both CMOS and NPN transistors includes a high temperature, long diffusion subsequent to deposition of the polysilicon gate for forming NPN base regions. In both processes, the threshold voltage of the PMOS devices is adjusted subsequent to both gate formation and the high temperature, long diffusions by implanting a suitable dopant into the PMOS channel through the gate. Since the gate is formed prior to threshold adjust, high temperature processing and long diffusions requiring the presence of the gate are completed without adversely affecting the adjusted threshold voltage. The p+ source/drain implant mask can be used to restrict the threshold adjust implant to the PMOS devices, thereby avoiding adversely affecting other devices in the integrated circuit.

Abstract: An MOSFET has the essential feature lying in that the depths of well regions are different between a channel region and a diffusion region under a gate electrode to suppress charges in depletion layers. The MOSFET comprises a first well region which is formed in the channel region of a substrate below a gate electrode, and has a PN junction shallower than the sum of the width of a channel depletion layer formed by a voltage applied to the gate electrode and the width of a depletion layer formed by a substrate voltage of the substrate, and a second well region which is formed in source and drain regions to extend to the first well region, and has a PN junction deeper than the sum of the width of a depletion layer formed in the source or drain region and the width of a depletion layer formed in the first well region by the substrate voltage of the substrate.

Abstract: A read only memory semiconductor integrated circuit device includes an improved cell region and a method of manufacture therefor. The improved cell region includes a recessed dielectric region overlying a gate electrode region. Such recessed dielectric region allows for an implanting or coding step to occur after the dielectric layer is applied to the surface of the device. Coding of the ROM device during a latter processing step shortens product turn-around-time. The improved cell also includes an improved method of manufacture. Such method provides for a dielectric layer formed over a gate electrode of a partially completed device. The method further provides etching the upper portion of the dielectric layer overlying the gate electrode to form a recessed region. A step of coding or implanting is then performed to change the device from enhancement mode into depletion mode, thereby providing the ROM code for the designated cell.

Abstract: A MIS device comprising a pair of first doped layers of a second conductivity type forming source/drain regions in a semiconductor base structure of a first conductivity type, and a gate electrode formed in a region between the first doped layers of the second conductivity type on a gate insulating film formed on the semiconductor base structure having a three-layer structure consisting of a second doped layer of the first conductivity type, a third doped layer of the second conductivity type and a fourth doped layer of the first conductivity type having an impurity concentration higher than that of the semiconductor base structure, which are formed in that order in the direction of depth from the surface of a channel region extending between the source/drain regions, the thickness of the third doped layer is determined so that the third doped layer is depleted by the respective built-in potentials of pn junctions formed by the second doped layer and the third doped layer and by the fourth doped layer and the

Abstract: The present invention provides a more stable SRAM cell by reducing the backgate biased threshold voltage of the SRAM's select transistor. In some embodiments, masking layers are used during dopant implantation of the select transistors to minimize the net dopant concentration in the select transistor's channel region. Minimizing this net dopant concentration lowers the backgate biased threshold voltage of the select transistor without any reduction in its on-resistance. Another embodiment may be used to achieve increased stability for SRAM cells formed with CMOS technology. The masking layers used to form N-type and P-type well regions are overlapped such that a third well formed intermediate the N-type and P-type wells has a dopant concentration equal to the net concentrations of the respective N-type and P-type wells. This third well, therefore, may be used as discussed above to achieve a lower backgate biased threshold voltage.

Abstract: A semiconductor integrated device having a current regulating diode may be substantially reduced in size and improved in performance by forming the current regulating diode of a plurality of MOS transistors each having a gate, a drain region, and a source region formed in a semiconductor substrate, the source regions and the substrate regions being electrically coupled to each other, the drain regions of at least two of the MOS transistors being electrically coupled, and the source regions of each of the MOS transistors being electrically coupled, the coupled drain regions, the coupled source regions, and the coupled gates forming a drain terminal, a source terminal and a gate terminal, respectively. In order to set a desired regulated current, selected coupling lines in the current regulating diode may be cut.

Abstract: A ROM semiconductor device and a method of manufacturing that device on a semiconductor substrate comprises the steps of forming a blanket word line layer over the device with a reverse word line mask over the word line layer, the word line mask comprising a parallel array of mask strips, forming a ROM code mask over the reverse word line mask, the ROM code mask having a ROM code opening centered between a pair of the mask strips. A code implant dopant is ion implanted through the ROM code opening down into a doped region in the substrate below the ROM code opening. The ROM code mask is removed. A word line mask is formed comprising complementary mask strips between the mask strips of the reverse word line mask followed by removal of the reverse word line mask, etching the word line layer to form a parallel array of word lines beneath the complementary mask strips, and forming a blanket layer of dielectric material over the device.

Abstract: A depletion type transistor formed on a semiconductor substrate includes a drain region and a source region formed in distinct areas on the substrate. An inversion layer is formed in the surface area between the drain and the source regions. The transistor further includes two insulated gates: a floating gate located above the substrate and insulated from the inversion layer by an insulating layer in such a way as to cover the inversion layer, and a control gate provided above the floating gate and insulated from the floating gate by the insulating layer.

Abstract: A MOSFET transistor device with a gate formed over a lightly doped semiconductor substrate with a gate, and a source region and a drain region. V.sub.T1 ions are uniformly implanted into the surface of the substrate forming a V.sub.T region with substantially uniform doping in the upper portion of the substrate near the surface thereof. A gate oxide layer is formed on the substrate. A gate conductor is deposited over the gate oxide layer. A large angle implant is implanted into the region of the device over the source region. Then ions are implanted to form the source and drain regions which are self-aligned with the gate.

Abstract: A semiconductor device manufactured by the process including a semiconductor substrate, which comprises the steps of forming buried bit lines below the surface of said semiconductor substrate forming individual source and drain regions; forming a gate oxide layer on the surface of the substrate; forming a first conductive structure on the gate oxide layer; forming an insulating structure in contact with the first conductive structure; removing material from the surface of the first conductive structure to expose at least a portion of the surface beneath the first conductive structure; and forming on the remaining structure on the semiconductor substrate metal line structures having edges vertically aligned with and above the source and drain regions in the buried bit lines; whereby a compound conductive structure is provided on the semiconductor substrate.