Abstract: A CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. The architecture of the present invention can be utilized with the n-well, p-well, or dual-well processes. For example, a preferred embodiment of the present invention is described relative to a p-well process wherein the p-well is formed in an n-type substrate. A network of NMOS transistors is formed in the p-well, and a network of PMOS transistors is formed in the n-type substrate. A contact is electrically coupled to the p-well region and is coupled to first means for independently controlling the voltage in the p-well region. Another contact is electrically coupled to the n-type substrate and is coupled to second means for independently controlling the voltage in the n-type substrate.

Abstract: Second insulating films of gate insulating films each are composed of a high-permittivity dielectric film having a relative dielectric constant of 8 or more and at least one of the high-permittivity dielectric films constituting the second insulating films is doped with at least one kind of impurity metal ions. The valence number of the impurity metal ions differs by 1 from that of metal ions constituting the high-permittivity dielectric films. Due to this doping, at least one of the density and polarity of charged defects in the high-permittivity dielectric films differs between the second insulating films. The threshold voltage of each MISFET is controlled independently.

Abstract: A silicon-on-insulator semiconductor device and manufacturing method therefor is provided in which a single wafer die contains a transistor over an insulator layer to form a fully depleted silicon-on-insulator device and a transistor formed in a semiconductor island over an insulator structure on the semiconductor wafer forms a partially depleted silicon-on-insulator device.

Abstract: A semiconductor device for use in a memory cell includes an active matrix provided with a semiconductor substrate, transistors formed on the semiconductor substrate, an insulating layer formed over the transistors and the semiconductor substrate, and a contact hole electrically connected to the transistors, a first ruthenium (Ru) layer formed over the contact hole and upon the insulating layer, and a second Ru layer with a rugged surface formed on top of the first Ru layer.

Abstract: The claimed invention relates to a semiconductor device and a method of fabricating the semiconductor device. More particularly, the claimed invention relates to a method of fabricating the semiconductor device in which parts of a gate electrode at the ends of a channel are lightly doped compared to the center part of the gate electrode, thereby eliminating a hump on a subthreshold current slope. To achieve the objects of the claimed invention, there is provided a semiconductor device that includes a semiconductor substrate divided into an isolation region and an active region. A gate oxide film is formed on a first upper surface of the active region. A gate electrode is formed on a second upper surface of the gate oxide film, the gate electrode having a first part and a second part. The first part is more lightly doped with impurities than the second part. A channel is formed in an upper end of the active region proximate the gate electrode.

Abstract: A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region.

Abstract: A capacitive element C1 having a small leakage current is formed by utilizing a gate oxide film 9B thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element C1 has a gate electrode 10E. A part of the gate electrode 10E is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the capacitive element may reliably operate even at a low power-supply voltage.

Abstract: An n-channel type MIS field effect transistor is fabricated on a p-type well defined in a standard p-type silicon substrate, and is expected to respond to a high-frequency signal, wherein a heavily-doped p-type well contact region is formed outside of the p-type well for increasing the substrate resistance, and a capacitor is coupled to the heavily-doped p-type well contact region for increasing the impedance so that the insertion loss is reduced by virtue of the large impedance of the silicon substrate.

Abstract: The present invention employs a scanned atomic force probe to physical incorporate impurity atoms (dopant or bandgap) into a semiconductor substrate so that the impurity atoms have high resolution and improved placement. Specifically, the method of the present invention comprising a step of physically contacting a semiconductor surface having a layer of a dopant/bandgap source material thereon such that upon said physical contact impurity atoms from the dopant/bandgap source material are driven into the semiconductor substrate.

Abstract: Performance for a gate insulation film of an insulated gate transistor is enhanced. A depletion layer is generated in a region of a gate electrode 12 which is provided in contact with a gate insulation film 4 in an OFF state, and the depletion layer disappears or a width thereof is reduced in an ON state.

Abstract: An enhancement mode semiconductor device has a barrier layer disposed between the gate electrode of the device and the semiconductor substrate underlying the gate electrode. The barrier layer increases the Schottky barrier height of the gate electrode-barrier layer-substrate interface so that the portion of the substrate underlying the gate electrode operates in an enhancement mode. The barrier layer is particularly useful ill compound semiconductor field effect transistors, and preferred materials for the barrier layer include aluminum gallium arsenide and indium gallium arsenide.

Abstract: A gate electrode is buried in a trench formed in the main surface of a semiconductor substrate and faces a counter doped layer, and source/drain layers are formed on both sides of the trench. Thus the source/drain layers are formed in shallower areas than the counter doped layer. As a result, the punch-through resistance is improved.

Abstract: A semiconductor device which is capable of operating with a single positive power supply and has a low gate resistance, and a process for production thereof.

Abstract: An n-channel metal-insulator-semiconductor field-effect transistor (MISFET) that exhibits negative differential resistance in its output characteristic (drain current as a function of drain voltage) is disclosed. For a fixed gate voltage, the MISFET channel current, which flows between the drain and source terminals of the transistor, firstly increases as the drain-to-source voltage increases above zero Volts. Once the drain-to-source voltage reaches a pre-determined level, the current subsequently decreases with increasing drain-to-source voltage. In this region of operation, the device exhibits negative differential resistance, as the drain current decreases with increasing drain voltage. The drain-to-source voltage corresponding to the onset of negative differential resistance is also tunable. In addition, the drain current and negative differential resistance can be electronically tailored by adjusting the gate voltage.

Abstract: A semiconductor device includes a semiconductor layer structure, and gate, drain and source electrodes provided on the semiconductor layer structure, the gate electrode being located between the drain and source electrodes. A depletion modulating part is located between the gate electrode and the drain electrode and includes portions spaced apart from each other in a gate-width direction.

Abstract: The present invention provides a semiconductor device that has reduced a short-channel effect by preventing the effective channel length at the sides of a channel of a transistor from decreasing by forming the length of a gate electrode to be different according to the parts. The semiconductor device according to the present invention includes a semiconductor substrate including active regions where a semiconductor device is to be fabricated and isolation regions for electrically isolating the active regions. A gate electrode is formed to go across the active region. A source and a drain are formed in the active region at both sides of the gate electrode, wherein the length of the gate electrode on the upper surface of the sides of the active region is longer than the length of the gate electrode of the center of the active region.

Abstract: ESD protection devices and methods to form them are provided in this invention. By employing the thin gate oxide fabricated by a dual gate oxide process, ESD protection devices with a lower trigger voltage are provided. The NMOS for ESD protection according to the present invention has islands with thin gate oxides and a control gate with a thick gate oxide. These islands overlap the drain region of the NMOS to reduce the breakdown voltage of the PN junction in the drain region, thereby reducing the ESD trigger voltage and improving the ESD protection level of the NMOS. Furthermore, the invention is applicable to general integrated-circuit processes as well as various ESD protection devices.

Abstract: A semiconductor device has source and drain regions, a gate insulating film, a gate electrode, and a channel region. The channel region includes a region where carriers move between the source and drain regions. An impurity concentration of the channel region is higher at an end portion of a surface depletion layer than at an interface between the semiconductor layer and the gate insulating film. The impurity concentration varies along a direction in which the gate electrode, the gate insulating film and the channel region are successively provided, and it increases substantially linearly near the end portion of the surface depletion layer.

Abstract: The present invention provides an improved lateral drift region for both bipolar and MOS devices where improved breakdown voltage and low ON resistance are desired. A top gate of the same conductivity type as the device region with which it is associated is provided along the surface of the substrate and overlying the lateral drift region. This top gate includes a higher doped region that does not deplete during reverse biasing. Because this region does not deplete the hot carriers flowing through it lose energy and therefore are less likely to be trapped by interface traps at the insulator oxide interface or in the bulk dielectric. Avoiding carrier trapping allows maintenance of a stable threshold voltage for the MOS device.

Abstract: A high-voltage MOS transistor is produced in a low-voltage CMOS process without adding extra process steps for producing the high-voltage MOS For. The high-voltage MOS transistor is to be used as an analog line driver and is produced on tho same silicon area as low voltage AD/DA-converters. Hereby, the low-voltage and the high-voltage design block are directly compatible with each other, e.g. have the same threshold voltages, which simplifies the design of the total solution.

Abstract: A method to form asymmetric MOS transistors using a replacement gate design. The method involves forming implanted regions (140) and (145) in the channel region after removal of the replacement gate structure (110) to produce high threshold voltage regions and low threshold voltage regions.

Abstract: A field effect transistor is disclosed having a relatively high doped region (of the same type dopant as the channel) to reduce the change in the depletion region within the channel with changes in the drain voltage (Vd). Changes in the drain current (Id) with changes in the drain voltage (Vd) is a cause of non-linearity for traditional MOSFET. Because of the additional higher doped region provided in the channel, the depletion region within the higher doped region changes less with changes in the drain voltage (Vd). The higher doped region is situated near the top of the channel, where most of the drain current flows. Thus, the higher doped region dominates the drain current through the device. Since the drain current is less susceptible to changes in drain voltage (Vd), a more linear device results.

Abstract: A charge trapping structure for use with an n-channel metal-insulator-semiconductor field-effect transistor (MISFET) is disclosed. A dielectric layer is formed close to a channel region of the MISFET, and includes a number of trapping sites which are arranged and have a concentration sufficient to temporarily store energetic electrons induced by an electric field to move from the channel into the trapping sites. The trapped electrons set up a counter field that depletes the channel of carriers, and as a bias voltage across the channel increases, the device exhibits negative differential resistance (NDR). The charge trapping structure, as well as the rest of the device, are formed using conventional CMOS processing techniques.

Abstract: A solid state imaging apparatus includes a detection capacitor storing a signal charge, and an output amplifier including a plurality of transistors, and outputting the signal charge stored in the detection capacitor as a voltage signal. A gate electrode of one of the plurality of transistors as an input transistor is connected to the detection capacitor. Also, the plurality of transistors other than the input transistor has a thinner gate insulating film than the input transistor.

Abstract: An integrated circuit and method of fabricating integrated circuits is provided for an integrated circuit having threshold voltage adjustment. Unlike conventional methods and devices, threshold voltage adjustment is provided by an inert ion implantation process whereby inert ions are implanted into an underlying substrate. The implantation forms a semi-insulative layer comprised of an accumulation of inert ions. The inert ion region is formed between source and drain regions of a device on the integrated circuit. During operation of the device, the accumulation region confines the depth of the depletion layer. By confining the depth of the depletion layer, the threshold voltage of the device is reduced.

Abstract: A method of manufacturing a semiconductor device comprising the steps of forming a dummy film and a dummy gate pattern at a predetermined gate-forming region on a semiconductor substrate, forming a first side wall insulating film on a side wall of the dummy gate pattern, forming an interlayer insulating film on a portion of the semiconductor substrate around the dummy gate pattern bearing the first side wall insulating film, forming a groove by removing the dummy gate pattern, removing a portion of dummy film exposed through the groove while leaving a portion of the first side wall insulating film as well as a portion of the dummy film disposed below the portion of the first side wall insulating film, forming a gate insulating film at least on a bottom surface of the groove, and forming a gate electrode on the gate insulating film formed in the groove.

Abstract: A capacitive element C1 having a small leakage current is formed by utilizing a gate oxide film 9B thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element C1has a gate electrode 10E. A part of the gate electrode 10E is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the capacitive element may reliably operate even at a low power-supply voltage.

Abstract: A semiconductor device according to the present invention includes a semiconductor substrate; device isolation regions provided in the semiconductor substrate; a first conductivity type semiconductor layer provided between the device isolation regions; a gate insulating layer provided on an active region of the first conductivity type semiconductor layer; a gate electrode provided on the gate insulating layer; gate electrode side wall insulating layers provided on side walls of the gate electrode; and second conductivity type semiconductor layers provided adjacent to the gate electrode side wall insulating layers so as to cover a portion of the corresponding device isolation region, the second conductivity type semiconductor layers acting as a source region and/or a drain region. The gate electrode and the first conductivity type semiconductor layer are electrically connected to each other.

Abstract: An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 &mgr;m deep into the body material but not more than 0.1 &mgr;m deep into the body material. The source/drain zones (140 and 142 or 160 and 162) of a p-channel IGFET (120 or 122) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed.

Abstract: A transistor structure is provided for ESD protection in an integrated circuit device. A semiconductor substrate has source and drain diffusion regions and respective source and drain wells under the source and drain diffusion regions. A shallow trench isolation formed over the semiconductor substrate and into the semiconductor substrate separates the source and drain diffusion regions and a portion of the source and drain wells. Source and drain contact structures respectively formed on the shallow trench isolation over the source and drain diffusion regions and extend through the shallow trench isolation to contact the source and drain diffusion regions. An ion implantation is performed through the contact openings into the bottoms of the source and drain wells to control the device trigger voltage and position the discharge current far away from the surface, which increases the device ESD performance significantly.

Abstract: A method of manufacturing a semiconductor device comprising the steps of forming a dummy film and a dummy gate pattern at a predetermined gate-forming region on a semiconductor substrate, forming a first side wall insulating film on a side wall of the dummy gate pattern, forming an interlayer insulating film on a portion of the semiconductor substrate around the dummy gate pattern bearing the first side wall insulating film, forming a groove by removing the dummy gate pattern, removing a portion of dummy film exposed through the groove while leaving a portion of the first side wall insulating film as well as a portion of the dummy film disposed below the portion of the first side wall insulating film, forming a gate insulating film at least on a bottom surface of the groove, and forming a gate electrode on the gate insulating film formed in the groove.

Abstract: A field effect transistor (300) having a source region (304) and a drain region (306) includes a source side halo region (332) formed at a junction between the source region and a channel region to substantially interrupt off state leakage current. The source side halo region is formed by implanting (408) first doping ions near the surface at the source side of the channel and implanting (410) second doping ions deeper in the channel, near the depth of a source extension (322). In this manner, optimization of leakage current of the field effect transistor is made independent of the drive current of the field effect transistor.

Abstract: A semiconductor memory device includes an SOI substrate, a plurality of word lines, a plurality of bit line pairs, a plurality of memory cells and a plurality of body fixing lines. The plurality of word lines are disposed in the row direction on the SOI substrate. The plurality of bit line pairs are disposed in the column direction on the SOI substrate. The plurality of memory cells are located on the SOI substrate and each are disposed correspondingly to one of crossings between the plurality of word lines and the plurality of bit line pairs. Each of the plurality of memory cells includes a capacitor and a transistor. The transistor is connected between the capacitor and one bit line in the corresponding bit line pair. The transistor is turned on in response to the potential of the corresponding word line. The plurality of body fixing lines are disposed on the SOI substrate. The plurality of body fixing lines are supplied with a predetermined potential.

Abstract: In a MOS semiconductor device including a normal MOS transistor and an output MOS transistor for an input/output buffer, the normal MOS transistor is formed in a normal well. In an output MOS transistor, the channel region of the second MOS transistor and an element isolation region are formed in the region of a higher impurity concentration. On the other hand, the source and drain regions are formed in a lower impurity concentration region. Thereby, the source/drain capacitance of the output MOS transistor may be reduced, and the input/output capacitance of the semiconductor device may be reduced.

Abstract: A p-type MOSFET having very shallow p-junction extensions. The semiconductor device is produced on a substrate by creating a layer of implanted nitrogen ions extending from the substrate surface to a predetermined depth preferably less than about 800 Å. The gate electrode serves as a mask so that the nitrogen implantation does not filly extend under the gate electrode. Boron is also implanted to an extent and depth comparable to the nitrogen implantation thereby forming very shallow p-junction extensions that remain confined substantially within the nitrogen layer even after thermal treatment. There is thus produced a pMOSFET having very shallow p-junction extensions in a containment layer of nitrogen and boron in the semiconductor material.

Abstract: A protective circuit includes a pair of diodes to protect the gate dielectric of an insulated-gate semiconductor device from over-voltage conditions, such as can occur during plasma etch manufacturing processes. The diodes are either anode- or cathode-coupled, and are connected between the gate of the device and bulk ground. Because of their opposing polarities, one of the diodes is always reverse-biased regardless of whether a positive or negative control voltage is applied to the gate of the device. As a result, the protective circuit imposes no operational restrictions on normal control voltages. At the same time, the circuit limits any plasma-induced charge buildup that can arise during manufacturing. If the gate voltage rises, a first of the two diodes is reverse biased and prevents the protective circuit from conducting. When the gate voltage reaches the reverse breakdown voltage of the first diode (plus the small forward voltage drop of the second diode), both diodes begin to conduct.

Abstract: A lateral high-voltage transistor has a semiconductor body made of a lightly doped semiconductor substrate of a first conductivity type and an epitaxial layer of a second conductivity type. The epitaxial layer is provided on the semiconductor substrate. The lateral high-voltage transistor has a drain electrode, a source electrode, a gate electrode and a semiconductor zone of the first conductivity type which is provided under the gate electrode and is embedded in the epitaxial layer. Between the source electrode and the drain electrode trenches are provided in lines and rows in the semiconductor layer. The walls of the trenches are highly doped with dopants of the first conductivity type.

Abstract: A capacitor structure (10) is implemented in an integrated circuit chip (11) along with other devices at the device level in the chip structure. The capacitor structure includes an elongated device body (17) formed from a first semiconductor material. This device body (17) is bordered on both lateral sides by lateral regions (20, 22) formed from a second semiconductor material. A dielectric layer (28) overlays both lateral regions (20, 22) and the device body (17), while an anode layer (30) overlays the dielectric layer in an area defined by the device body. Each lateral region (20, 22) is coupled to ground at a first end (25) of the elongated device body (17). The anode (30) is coupled to the chip supply voltage at a second end (33) of the device body opposite to the first end. The entire structure is designed and dimensioned to form an area-efficient and high-frequency capacitor.

Abstract: An integrated semiconductor logic gate apparatus having optimized asymmetric channel regions and method for fabricating the apparatus is disclosed. The fabrication process includes ion-implanting the drain side of the channel to produce asymmetric channels on the gate transistors by using a criss-cross form of ion implantation. The criss-cross ion-implantation is performed after formation of the multiple gate stacks and is facilitated by a patterned photoresist mask that leaves an open, unprotected region above adjacent gate stacks through which the ion-implantation is performed. The criss-cross ion-implantation includes two tilt angles that are determined by tangent expressions that factor the height of the photoresist mask, the width of the unprotected opening over pairs of gate stacks and the width of the channel regions, including a distance relating to the point where the source/drain potential barrier is a minimum beneath the overlying gate stack.

Abstract: The present invention is drawn to a semiconductor integrated circuit device employing on the same silicon substrate a plurality of kinds of MOS transistors different in magnitude of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of two power supply units.

Abstract: Methods of forming field effect transistors and resultant field effect transistor circuitry are described. In one embodiment, a semiconductive substrate includes a field effect transistor having a body. A first resistive element is received by the substrate and connected between the transistor's gate and the body. A second resistive element is received by the substrate and connected between the body and a reference voltage node. The first and second resistive elements form a voltage divider which is configured to selectively change threshold voltages of the field effect transistor with state changes in the gate voltage. In a preferred embodiment, first and second diode assemblies are positioned over the substrate and connected between the gate and body, and the body and a reference voltage node to provide the voltage divider.

Abstract: A manufacturing method produces a semiconductor IC device which can maintain a low power consumption for electronic circuits and form gate-isolation layers of different thicknesses without increasing the manufacturing cost. The semiconductor IC device has gate-isolation layers of different thicknesses on the same semiconductor substrate surface. To form such gate-isolation layers, a silicon dioxide layer is formed in first and second regions. The dopant-concentration is adjusted in silicon dioxide layer that is to have a thickness different from the above silicon dioxide layer thickness in the second region B. A carbon-containing semiconductor layer is selectively formed in either the first region or the second region. Therefore, there is no need for additional steps for forming silicon dioxide layers of different thicknesses in the first region and in the second region.

Abstract: The threshold voltages of transistors are set by controlling the amount of overlap in the direction of channel length between a channel region and a source region and the amount of overlap in the direction of channel length between the channel region and a drain region, whereby, in a semiconductor integrated circuit device in which transistors having different threshold voltages or different channel widths are mounted together, the ion injection conditions for the channel regions can be shared, thereby reducing the number of masks and the number of processing steps.

Abstract: An integrated circuit arrangement having two NMOS transistors with different cut off voltages and two PMOS transistors with different cut off voltages. Channel regions of the NMOS transistors exhibit the same dopant concentration. The analogous case applies to the PMOS transistors. The different cut off voltages are achieved by different chemical compositions of the gate electrodes of the transistors. Preferably, the chemical compositions of the gate electrodes of respectively one of the NMOS transistors and one of the PMOS transistors thereby coincide. Si1−xGex with 0≦x≦1 is suitable as a material for the gate electrodes. The transistors preferably form pairs with transistors complementary to one another that exhibit the same cut off voltages. Given a dopant concentration of the channel regions of the NMOS transistors that is approximately 1.5 times greater than a dopant concentration of the channel regions of the PMOS transistors, the value of x amounts, for example, to 0.

Abstract: A transistor of the integrated MOS type with a high threshold voltage and low multiplication coefficient is formed in a chip that includes a substrate and defining an active area delimited by field oxide regions. The active area partially houses a tub having the same type of conductivity as the substrate and a greater doping level. In particular, the tub occupies a first half of the active area, while a second half of the active area is formed directly by the substrate. A gate region is present above the substrate and is isolated from the substrate by means of a gate oxide layer. The gate region is arranged partially above the second half of the active area and partially above the tub. The transistor also comprises a source region, which is formed in the tub on a first side of the gate region, and a drain region, which is arranged in the second half of the active area, on a second side of the gate region.

Abstract: The invention relates to a SOI deep depletion MOS transistor provided in a thin silicon layer (5) adjoining a surface (4) of a silicon body (3) and insulated from a silicon substrate (7) by a buried oxide layer (6). The channel region (13) of a first conductivity type is provided with at least one and preferably a plurality of zones (16) of the opposite conductivity type adjoining the surface to remove minority carriers from the interface between the channel and the gate oxide (15). The zones (16) extend across the whole thickness of the channel and adjoin the buried oxide at the side of the channel remote from the gate dielectric. Due to this construction, minority carriers are removed also from the rear side of the channel. This enables the transistor to be operative also at high voltages having values at which the substrate and the buried oxide operate as a second gate and as a second gate dielectric, respectively.

Abstract: The invention relates to a high-voltage deep depletion transistor, provided in a semiconductor body (1) having a substrate (2) of a first conductivity type, for example the p-type, and a surface layer (3) of the opposite conductivity type, for example the n-type for an n-channel transistor. To prevent formation of inversion layers below the gate, the channel is subdivided into a plurality of sub-channel regions (7a, 7b, 7c, 7d) mutually separated by p-type regions (11a, 11b, 11c, 11d) which serve to remove generated holes. The p-type regions extend across the whole thickness of the channel and are contacted via the substrate. Each sub-channel region may be subdivided further by intermediate p-type regions (13) to improve the removal of holes.

Abstract: In a semiconductor device comprising a MOS transistor driven at a relatively low voltage and a MOS transistor driven at a relatively high voltage formed on the same semiconductor substrate, the MOS transistor driven at the relatively high voltage comprises: a first active region of a first conductivity type in the semiconductor substrate; a first gate oxide film formed on the first active region and having increased thickness at the edge regions thereof than in the central region thereof in the direction of current flow; and a first electrode formed on the first gate oxide film and doped at a relatively low concentration with an impurity of a second conductivity type which is opposite to the first conductivity type; and the MOS transistor driven at the relatively low voltage comprises: a second active region of a first conductivity type in the semiconductor substrate; a second gate oxide film formed on the second active region; and a second electrode formed on the second gate oxide film and doped at a relativ

Abstract: A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region.

Abstract: When the threshold voltage of a long-channel transistor is set during the same dopant step of a manufacturing process that sets the threshold voltage of a short-channel transistor, the threshold voltage of the long-channel transistor is increased by connecting the long-channel transistor in series with a schottky diode.