Abstract: A process for forming defect-free source and drain extensions for a MOSFET built on a germanium based channel region deposits a first silicon germanium layer on a semiconductor substrate, deposits a gate dielectric layer on the silicon germanium layer, and deposits a gate electrode layer on the gate dielectric layer. A dry etch chemistry etches those layers to form a gate electrode, a gate dielectric, and a silicon germanium channel region on the semiconductor substrate. Next, an ion implantation process forms halo implant regions that consume portions of the silicon germanium channel region and the semiconductor substrate. Finally, an in-situ doped epitaxial deposition process grows a pair of silicon germanium layers having LDD regions. The silicon germanium layers are adjacent to the silicon germanium channel region and the halo implant regions do not damage any portion of the silicon germanium layers.

Abstract: Provided are a metal oxide semiconductor (MOS) transistor and a complementary MOS (CMOS) transistor each having a strained channel epi layer, and methods of fabricating the transistors. The MOS transistor may include at least one active region defined by an isolation structure formed in a substrate. At least one channel trench may be formed in a part of the at least one active region. At least one strained channel epi layer may be in the at least one channel trench. At least one gate electrode may be aligned on the at least one strained channel epi layer. Sources/drains may be arranged in the at least one active region along both sides of the at least one strained channel epi layer.

Abstract: A MOS transistor and a method for manufacturing the transistor are disclosed. The method for manufacturing the MOS transistor may include successively stacking a pad oxide layer and a mask layer on a semiconductor substrate, patterning the pad oxide layer and the mask layer, to expose a trench forming region of the semiconductor substrate, forming a trench in the semiconductor substrate by etching the exposed trench forming region, and forming an anti-diffusion layer and an oxide layer over the entire surface of the semiconductor substrate including the trench. This method can reduce leakage current, among other things, resulting in improved characteristics of transistor products.

Abstract: A semiconductor transistor structure with increased mobility in the channel zone and a method of its fabrication are described. A semiconductor substrate having a first dopant is formed. A diffusion barrier layer having a second dopant is formed on the semiconductor substrate to suppress outdiffusion of the first dopant. Next, a semiconductor layer having substantially low dopant concentration relative to the first layer is epitaxially grown on the diffusion barrier layer. The semiconductor layer defines a channel in the semiconductor transistor structure. The low dopant concentration in the semiconductor layer increases the mobility of the carriers in the channel of the semiconductor transistor structure. A gate electrode and a gate dielectric are formed on the semiconductor layer with the low dopant concentration.

Abstract: A semiconductor device and the methods of forming the same are provided. The semiconductor device includes a low energy band-gap layer comprising a semiconductor material; a gate dielectric on the low energy band-gap layer; a gate electrode over the gate dielectric; a first source/drain region adjacent the gate dielectric, wherein the first source/drain region is of a first conductivity type; and a second source/drain region adjacent the gate dielectric. The second source/drain region is of a second conductivity type opposite the first conductivity type. The low energy band-gap layer is located between the first and the second source/drain regions.

Abstract: A method for smoothing variations in threshold voltage in an integrated circuit layout. The method begins by identifying recombination surfaces associated with transistors in the layout.

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that employ high-k dielectric layers. An n-type well region (304) is formed within a semiconductor body (302). A threshold voltage adjustment implant is performed by implanting a p-type dopant into the n-type well region to form a counter doped region (307). A high-k dielectric layer (308) is formed over the device (300). A polysilicon layer (310) is formed on the high-k dielectric layer and doped n-type. The high-k dielectric layer (308) and the polysilicon layer (310) are patterned to form polysilicon gate structures. P-type source/drain regions (306) are formed within the n-type well region (304).

Abstract: By providing a self-biasing semiconductor switch, an SRAM cell having a reduced number of individual active components may be realized. In particular embodiments, the self-biasing semiconductor device may be provided in the form of a double channel field effect transistor that allows the formation of an SRAM cell with less than six transistor elements and, in preferred embodiments, with as few as two individual transistor elements.

Abstract: A semiconductor device includes a first semiconductor layer, and a first insulated-gate field-effect transistor of a first conductivity type that is provided in a major surface region of the first semiconductor layer. The semiconductor device further includes an electrostrictive layer that is provided on a back surface of the first semiconductor layer and applies a first stress along a channel length to a channel region of the first insulated-gate field-effect transistor when the first insulated-gate field-effect transistor is operated.

Abstract: The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.

Abstract: Semiconductor devices and methods of manufacturing the same are disclosed. A disclosed semiconductor device comprises a semiconductor substrate; a gate formed on the semiconductor substrate; a gate oxide layer interposed between the semiconductor substrate and the gate; and source and drain regions formed within the substrate at opposite sides of the gate. The gate oxide layer has a first region with a first thickness and a second region with a second thickness. The second thickness is thicker than the first thickness.

Abstract: Some embodiments of the present invention provide high voltage transistors including a semiconductor substrate and a device isolation film defining an active region in the semiconductor substrate. A gate electrode extends along a central portion of the active region while maintaining a predetermined width on the semiconductor substrate. A second well is formed on both sides of the gate electrode in the semiconductor substrate, and partially extends to a bottom surface of the device isolation film. The active region in the semiconductor substrate comprises a first active region disposed under the gate electrode, and separating the device isolation film and a second active region defined by the first active region and the device isolation film. Methods of manufacturing high voltage transistors are also provided.

Abstract: In FET, a second nitride semiconductor layer is provided on a first nitride semiconductor layer, and a source electrode and a drain electrode are each provided to have at least a portion thereof in contact with the second nitride semiconductor layer. A concave portion is formed in the upper surface of the second nitride semiconductor layer to be located between the source electrode and the drain electrode. A gate electrode is provided over the concave portion to cover the opening of the concave portion.

Abstract: The present invention discloses a method of optimizing threshold voltage of P-type MOS transistor, including: providing a semiconductor substrate; forming a P-type MOS transistor on the semiconductor substrate; and performing a second N-type ion implantation in the source and drain extension regions. A P-type MOS transistor and a method for forming the same are also provided, the method includes: providing a semiconductor substrate including a region I and a region II being concentric with the region I and occupying 15% to 25% of the area of the whole semiconductor substrate; forming a P-type MOS transistor on the semiconductor substrate; and performing a second N-type ion implantation in the source and drain extension regions of the region II. Therefore, the reduction in threshold voltage of the P-type MOS transistors in region II of the semiconductor substrate is suppressed.

Abstract: A semiconductor field effect transistor can be used with RF signals in an amplifier circuit. The transistor includes a source region and a drain region with a channel region interposed in between the source and drain regions. The transistor is structured such that the threshold voltage for current flow through the channel region varies at different points along the width direction, e.g., to give an improvement in the distortion characteristics of the transistor.

Abstract: Structures and a method for detecting ionizing radiation using silicon-on-insulator (SOI) technology are disclosed. In one embodiment, the invention includes a substrate having a buried insulator layer formed over the substrate and an active layer formed over the buried insulator layer. Active layer may be fully depleted. A transistor is formed over the active layer, and includes a first gate conductor, a first gate dielectric and source/drain diffusion regions. The first gate conductor may include a material having a substantially (or fully) depleted doping concentration such that it has a resistivity higher than doped polysilicon such as intrinsic polysilicon. A second gate conductor is formed below the buried insulator layer and provides a second gate dielectric corresponding to the second gate conductor. A channel region between the first gate conductor and the second gate conductor is controlled by the second gate conductor (back gate) such that it acts as a radiation detector.

Abstract: Semiconductor devices and methods for fabricating the same are provided. An exemplary embodiment of a semiconductor device comprises a substrate with a plurality of isolation structures formed therein, defining first and second areas over the substrate. A transistor is formed on a portion of the substrate in the first and second areas, respectively, wherein the transistor in the second area is formed with merely a pocket doping region in the substrate adjacent to a drain region thereof. A first dielectric layer is formed over the substrate, covering the transistor formed in the first and second areas. A plurality of first contact plugs is formed through the first dielectric layer, electrically connecting a source region and a drain region of the transistor in the second area, respectively. A second dielectric layer is formed over the first dielectric layer with a capacitor formed therein, wherein the capacitor electrically connects one of the first contact plugs.

Abstract: A semiconductor device of this invention is a vertical power MOSFET having a plurality of first trenches where a trench gate is formed. It has a first column region of a second conductivity type placed beneath the first trenches and formed vertically in an epitaxial layer of a first conductivity type, and a second column region of the second conductivity type placed beneath a base region between the first trenches and formed vertically in the epitaxial layer of the first conductivity type. A sum of depletion charge in the first and the second column regions is substantially equal to depletion charge in the epitaxial layer of the first conductivity type.

Abstract: Semiconductor structures having a decreased semiconductor junction capacitance of a semiconductor junction within an active semiconductor layer may be fabricated using an ion implantation and thermal annealing method. The ion implantation and thermal annealing method provides for a plurality of voids located completely within the active semiconductor layer proximate to the semiconductor junction located within the active semiconductor layer, absent stressing of the active semiconductor layer.

Abstract: An n-type field effect transistor (NFET) and methods of forming a halo for an NFET to control the short channel effect are disclosed. One method includes forming a gate over a silicon substrate; recessing the silicon adjacent to the gate; forming a halo by epitaxially growing boron in-situ doped silicon germanium (SiGe) in the recess; and epitaxially growing silicon over the silicon germanium. Alternatively, the halo can be formed by ion implanting boron into an embedded SiGe region within the silicon substrate. The resulting NFET includes a boron doped SiGe halo embedded within the silicon substrate. The embedded SiGe layer may be a relaxed layer without inserting strain in the channel. The high solid solubility of boron in SiGe and low diffusion rate allows formation of a halo that will maintain the sharp profile, which provides better control of the short channel effect and increasing control over NFET threshold voltage roll-off.

Abstract: A semiconductor storage device has a single gate electrode formed on a semiconductor substrate through a gate insulation film. First and second memory function bodies formed on both sides of the gate electrode. A P-type channel region is formed in a surface of the substrate on the side of the gate electrode. N-type first and second diffusion regions are formed on both sides of the channel region. The channel region is composed of an offset region located under the first and second memory function bodies and a gate electrode beneath region located under the gate electrode. The concentration of a dopant which imparts a P-type conductivity to the offset region is effectively lower than the concentration of a dopant which imparts the P-type conductivity to the gate electrode beneath region. This makes it possible to provide the semiconductor storage device which is easily shrunk in scale.

Abstract: The present invention proposes a voltage-clipping device utilizing a pinch-off mechanism formed by two depletion boundaries. A clipping voltage of the voltage-clipping device can be adjusted in response to a gate voltage; a gap of a quasi-linked well; and a doping concentration and a depth of the quasi-linked well and a well with complementary doping polarity to the quasi-linked well. The voltage-clipping device can be integrated within a semiconductor device as a voltage stepping down device in a tiny size, compared to traditional transformers.

Abstract: A twin-cell type semiconductor memory device in which the area of a chip can be reduced. In the twin-cell type semiconductor memory device for storing data in at least one pair of memory cells as complementary information, memory cells are arranged at each of a plurality of word lines at intervals at which bit lines are located. At least the one pair of memory cells, which have stored the complementary information and which indicate a plurality of areas each connected to a pair of bit lines, form a twin cell.

Abstract: A high-reliable depletion-type MOS field-effect transistor as a process monitor is provided. A diode formed in polycrystalline silicon and a diode formed in a semiconductor substrate form a bi-directional diode. The bi-directional diode connects a gate electrode with the semiconductor substrate in the depletion-type MOS field-effect transistor through metal wirings.

Abstract: A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor includes a substrate with spaced-apart source and drain regions formed in the substrate and a channel region defined between the source and drain regions. A layer of gate oxide is formed over at least a part of the channel region with a gate formed over the gate oxide. The gate further includes at least one implant aperture formed therein with the channel region of the substrate further including an implanted region within the channel between the source and drain regions. Methods for forming the threshold voltage adjusted transistor are also disclosed.

Abstract: A new Insulated-Gate Field-Effect Thin Film Transistor (Gated-FET) is disclosed. A semiconductor thin film Gated-FET device, comprising: a lightly doped resistive channel region formed on a semiconductor thin film layer, the thickness of the channel comprising the entire thin film thickness; and an insulator layer deposited on said channel surface with a gate region formed on a gate material deposited on said insulator layer, said gate region receiving a gate voltage comprised of: a first level that modulate said channel resistance to a substantially non-conductive state by fully depleting majority carriers from said thin film layer in the channel region; and a second level that modulate said channel resistance to a substantially conductive state by at least partially accumulating majority carriers near the gate surface of the thin film layer in said channel region.

Abstract: A semiconductor structure is provided that includes a Vt stabilization layer between a gate dielectric and a gate electrode. The Vt stabilization layer is capable of stabilizing the structure's threshold voltage and flatband voltage to a targeted value and comprises a nitrided metal oxide, or a nitrogen-free metal oxide, with the proviso that when the Vt stabilization layer comprises a nitrogen-free metal oxide, at least one of the semiconductor substrate or the gate dielectric includes nitrogen. The present invention also provides a method of fabricating such a structure.

Abstract: This invention is characterized in that, a gate electrode 27F formed on a P-type well 3 via a gate oxide film 9, a high-concentration N-type source layer and a high-concentration N-type drain layer 15 respectively formed apart from the gate electrode and a low-concentration N-type source layer and a low-concentration N-type drain layer respectively formed so that they respectively surround the N-type source layer and the N-type drain layer 10 and respectively parted by a P-type body layer formed under the gate electrode 27F are provided.

Abstract: An apparatus and method for manufacturing metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, which MOS transistors are area efficient, and where the drive strength and leakage current of the MOS transistors is improved. The invention uses a dynamic threshold voltage control scheme that does not require a change to the existing MOS technology process. The invention provides a technique that controls the threshold voltage of the transistor. In the OFF state, the threshold voltage of the transistor is set high, keeping the transistor leakage to a small value. In the ON state, the threshold voltage is set to a low value, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS.

Abstract: In the case of using an analog buffer circuit, an input voltage is required to be added a voltage equal to a voltage between the gate and source of a polycrystalline silicon TFT; therefore, a power supply voltage is increased, thus a power consumption is increased with heat. In view of the foregoing problem, the invention provides a depletion mode polycrystalline silicon TFT as a polycrystalline silicon TFT used in an analog buffer circuit such as a source follower circuit. The depletion mode polycrystalline silicon TFT has a threshold voltage on its negative voltage side; therefore, an input voltage does not have to be increased as described above. As a result, a power supply voltage requires no increase, thus a low power consumption of a liquid crystal display device in particular can be realized.

Abstract: A semiconductor device able to secure electrical effective thicknesses required for insulating films of electronic circuit elements by using depletion of electrodes of the electronic circuit elements even if the physical thicknesses of the insulating films are not different, where gate electrodes of high withstand voltage use transistors to which high power source voltages are supplied contain an impurity at a relatively low concentration, so the gate electrodes are easily depleted at the time of application of the gate voltage; depletion of the gate electrodes is equivalent to increasing the thickness of the gate insulating films; the electrical effective thicknesses required of the gate insulating films can be made thicker; and the gate electrodes of high performance transistors for which a high speed and large drive current are required do not contain an impurity at a high concentration where depletion of the gate electrodes will not occur, so the electrical effective thickness of the gate insulating films

Abstract: A method for making circuit device that includes a first transistor having a first metal gate electrode overlying a first gate dielectric on a first area of a semiconductor substrate. The first gate electrode has a work function corresponding to the work function of one of P-type silicon and N-type silicon. The circuit device also includes a second transistor coupled to the first transistor. The second transistor has a second metal gate electrode over a second gate dielectric on a second area of the semiconductor substrate. The second gate metal gate electrode has a work function corresponding to the work function of the other one of P-type silicon and N-type silicon.

Abstract: A technique enabling to improve element isolation characteristic of a semiconductor device is provided. An element isolation structure is provided in a semiconductor substrate in which a silicon layer, a compound semiconductor layer and a semiconductor layer are laminated in this order. The element isolation structure is composed of a trench, a semiconductor film, and first and second insulating films. The trench extends through the semiconductor layer and extends to the inside of the compound semiconductor layer. The semiconductor film is provided on the surface of the trench, and the first insulating film is provided on the semiconductor film. The second insulting film is provided on the first insulating film and fills the trench.

Abstract: In one embodiment, a compound semiconductor vertical FET device (11) includes a first trench (29) formed in a body of semiconductor material (13), and a second trench (34) formed within the first trench (29) to define a channel region (61). A doped gate region (59) is then formed on the sidewalls and the bottom surface of the second trench (34). Source regions (26) are formed on opposite sides of the double trench structure (28). Localized gate contact regions (79) couple individual doped gate regions (59) together. Contacts (84,85,87) are then formed to the localized gate contact regions (79), the source regions (26), and an opposing surface (21) of the body of semiconductor material (13). The structure provides a compound semiconductor vertical FET device (11, 41, 711, 712, 811, 812) having enhanced blocking capability and improved switching performance.

Abstract: A field effect transistor includes a first semiconductor region forming a channel region, a gate electrode insulatively disposed above the first semiconductor region, source and drain electrodes formed to sandwich the first semiconductor region in a channel lengthwise direction, and second semiconductor regions formed between the first semiconductor region and the source and drain electrodes and having impurity concentration higher than the first semiconductor region. The thickness of the second semiconductor region in the channel lengthwise direction is set to a value equal to or less than depletion layer width determined by the impurity concentration so that the second semiconductor region is depleted in a no-voltage application state.

Abstract: A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.

Abstract: A power supply device includes a control IC fabricated by a bipolar process and a power supply element fabricated by a MOS process, both of them die-bonded on a leadframe, and with a chip edge of one of them kept in intimate contact with a chip edge of the other. Thus, heat conducts via those chip edges with increased efficiency, permitting the heat generated in the power supply element to quickly conduct to the control IC. This prevents heat-induced breakdown to which a MOS semiconductor is susceptible. The power supply element fabricated by a MOS process can be a horizontal structure so that a current flows from one part of the top surface of the chip to another. This makes it easy to reduce power loss. The power supply element and the control IC can be die-bonded with a single type of die-bonding paste.

Abstract: A transistor is formed with a source ballast resistor that regulates channel current. In an LDMOS transistor embodiment, the source ballast resistance may be formed using a high sheet resistance diffusion self aligned to the polysilicon gate, and/or by extending a depletion implant from under the polysilicon gate toward the source region. The teachings herein may be used to form effective ballast resistors for source and/or drain regions, and may be used in many types of transistors, including lateral and vertical transistors operating in a depletion or an enhancement mode, and BJT devices.

Abstract: The invention includes methods of forming circuit devices. A metal-containing material comprising a thickness of no more than 20 ? (or alternatively comprising a thickness resulting from no more than 70 ALD cycles) is formed between conductively-doped silicon and a dielectric layer. The conductively-doped silicon can be n-type silicon and the dielectric layer can be a high-k dielectric material. The metal-containing material can be formed directly on the dielectric layer, and the conductively-doped silicon can be formed directly on the metal-containing material. The circuit device can be a capacitor construction or a transistor construction. If the circuit device is a transistor construction, such can be incorporated into a CMOS assembly. Various devices of the present invention can be incorporated into memory constructions, and can be incorporated into electronic systems.

Abstract: A method of forming an abrupt junction device with a semiconductor substrate is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed on the semiconductor substrate adjacent the gate and the gate dielectric. A thickening layer is formed by selective epitaxial growth on the semiconductor substrate adjacent the sidewall spacer. Raised source/drain dopant implanted regions are formed in at least a portion of the thickening layer. Silicide layers are formed in at least a portion of the raised source/drain dopant implanted regions to form source/drain regions, beneath the silicide layers, that are enriched with dopant from the silicide layers. A dielectric layer is deposited over the silicide layers, and contacts are then formed in the dielectric layer to the silicide layers.

Abstract: A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities, whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region.

Abstract: A regular Schottky diode or a device that has a Schottky diode characteristic and an MOS transistor are coupled in series to provide a significant improvement in leakage current and breakdown voltage with only a small degradation in forward current. In the reverse bias case, there is a small reverse bias current but the voltage across the Schottky diode remains small due the MOS transistor. Nearly all of the reverse bias voltage is across the MOS transistor until the MOS transistor breaks down. This transistor breakdown, however, is not initially destructive because the Schottky diode limits the current. As the reverse bias voltage continues to increase the Schottky diodes begins to absorb more of the voltage. This increases the leakage current but the breakdown voltage is a somewhat additive between the transistor and the Schottky diode.

Abstract: In a semiconductor device of a polysilicon gate electrode structure having three or more different Fermi levels, a P type polysilicon having a lowest Fermi level is disposed on a first N type surface channel MOS transistor. A first N type polysilicon having a highest Fermi level is disposed on a second N type surface channel MOS transistor. A second N type polysilicon having an intermediate Fermi level between the highest and the lowest Fermi levels and doped with both an N type impurity and a P type impurity is disposed on a P channel MOS transistor.

Abstract: A MISFET in a semiconductor device has a gate insulating film provided on a substrate, a gate electrode provided on the gate insulating film, sidewalls provided on the side surfaces of the gate electrode, lightly doped diffusion layers provided in the respective regions of the substrate located below the edge portions of the gate electrodes, heavily doped diffusion layers provided in the respective regions of the substrate located laterally below the gate electrode and the sidewalls, and pocket diffusion layers covering the lower portions of the lightly doped diffusion layers and parts of the side surfaces thereof in overlapping relation with each other below the gate electrode. Impurity concentrations in the pocket diffusion layers are set such that the threshold of the MISFET has a desired value.

Abstract: The semiconductor device of this invention has a P type well region formed inside a P type semiconductor substrate, on which at least three gate insulating films each having a different thickness are formed. Also, the device has the gate electrode formed extending over the three gate insulating films. The ion implantation of the impurity for controlling the threshold voltage is performed only under the thinnest gate insulating film of the three gate insulating films.

Abstract: Provided is a manufacturing method of a semiconductor device which comprises forming, all over the surface of a substrate below the channel region of a MISFET, a p type impurity layer having a first peak in impurity concentration distribution and another p type impurity layer having a second peak in impurity concentration distribution, each layer having a function of preventing punch-through. Compared with a device having a punch through stopper layer of a pocket structure, the device of the present invention is suppressed in fluctuations in the threshold voltage. Moreover, with a relative increase in the controllable width of a depletion layer, a sub-threshold swing becomes small, thereby making it possible to prevent lowering of the threshold voltage and to improve a switching rate of the MISFET.

Abstract: A method for programming a read-only memory cell including a transistor whose source and drain, which have a second type of doping, are formed in a semiconductor substrate with a first type of doping, includes a step of carrying out a contradoping in a region of the source, the region being adjacent to the conduction channel 4, to make it a region with the first type of doping so as to prevent a transistor effect from occurring.

Abstract: Deterministically doped field-effect devices and methods of making same. One or more dopant atoms, also referred to as impurities or impurity atoms, are arranged in the channel region of a device in engineered arrays. Component atoms of an engineered array are substantially fixed by controlled placement in order to provide a barrier topology designed to control of source-drain carrier flow to realize an ultra-small device with appropriate, consistent performance characteristics. Devices can be made by placing atoms using proximity probe manipulation, ion implantation, by facilitating self-assembly of the atoms as necessary, or other techniques. These atomic placement techniques are combined in example embodiments with traditional methods of forming a substrate, insulators, gates, and any other structural elements needed in order to produce practical field-effect devices.

Abstract: Thin film transistor based three-dimensional CMOS inverters utilizing a common gate bridged between a PFET device and an NFET device. One or both of the NFET and PFET devices can have an active region extending into both a strained crystalline lattice and a relaxed crystalline lattice. The relaxed crystalline lattice can comprise appropriately-doped silicon/germanium. The strained crystalline lattice can comprise, for example, appropriately doped silicon, or appropriately-doped silicon/germanium. The CMOS inverter can be part of an SOI construction formed over a conventional substrate (such as a monocrystalline silicon wafer) or a non-conventional substrate (such as one or more of glass, aluminum oxide, silicon dioxide, metal and plastic).

Abstract: A CMOS based n-channel metal-insulator-semiconductor field-effect transistor (MISFET) that exhibits a useful negative differential resistance effect is disclosed. The resulting device can be incorporated into a number of useful applications, including as part of a memory device, a logic device, etc.