Abstract: A semiconductor device with a strained region is provided. The semiconductor device includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer, the second dielectric layer having a first fin disposed therein and an interface disposed proximate the first fin. The interface includes a first oxide region disposed in the first dielectric layer and a second oxide region disposed in the second dielectric layer. The interface induces strain in a region of the semiconductor device. A method of making a semiconductor device with a strained region is also provided.

Abstract: A semiconductor device that includes a gate structure on a channel region of a semiconductor device. Source and drain regions may be present on opposing sides of the channel region. The semiconductor device may further include a composite gate sidewall spacer present on a sidewall of the gate structure. The composite gate sidewall spacer may include a first composition portion having an air gap encapsulated therein, and a second composition portion that is entirely solid and present atop the first composition portion.

Abstract: Various embodiments provide semiconductor structures and methods for forming the same. In an exemplary method, a semiconductor substrate is provided. A first stop layer, a first sacrificial layer, a second stop layer, and a second sacrificial layer are formed sequentially on the semiconductor substrate. The second sacrificial layer, the second stop layer, the first sacrificial layer, the first stop layer, and the semiconductor substrate are etched to form a groove, the groove then being filled to form an isolation structure. The second sacrificial layer is removed to expose sidewalls and a top of an exposed portion of the isolation structure. The second stop layer is removed, and the exposed portion of the isolation structure is etched to reduce a width of the top of the exposed portion of the isolation structure. The first sacrificial layer is removed. A floating gate is formed on the first stop layer.

Abstract: A method of forming a gate structure over a hybrid substrate structure with topography having a bulk region and an SOI region is disclosed including forming a gate material layer above the SOI and bulk regions, forming a mask layer above the gate material layer, forming a first planarization layer above the mask layer, forming a first gate structure masking pattern above the first planarization layer, patterning the first planarization layer in alignment with the first gate structure masking pattern, and patterning the mask layer in accordance with the patterned first planarization layer, resulting in a gate mask disposed above the gate material layer.

Abstract: The present technology relates to a solid-state imaging device, manufacturing method of a solid-state imaging device, and an electronic device, which can provide a solid-state imaging device having further improved features such as reduced optical color mixing and the like. Also, an electronic device using the solid-state imaging device thereof is provided. According to a solid-state imaging device having a substrate 12 and multiple photoelectric converters 40 that are formed on the substrate 12, an insulating film 21 forms an embedded element separating unit 19. The element separating unit 19 is configured of an insulating film 20 having a fixed charge that is formed so as to coat the inner wall face of a groove portion 30, within the groove portion 30 which is formed in the depth direction from the light input side of the substrate 12.

Abstract: A trench MOSFET including: an epitaxial layer; a body region on the epitaxial layer, the body region and the epitaxial layer forming a first interface; a trench; a trench bottom oxide in the trench; and polysilicon in the trench, the trench bottom oxide and the polysilicon forming a second interface; where the first and second interfaces are substantially aligned or are at substantially the same level.

Abstract: A field-stop reverse conducting insulated gate bipolar transistor and a manufacturing method thereof. The transistor comprises a terminal structure (200) and an active region (100). An underlayment of the field-stop reverse conducting insulated gate bipolar transistor is an N-type underlayment, the back surface of the underlayment is provided with an N-type electric field stop layer (1), one surface of the electric field stop layer (1) departing from the underlayment is provided with a back-surface P-type structure (10), and the surface of the back-surface P-type structure (10) is provided with a back-surface metal layer (12). A plurality of polysilicon filling structures (11) which penetrate into the electric field stop layer (1) from the back-surface P-type structure (10) are formed in the active region (100).

Abstract: A solid-state imaging device includes: a semiconductor substrate provided with an effective pixel region including a light receiving section that photoelectrically converts incident light; an interconnection layer that is provided at a plane side opposite to the light receiving plane of the semiconductor substrate; a first groove portion that is provided between adjacent light receiving sections and is formed at a predetermined depth from the light receiving plane side of the semiconductor substrate; and an insulating material that is embedded in at least a part of the first groove portion.

Abstract: A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide.

Abstract: In various method embodiments, a device region in a semiconductor substrate and isolation regions adjacent to the device region are defined. The device region has a channel region and the isolation regions have strain-inducing regions laterally adjacent to the channel regions. The channel region is strained with a desired strain for carrier mobility enhancement, where at least one ion type is implanted with an energy resulting in a peak implant in the strain-inducing regions of the isolation regions. Other aspects and embodiments are provided herein.

Abstract: A semiconductor device includes a semiconductor substrate, an element isolating trench structure that includes an element isolating trench formed in one main surface of the semiconductor substrate, an insulating material that is formed within the element isolating trench, element formation regions that are surrounded by the element isolating trench, and semiconductor elements that are respectively formed in the element formation regions. The element isolating trench includes first element isolating trenches extending in a first direction, second element isolating trenches extending in a second direction that are at a right angle to the first direction, and third element isolating trenches extending in a third direction inclined at an angle ? (0°<?<90°) from the first direction.

Abstract: A method of forming 2D self-aligned vias before forming a subsequent metal layer and reducing capacitance of the resulting device and the resulting device are provided. Embodiments include forming dummy metal lines in a SiOC layer and extending in a first direction; replacing the dummy metal lines with metal lines, each metal line having a nitride cap; forming a softmask stack over the nitride cap and the SiOC layer; patterning a plurality of vias through the softmask stack down to the metal lines, the plurality of vias self-aligned along a second direction; removing the softmask stack; forming second dummy metal lines over the metal lines and extending in the second direction; forming a second SiOC layer between the dummy second metal lines on the SiOC layer; and replacing the dummy second metal lines with second metal lines, the second metal lines electrically connected to the metal lines through a via.

Abstract: Methods of forming semiconductor structures that include bodies of a semiconductor material disposed between rails of a dielectric material are disclosed. Such methods may include filling a plurality of trenches in a substrate with a dielectric material and removing portions of the substrate between the dielectric material to form a plurality of openings. In some embodiments, portions of the substrate may be undercut to form a continuous void underlying the bodies and the continuous void may be filled with a conductive material. In other embodiments, portions of the substrate exposed within the openings may be converted to a silicide material to form a conductive material under the bodies. For example, the conductive material may be used as a conductive line to electrically interconnect memory device components. Semiconductor structures and devices formed by such methods are also disclosed.

Abstract: An oxide layer is formed over a substrate having a smaller isolation trench and a large isolation trench. A nitride layer is formed over the oxide layer such that it completely fills the smaller isolation trench and lines the larger isolation trench. The nitride layer is etched back to form a recess in the nitride layer in the smaller isolation trench while at least a portion of the nitride layer lining the larger isolation trench is completely removed. A layer of HDP oxide is deposited over the substrate, completely filling the smaller and larger isolation trenches. The HDP oxide layer is planarized to the upper surface of the substrate. The deeper larger isolation trench may be formed by performing an etching step after the nitride layer has been etched back, prior to depositing HDP oxide.

Abstract: The present invention provides a metal oxide semiconductor (MOS) device, comprising a gate structure and an epitaxial structure. The gate structure is disposed on a substrate. The epitaxial structure is disposed in the substrate at two sides of the gate structure and apart thereof serves a source/drain of the MOS, wherein the epitaxial structure comprises: a first buffer layer with a second conductive type, a second buffer layer, and an epitaxial layer with a first conductive type complementary to the second conductive type. The present invention further provides a method of forming the same.

Abstract: A circuit structure includes a semiconductor substrate having a top surface. A dielectric material extends from the top surface into the semiconductor substrate. A high-k dielectric layer is formed of a high-k dielectric material, wherein the high-k dielectric layer comprises a first portion on a sidewall of the dielectric material, and a second portion underlying the dielectric material.

Abstract: A nonplanar circuit device having a strain-producing structure disposed under the channel region is provided. In an exemplary embodiment, the integrated circuit device includes a substrate with a first fin structure and a second fin structure disposed on the substrate. An isolation feature trench is defined between the first fin structure and the second fin structure. The circuit device also includes a strain feature disposed on a horizontal surface of the substrate within the isolation feature trench. The strain feature may be configured to produce a strain on a channel region of a transistor formed on the first fin structure. The circuit device also includes a fill dielectric disposed on the strain feature within the isolation feature trench. In some such embodiments, the strain feature is further disposed on a vertical surface of the first fin structure and on a vertical surface of the second fin structure.

Abstract: A semiconductor device includes a substrate and a gate structure formed over the substrate. The semiconductor device further includes an insulator feature formed in the substrate. The insulator feature includes an insulating layer and a capping layer over the insulating layer.

Abstract: A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having varied second sizes, and a plurality of first via dummy patterns smaller than the second dummy patterns and arranged in a spatial range within the second dummy patterns.

Abstract: A semiconductor device includes an oxide film structure having different thicknesses depending on where the oxide film structure is formed. In the semiconductor device, a wall oxide film is formed to have different thicknesses depending on locations of sidewalls of an active region. The semiconductor device includes an active region, a first wall oxide film disposed over a first sidewall of the active region that extends along a first direction of the active region, the first wall oxide film having a first thickness, and a second wall oxide film disposed over a second sidewall of the active region that extends along a second direction of the active region, a second wall oxide film having a second thickness that is different from the first thickness.

Abstract: One illustrative method includes forming at least one layer of epi semiconductor cladding material around a fin and patterning the cladding material and the fin, thereby resulting in the patterned fin being positioned under the patterned cladding material, wherein the patterned cladding material has an upper portion and a plurality of substantially vertically oriented legs extending downward from the upper portion. The method also includes selectively removing the patterned fin relative to the patterned cladding material, forming a sacrificial gate structure all around at least a portion of the cladding material, forming an epi semiconductor source/drain region on each of the substantially vertically oriented legs, and forming a final gate structure around at least a portion of the cladding material.

Abstract: Aspects of the present disclosure describe a termination structure for a power MOSFET device. A termination trench may be formed into a semiconductor material and may encircle an active area of the MOSFET. The termination trench may comprise a first and second portion of conductive material. The first and second portions of conductive material are electrically isolated from each other. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having a gate electrode, first and second gate dielectric layers is formed in a trench. The trench has an upper trench portion and a lower trench portion. A field plate is formed in the trench. First and second diffusion regions are formed. The gate is displaced from the second diffusion region.

Abstract: The present disclosure provides a method for fabricating a semiconductor device that includes providing a silicon substrate, forming a gate stack over the silicon substrate, performing a biased dry etching process to the substrate to remove a portion of the silicon substrate, thereby forming a recess region in the silicon substrate, performing a non-biased etching process to the recess region in the silicon substrate, thereby forming a bottle-neck shaped recess region in the silicon substrate, and epi-growing a semiconductor material in the bottle-neck shaped recess region in the silicon substrate. An embodiment may include a biased dry etching process including adding HeO2 gas and HBr gas. An embodiment may include performing a first biased dry etching process including N2 gas and performing a second biased dry etching process not including N2 gas.

Abstract: One or more embodiments relate to a semiconductor structure, comprising: a conductive feature; an outer guard ring; and an inner guard ring between the outer guard ring and the conductive feature, the inner guard ring being electrically coupled to the conductive feature.

Abstract: Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a stress-inducing material disposed in a top portion of the trench over the insulating material.

Abstract: A semiconductor device and a manufacturing method thereof are disclosed. The semiconductor device includes a silicon substrate, a spacer, a doped region, and a deep trench isolation (DTI). The silicon substrate has a deep trench. The spacer is formed on an upper portion of the sidewall of the deep trench. The doped region is formed on a lower portion of the sidewall of the deep trench. The deep trench isolation is formed in the deep trench.

Abstract: To provide a semiconductor device provided with an element isolation structure capable of hindering an adverse effect on electric characteristics of a semiconductor element, and a method of manufacturing the same. The thickness of a first silicon oxide film left in a shallow trench isolation having a relatively narrow width is thinner than the first silicon oxide film left in a shallow trench isolation having a relatively wide width. A second silicon oxide film (an upper layer) having a relatively high compressive stress by an HDP-CVD method is more thickly laminated over the first silicon oxide film in a lower layer by a thinned thickness of the first silicon oxide film. The compressive stress of an element isolation oxide film finally formed in a shallow trench isolation having a relatively narrow width is more enhanced.

Abstract: A semiconductor device includes a semiconductor substrate, an element isolating trench structure that includes an element isolating trench formed in one main surface of the semiconductor substrate, an insulating material that is formed within the element isolating trench, element formation regions that are surrounded by the element isolating trench, and semiconductor elements that are respectively formed in the element formation regions. The element isolating trench includes first element isolating trenches extending in a first direction, second element isolating trenches extending in a second direction that are at a right angle to the first direction, and third element isolating trenches extending in a third direction inclined at an angle ? (0°<?<90°) from the first direction.

Abstract: A semiconductor structure includes a semiconductor substrate with a substrate region and a trench extending into the surface region of the semiconductor substrate. The trench includes sidewalls, a bottom and a depth. The semiconductor structure further includes a trench liner overlying the bottom and the sidewalls of the trench. The semiconductor structure also includes a shallow trench isolation structure filling at least the depth of the trench. The shallow trench isolation structure is formed from alternating layers of silicon nitride and high-density plasma oxide.

Abstract: A trench groove is formed and a silicon oxide film is buried in the periphery of a channel region of (0001) surface 4h-SiC semiconductor element. The oxide film in the trench groove is defined in such a planar layout that a tensile strain is applied along the direction of the c-axis and a compressive strain is applied along two or more of axes on a plane perpendicular to the c-axis. For example, trench grooves buried with an oxide film may be configured to such a layout that they are in a trigonal shape surrounding the channel, or are arranged symmetrically with respect to the channel as a center when arranged discretely.

Abstract: A semiconductor structure includes a substrate, a shallow trench isolation (STI) structure embedded in the substrate, a stressor embedded in the substrate, and a conductive plug over and electrically coupled with the stressor. A same-material region is sandwiched by the STI structure and an entire sidewall of the stressor, and the same-material region is a continuous portion of the substrate.

Abstract: A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes an epitaxial layer and a dielectric material. The epitaxial layer is in a trench of the semiconductor and is peripherally enclosed thereby, in which the epitaxial layer is formed by performing etch and epitaxy processes. The etch and epitaxy process includes etching out a portion of a sidewall of the trench and a portion of a bottom surface of the trench and forming the epitaxial layer conformal to the remaining portion of the sidewall and the remaining portion of the bottom surface. The dielectric material is peripherally enclosed by the epitaxial layer.

Abstract: A shallow trench isolation structure containing a first shallow trench isolation portion comprising the first shallow trench material and a second shallow trench isolation portion comprising the second shallow trench material is provided. A first biaxial stress on at least one first active area and a second bidirectional stress on at least one second active area are manipulated separately to enhance charge carrier mobility in middle portions of the at least one first and second active areas by selection of the first and second shallow trench materials as well as adjusting the type of the shallow trench isolation material that each portion of the at least one first active area and the at least one second active area laterally abut.

Abstract: A semiconductor structure includes a substrate, a recess and a material. The recess is located in the substrate, wherein the recess has an upper part and a lower part. The minimum width of the upper part is larger than the maximum width of the lower part. The material is located in the recess.

Abstract: Methods and devices associated with phase change memory include diodes operating as selector switches having a large driving current and high switching speed. A method of forming a semiconductor device includes providing a semiconductor substrate, defining a diode array region and a peripheral region on the semiconductor substrate, forming an N+ buried layer in the diode array region by performing an ion implantation process and an annealing process. The method also includes forming a semiconductor epitaxial layer on the N+ buried layer, forming deep trench isolations through the epitaxial layer and the N+ buried layer into a portion of the substrate in the first direction, and forming shallow trench isolations in the diode array region and in the peripheral region in the second direction. The shallow trench isolation has a depth equal to or greater than a thickness of the epitaxial layer.

Abstract: An integrated circuit device incorporating a plurality of isolation trench structures configured for disparate applications and a method of forming the integrated circuit are disclosed. In an exemplary embodiment, a substrate having a first region and a second region is received. A first isolation trench is formed in the first region, and a second isolation trench is formed in the second region. A first liner layer is formed in the first isolation trench, and a second liner layer is formed in the second isolation trench. The second liner layer has a physical characteristic that is different from a corresponding physical characteristic of the first liner layer. An implantation procedure is performed on the second isolation trench and the second liner layer formed therein. The physical characteristic of the second liner layer may be selected to enhance an implantation depth or an implantation uniformity compared to the first liner layer.

Abstract: A semiconductor device includes a first isolation layer formed in a trench in a substrate. The isolation layer includes a first oxide layer formed in the trench and a second oxide layer formed over the first oxide layer, wherein the first oxide layer and the second oxide layer have a same composition.

Abstract: A semiconductor device includes a first conductive layer, at least one first slit through the first conductive layer, and configured to divide the first conductive layer in the unit of a memory block, second conductive layers stacked on the first conductive layer, and a second slit through the second conductive layers at a different location from the first slit and configured to divide the second conductive layers in the unit of the memory block.

Abstract: A semiconductor substrate (41) includes an insulating substrate (30), a plurality of semiconductor thin films (46) which are arranged on the insulating substrate (30) to be separated from each other, and a conductive film (33) which is arranged between the semiconductor thin films (46). Therefore, it is possible to uniformly thin the film thickness of each of the semiconductor thin films.

Abstract: According to a structure herein, a silicon substrate has an active device in the silicon substrate. A dielectric film is on the active device. An isolation trench is in the dielectric film surrounding the active device. The trench extends through the dielectric film and at least partially into the silicon substrate. A core is in the isolation trench. The core comprises material having thermal conductivity greater than silicon dioxide and electrical conductivity approximately equal to silicon dioxide.

Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. An etch sequence is performed to form a first etched region over a planar region of a semiconductor arrangement. The first etched region exposes a planar structure, such as an alignment mark used for alignment during semiconductor fabrication. The etch sequence forms a second etched region over a semiconductor fin region of the semiconductor arrangement. In an embodiment, the etch sequence forms a first trench, a first fin nub and a first pillar in the semiconductor fin region, where the first trench is formed in a semiconductor substrate of the semiconductor fin region. A multi-depth STI structure is formed over at least one of the first trench, the first fin nub, or the first pillar.

Abstract: A semiconductor structure includes a surface having a plurality of portions and a dielectric material over the surface. The dielectric material includes an aspect ratio substantially equal to or greater than a predetermined value.

Abstract: The present application discloses a semiconductor structure and a method for manufacturing the same. Compared with conventional approaches to form contacts, the present disclosure reduces contact resistance and avoids a short circuit between a gate and contact plugs, while simplifying manufacturing process, increasing integration density, and lowering manufacture cost. According to the manufacturing method of the present disclosure, second shallow trench isolations are formed with an upper surface higher than an upper surface of the source/drain regions. Regions defined by sidewall spacers of the gate, sidewall spacers of the second shallow trench isolations, and the upper surface of the source/drain regions are formed as contact holes. The contacts are formed by filling the contact holes with a conductive material. The method omits the steps of etching for providing the contact holes, which lowers manufacture cost.

Abstract: An oxide layer is formed over a substrate having a smaller isolation trench and a large isolation trench. A nitride layer is formed over the oxide layer such that it completely fills the smaller isolation trench and lines the larger isolation trench. The nitride layer is etched back to form a recess in the nitride layer in the smaller isolation trench while at least a portion of the nitride layer lining the larger isolation trench is completely removed. A layer of HDP oxide is deposited over the substrate, completely filling the smaller and larger isolation trenches. The HDP oxide layer is planarized to the upper surface of the substrate. The deeper larger isolation trench may be formed by performing an etching step after the nitride layer has been etched back, prior to depositing HDP oxide.

Abstract: A split gate power transistor includes a laterally configured power MOSFET including a doped silicon substrate having a first doped region and a second doped region of an opposite type as the first doped region, a gate oxide layer formed on a surface of the substrate, and a split polysilicon layer formed over the gate oxide layer. The polysilicon layer is cut into two electrically isolated portions, a first portion forming a polysilicon gate positioned over a channel region and a transition region of the substrate, and a second portion forming a polysilicon field plate formed entirely over a field oxide filled trench formed in the second doped region. The two polysilicon portions are separated by a gap. A lightly doped region is implanted in the substrate below the gap and adjacent to the trench, thereby forming a fill region having the same doping type as the first doped region.

Abstract: A surface mount packaging structure that yields improved thermo-mechanical reliability and more robust second-level package interconnections is disclosed. The surface mount packaging structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level metal interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer on a side opposite the semiconductor devices, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to the first surface of a multi-layer substrate structure, with a dielectric material positioned between the dielectric layer and the multi-layer substrate structure to fill in gaps in the surface-mount structure and provide additional structural integrity thereto.

Abstract: An embodiment radio frequency area of an integrated circuit is disclosed. The radio frequency area includes a substrate having an implant region. The substrate has a first resistance. A buried oxide layer is disposed over the substrate and an interface layer is disposed between the substrate and the buried oxide layer. The interface layer has a second resistance lower than the first resistance. A silicon layer is disposed over the buried oxide layer and an interlevel dielectric is disposed in a deep trench. The deep trench extends through the silicon layer, the buried oxide layer, and the interface layer over the implant region. The deep trench may also extend through a polysilicon layer disposed over the silicon layer.

Abstract: A semiconductor structure includes a shallow trench isolation (STI) structure. The semiconductor structure includes a substrate having a first surface. A STI structure extends from the first surface into the substrate. The STI structure includes a first portion and a second portion. The first portion extends from the first surface into the substrate, and has an intersection with the first surface. The second portion extends away from the first portion, and has a tip at a distance away from the intersection in a direction parallel to the first surface. The first portion and the second portion are filled with a dielectric material.

Abstract: The invention provides a semiconductor device and a method of manufacturing the same. The inventive method includes: 1) forming a pad oxide layer on a substrate; 2) forming on the pad oxide layer a barrier layer with an isolation region pattern exposing the surface of the pad oxide layer; 3) injecting ions so that the ions enter the substrate through the surface of the pad oxide layer exposed by the isolation region pattern; 4) performing heat treatment the substrate to transversely diffuse the ions in the substrate to form an ion injection layer; 5) etching the pad oxide layer and the ion injection layer using the barrier layer with the isolation region pattern as a mask to form a shallow trench isolation region on the substrate; and 6) forming a field oxide layer in the shallow trench isolation region of the substrate.