Abstract: Light emitting diode (LED) packages and methods are disclosed herein. In one aspect, a light emitting package is disclosed. The light emitting package includes one or more areas of conductive material having a thickness of less than approximately 50 microns (?m). The package can further include at least one light emitting diode (LED) electrically connected to the conductive material and at least one thin gap disposed between areas of conductive material.

Abstract: A method for fabricating a semiconductor memory device is provided. The method includes: etching a first region of the semiconductor memory device to expose a first capping layer; forming a second capping layer on the first capping layer; etching a portion of the first capping layer and a portion of the second capping layer to form a first trench reaching a first metal line; and forming a second metal line in the first trench to contact the first metal line.

Abstract: A system module includes a printed circuit board (PCB), a first semiconductor chip embedded in the PCB, a semiconductor package connected to the PCB through a plurality of stack balls, and a second semiconductor chip disposed on a surface of the PCB in a space between the PCB and the semiconductor package.

Abstract: Field-effect transistor (FET) devices are described herein that include an insulator layer, a field-effect transistor implemented over the insulator layer, a substrate layer implemented under the insulator layer, and a proximity electrode that extends at least partially through the insulator layer and positioned from the FET by a distance that is less than about 5 ?m. The FET device can include one or more substrate contact features as well.

Abstract: Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography.

Abstract: A magnetic polymer for use in microelectronic fabrication includes a polymer matrix and a plurality of ferromagnetic particles disposed in the polymer matrix. The magnetic polymer can be part of an insulation layer in an inductor formed in one or more backend wiring layers of an integrated device. The magnetic polymer can also be in the form of a magnetic epoxy layer for mounting contacts of the integrated device to a package substrate.

Abstract: The present disclosure provides a three dimensional integrated circuit having a plurality of dies. Each die includes a trigger line common to the other dies, and an ESD detection circuit coupled to the common trigger line and to a first power line common to the other dies, wherein when the ESD detection circuit of one of the plural dies detects an ESD event, the ESD detection circuit is configured to generate a control signal to the common trigger line to control a power clamp in each of the plural dies to clamp an ESD event to the common first power line or a second power line.

Abstract: Methods of processing a substrate include: providing a substrate having a polymer dielectric layer, a metal pad formed within the polymer dielectric layer and a first metal layer formed atop the polymer dielectric layer; depositing a polymer layer atop the substrate; patterning the polymer layer to form a plurality of openings, wherein the plurality of openings comprises a first opening formed proximate the metal pad; depositing a first barrier layer atop the polymer layer; depositing a dielectric layer atop the first barrier layer; etching the dielectric layer and the first barrier layer from within the first opening and a field region of the polymer layer; depositing a second barrier layer atop the substrate; depositing a second metal layer atop the substrate wherein the second metal layer fills the plurality of openings; and etching the second metal layer from a portion of the field region of the polymer layer.

Abstract: An electronics package includes an insulating substrate, a semiconductor device having a top surface coupled to a first side of the insulating substrate, and a pass-through component coupled to the first side of the insulating substrate. The pass-through component includes an insulating core and at least one through-hole structure comprising a conductive body extending through the thickness of the insulating core. A metallization layer is formed on a second side of the insulating substrate and extends through at least one via in the insulating substrate to electrically couple at least one conductive pad on the top surface of the semiconductor device to the at least one through-hole structure. An insulating material surrounds the semiconductor device and the insulating core of the pass-through component.

Abstract: According to an embodiment of the present invention, a method for forming a coil comprises patterning a first mask on a handle wafer, and depositing a conductive material on exposed portions of the handle wafer to partially define the coil. A second mask is patterned on portions of the first mask and the conductive material. A solder material is deposited on a portion of the conductive material to partially define a support member. The solder material is bonded to a wafer, and the handle wafer is separated from the conductive material.

Abstract: A fully depleted region may be used to reduce poly-to-substrate parasitic capacitance in an electronic device with poly-silicon layer. When the fully depleted region is located at least partially beneath the electronic device, an additional parasitic capacitance is formed between the fully depleted region and the substrate region. This additional parasitic capacitance is coupled in series with a first parasitic capacitance between a poly-silicon layer of the electronic device and the doped region. The series combination of the first parasitic capacitance and the additional parasitic capacitance results in an overall reduction of parasitic capacitance experience by an electronic device. The structure may include two doped regions on sides of the electronic device to form a fully depleted region based on lateral interaction of dopant in the doped regions and the substrate region.

Abstract: A method for manufacturing a wafer level fan-out package includes attaching a semiconductor chip on a partial area of an IO pattern formed on one surface of a wafer, forming a first passivation layer on surfaces of the semiconductor chip and the wafer, forming an RDL (redistribution layer) that is electrically conducted with the IO pattern and the semiconductor chip, in a partial area of a top surface of the first passivation layer, and forming a second passivation layer on the top surface of the first passivation layer and a partial surface of the RDL.

Abstract: A magnetic core includes a center section having a substantially uniform thickness, and an edge section connected to and surrounding the center section. The edge section includes a bottom portion and a top portion disposed on the bottom portion, in which the bottom portion has a gradual side surface since the top portion has a steep side surface. The profile of the magnetic core can be more rectangular thereby providing better inductor performance.

Abstract: In one embodiment, an integrated circuit package includes a package substrate, a printed circuit board, an interposer structure and a transmission line bridge interconnect within the interposer. The interposer structure, which includes multiple interposer layers, may be formed on a top surface of the package substrate. The printed circuit board may be coupled to the package substrate through the transmission line bridge interconnect. The transmission line may be formed on at least one of the interposer layers. The transmission line may be utilized to convey signals between the package substrate and the printed circuit board. The transmission line may be a stripline transmission line or a micro-strip transmission line. The transmission line may have a low parasitic inductance and implementation of the transmission line does not introduce large dimensional discontinuity throughout that signal pathway. The integrated circuit package may be part of a circuit system that includes external circuits.

Abstract: A coupling element is disclosed, comprising four coils that are arranged such that each one of the coils extends both in a first layer and a second layer. The first layer and the second layer are stacked with respect to each other and separated by an intermediate dielectric layer. The layout of each layer is configured to provide a transformer coupling between a first one and a third one of the coils, and between a second one and a fourth one of the coils. Further, the first coil and the second coil, and the third coil and the fourth coil, respectively, are routed so as to allow a differential signaling. A semiconductor device and a differential hybrid coupler comprising the coupling element are also disclosed.

Abstract: A non-volatile memory device comprises a memory area including a memory cell, and a peripheral area including a circuit that drives the memory cell. The circuit includes a first resistance element. The first resistance element includes a first conductive layer extending in a first direction, a first insulating layer provided on the first conductive layer, and a second conductive layer that includes a portion provided on the first insulating layer and an end portion in contact with the first conductive layer.

Abstract: The present invention provides a high-frequency integrated device, comprising a substrate including at least an on-chip active and passive member and a ferrite layer bonded to the substrate through an interfacial bridge and substantially wrapping plurality of surfaces of said at least on-chip active and passive members. The present invention also provides a system incorporating the high-frequency integrated device of the present invention. The present invention further provides a process for the preparation of the high-frequency integrated device.

Abstract: A semiconductor structure and a method are disclosed herein. The semiconductor structure includes a dielectric waveguide vertically disposed between a first layer and a second layer, a driver die configured to generate, at a first output node, a driving signal, a first transmission electrode located along a first side of the dielectric waveguide and configured to receive the driving signal from the first output node, a first receiver electrode located along the first side of the dielectric waveguide, and a receiver die configured to receive a received signal from the first receiver electrode.

Abstract: An electronic device includes: a substrate; a first all-solid-state secondary cell provided on the substrate, the first all-solid-state secondary cell including a first electrode layer, a solid electrolyte layer, and a second electrode layer; a first transistor including a first source drain, a second source drain electrically connected to the second electrode layer, and a first gate electrode; a first terminal electrically connected to the first electrode layer; a second terminal to control a potential of the first gate electrode; a third terminal electrically connected to the first source drain; and a sealing layer covering the first all-solid-state secondary cell and the first transistor, wherein the first terminal, the second terminal, and the third terminal are exposed on an upper surface of the sealing layer.

Abstract: A structure and method for the formation and use of fuses within a semiconductor device is provided. The fuses may be formed within the third metal layer and are formed so as to be arranged perpendicularly to active devices located on an underlying semiconductor substrate. Additionally, the fuses within the third metal layer may be formed thicker than an underlying second metal layer.

Abstract: A semiconductor memory device includes a thin-film capacitor disposed at a position facing a circuit surface of a memory chip except for a center pad region. The thin-film capacitor includes a first plane electrode, a thin-film dielectric layer, and a second plane electrode. The first plane electrode includes a first power supply input portion to which a power supply voltage of one polarity is provided, and a first power supply output portion disposed near the center pad region to output the power supply voltage of one polarity to a center pad. The second plane electrode is formed on the dielectric layer and includes a second power supply input portion to which the power supply voltage of the other polarity is provided, and a second power supply output portion disposed near the center pad region to apply the power supply voltage of the other polarity to the center pad.

Abstract: A wiring substrate includes an insulation layer, separated wires formed on a first surface of the insulation layer, a first plating layer formed on a first surface of each of the wires, a reflection layer including a first opening that exposes at least a portion of the first plating layer as a connection pad, and an electronic component mounted on a second surface of each of the wires, which is located on an opposite side of the first surface of each of the wires. The electronic component is embedded in the insulation layer.

Abstract: A device includes vertically and laterally spaced sensors that sense different physical stimuli. Fabrication of the device entails forming a device structure having a first and second wafer layers with a signal routing layer interposed between them. Active transducer elements of one or more sensors are formed in the first wafer layer and a third wafer layer is attached with the second wafer layer to produce one or more cavities in which the active transducer elements are located. A trench extends through the second wafer and through a portion of the signal routing layer. The trench electrically isolates a region of the second wafer layer surrounded by the trench from a remainder of the second wafer layer. Another active transducer element of another sensor is formed in this region. The transducer element formed in the second wafer layer may be a diaphragm for a pressure sensor of the sensor device.

Abstract: A mechanical resonator includes a spring-mass system, wherein the spring-mass system comprises a phase-change material. The mechanical resonator typically comprises an electrical circuit portion, coupled to the phase-change material to alter a phase configuration within the phase-change material. Methods of operation are also disclosed.

Abstract: A scalable switching regulator architecture has an integrated inductor. In some embodiments an area and current drive capability of switches of the switching regulator is matched with an inductor built within an area above the switches. In some embodiments the combined switches and inductor are constructed as a unit cell and can be combined to form larger elements as required for higher current drive capability and multiphase operation.

Abstract: An embodiment package includes a conductive pillar mounted on an integrated circuit chip, the conductive pillar having a stepper shape, a metal trace partially embedded in a substrate, the metal trace having a bonding pad portion protruding from the substrate, and a solder feature electrically coupling the conductive pillar to the bonding pad portion of the metal trace.

Abstract: The present disclosure provides a semiconductor device with a structural stability. The semiconductor device includes a stack of vertical alterations of conductive layers and insulating layers; supports passing through the stack, each of the supports having a cross-section of an equilateral polygon, the supports being equidistantly arranged in a first direction and a second direction, the first and second directions crossing each other; and contact plugs electrically coupled respectively to the conductive layers, each of the contact plugs being disposed between at least two adjacent supports of the supports.

Abstract: Embedded air core inductors are described for integrated circuit package substrates. The substrates have a thermal conductor for the inductors. One example includes a package substrate to carry an integrated circuit die, the package substrate having a plurality of top side pads to connect to the die on a top side and a plurality of bottom side pads to connect to an external component on a bottom side. An inductor is embedded within the package substrate, A thermal conductor is embedded within the package substrate adjacent to the inductor to conduct heat away from the inductor, and a heat sink is thermally coupled to the thermal conductor to receive the heat from the conductor.

Abstract: A pressure sensor is integrated into an integrated circuit fabrication and packaging flow. In one example, a releasable layer is formed over a removable core. A first dielectric layer is formed. A metal layer is patterned to form conductive metal paths and to form a diaphragm with the metal. A second dielectric layer is formed over the metal layer and the diaphragm. A second metal layer is formed to connect with formed vias and to form a metal mesh layer over the diaphragm. The first dielectric layer is etched under the diaphragm to form a cavity and the cavity is covered to form a chamber adjoining the diaphragm.

Abstract: AFE circuitry handles both voltage and current input signals. In one embodiment, both a voltage path and a current path are provided from the input. Switching circuitry selects one of the paths. A switch also turns on or off a current-to-voltage conversion circuit used to convert a current input into a voltage. In one embodiment, noise is significantly reduced by using a dedicated ground pin or terminal for the negative reference of a differential circuit. This applies the same external board noise, which is on the input signal, to the negative reference, so the noise is canceled in the differential signal. In one embodiment, temperature compensation is provided via an IPTAT circuit which is used to shift the voltage up in order to balance the decrease in DC voltage with increasing temperature.

Abstract: A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer.

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first via, and a first bump pad. The first via traverses the substrate. The first via has a first via dimension. The first bump pad is on a surface of the substrate. The first bump pad is coupled to the first via. The first bump pad has a first pad dimension that is equal or less then the first via dimension. In some implementations, the integrated device includes a second via and a second bump pad. The second via traverses the substrate. The second via has a second via dimension. The second bump pad is on the surface of the substrate. The second bump pad is coupled to the second via. The second bump pad has a second pad dimension that is equal or less then the second via dimension.

Abstract: A reconstituted electronic device comprising at least one die and at least one passive component. A functional material is incorporated in the substrate of the device to modify the electrical behavior of the passive component. The passive component may be formed in redistribution layers of the device. Composite functional materials may be used in the substrate to forms part of or all of the passive component. A metal carrier may form part of the substrate and part of the at least one passive component.

Abstract: A packaged integrated circuit (IC) device includes a flexible substrate having contact pads, an IC die mounted on the substrate and electrically connected to the contact pads, and conductive threads sewn into the substrate. The conductive threads have proximal ends electrically connected to corresponding ones of the contact pads with conductive bumps. The conductive threads eliminate the need for a complicated multi-layer substrate structure for interconnect fan-out so the substrate may be formed of a variety of materials such as cloth or paper.

Abstract: A mechanism is provided for integrating an inductor into a semiconductor. A circular or other closed loop trench is formed in a substrate with sidewalls connected by a bottom surface in the substrate. A first insulator layer is deposited on the sidewalls of the trench so as to coat the sidewalls and the bottom surface. A conductor layer is deposited on the sidewalls and the bottom surface of the trench so as to coat the first insulator layer in the trench such that the conductor layer is on top of the first insulator layer in the trench. A first magnetic layer is deposited on the sidewalls and bottom surface of the trench so as to coat the first insulator layer in the trench without filling the trench. The first magnetic layer deposited on the sidewalls forms an inner closed magnetic loop and an outer closed magnetic loop within the trench.

Abstract: A semiconductor device includes a first conductive layer, a second conductive layer spaced from the first conductive layer, a variable resistance layer interposed between the first and second conductive layers, and an impurity-doped layer provided over a side surface of the variable resistance layer. The variable resistance layer has a smaller width than the first and the second conductive layers.

Abstract: The semiconductor system includes a controller and a semiconductor device. The controller outputs commands and receives an output datum to discriminate whether at least one of a plurality of fuse cells abnormally operates. The semiconductor device compares logic levels of a plurality of fuse data generated from the plurality of fuse cells with each other, thereby generating a flag signal enabled when at least one of the logic levels of the plurality of fuse data is different from the other logic levels while a boot-up operation is executed according to a combination of the commands. In addition, the semiconductor device outputs the flag signal as the output datum while a read operation is executed according to a combination of the commands.

Abstract: An embodiment of an apparatus to reduce supply voltage noise with capacitors of an interposer of a stacked die is disclosed. In this embodiment, an interposer is coupled to a first integrated circuit die using a first plurality of interconnects. A substrate is coupled to the interposer using a second plurality of interconnects. The substrate includes a supply voltage plane and a ground plane, each of which is coupled to the first integrated circuit die using the second plurality of interconnects, the interposer, and the first plurality of interconnects. The interposer includes capacitors coupled in parallel using the supply voltage plane, the ground plane, and the second plurality of interconnects, where capacitance from capacitors of the interposer is provided to the first integrated circuit die using the supply voltage plane and the ground plane of the substrate.

Abstract: A wiring substrate includes a heat sink, an insulation layer, first and second wiring layers, first and second through wirings, and first and second pads. The insulation layer is arranged on the heat sink with an adhesive layer located in between. The insulation layer includes first and second through holes. The first and second wiring layers are arranged on a surface of the insulation layer in contact with the adhesive layer. The first and second wiring layers are embedded in the adhesive layer. The first through wiring formed in the first through hole is connected to the first wiring layer and thermally coupled to the semiconductor device. The second through wiring formed in the first through hole is connected to the second wiring layer and electrically connected to the semiconductor device. The pads cover exposed surfaces of the through wirings.

Abstract: A device includes a laterally diffused metal-oxide-semiconductor (LDMOS) device integrated with an optical modulator. An optical waveguide of the optical modulator includes a silicon-containing structure in a drift region of the LDMOS device.

Abstract: A printed wiring board includes a core substrate, a first buildup layer formed on a first surface of the core substrate and including an insulation layer and a conductive layer, a second buildup layer formed on a second surface of the core substrate on the opposite side with respect to the first buildup layer and including an insulation layer and a conductive layer, and an inductor device positioned in the second buildup layer and including a resin insulation layer and a coil layer formed on the resin insulation layer. The second buildup layer has a cavity in which the inductor device is accommodated.

Abstract: A metal-insulator-metal (MIM) capacitor reduces a number of masks and processing steps compared to conventional techniques. A first conductive layer of a MIM capacitor is deposited on a semiconductor chip and patterned using a MIM conductive layer mask. A conductive redistribution layer (RDL) is patterned over the MIM dielectric layer. The conductive redistribution layer includes two RDL nodes that overlap the first conductive layer of the MIM capacitor. A conductive via or bump extends through the MIM dielectric layer and couples one of the RDL nodes to the first conductive layer of the MIM capacitor.

Abstract: A reconstituted electronic device comprising at least one die and at least one passive component. A functional material is incorporated in the substrate of the device to modify the electrical behavior of the passive component. The passive component may be formed in redistribution layers of the device. Composite functional materials may be used in the substrate to forms part of or all of the passive component. A metal carrier may form part of the substrate and part of the at least one passive component.

Abstract: A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.

Abstract: The present disclosure relates to a silicon-on-insulator (SOI) substrate having a trap-rich layer, with crystal defects, which is disposed within a handle wafer, and an associated method of formation. In some embodiments, the SOI substrate has a handle wafer. A trap-rich layer, having a plurality of crystal defects that act to trap carriers, is disposed within the handle wafer at a position abutting a top surface of the handle wafer. An insulating layer is disposed onto the handle wafer. The insulating layer has a first side abutting the top surface of the handle wafer and an opposing second side abutting a thin layer of active silicon. By forming the trap-rich layer within the handle wafer, fabrication costs associated with depositing a trap-rich material (e.g., polysilicon) onto a handle wafer are reduced and thermal instability issues are prevented.

Abstract: A NAND flash memory chip includes wide openings in an inter-poly dielectric layer through which gaps are later etched to define structures such as select gates. Such select gates are asymmetric, with inter-poly dielectric on a side adjacent to a memory cell and no inter-poly dielectric on a side away from a memory cell. Gaps etched through such openings may also define peripheral devices.

Abstract: An inductive device is provided, which includes a substrate, a layer having a plurality of conductive metal traces and a metal shield layer. The conductive trace has an input port, a first portion, a second portion, a third portion and an output port. The metal shield layer is disposed between the substrate and the conductive trace. Each of the plurality of conductive metal traces has a respective length and a respective width. Each of the plurality of conductive metal traces are separated from one another. Each of the plurality of conductive metal traces are disposed perpendicularly with the first portion and the third portion. The metal shield layer provides spaced shield traces substantially perpendicular with the conductive metal traces.

Abstract: A vertical power transistor is monolithically packaged on a semiconductor die with gate buffer circuitry. The gate buffer circuitry is adapted to deliver a biasing voltage to a gate contact of the vertical power transistor for switching the device between an ON state and an OFF state. By monolithically packaging the gate buffer circuitry together with the vertical power transistor, parasitic inductance between the gate buffer circuitry and the gate of the vertical power transistor is minimized, thereby decreasing the switching time of the vertical power transistor and reducing switching noise.

Abstract: According to embodiment, a nonvolatile semiconductor memory device, includes: a memory cell region; and a peripheral region, the memory cell region including: a semiconductor layer including semiconductor regions; control gate electrodes; a first insulating film; a semiconductor-containing layer having a smaller thickness than the first insulating film; and a second insulating film, the peripheral region including: the semiconductor layer; a third insulating film; the semiconductor-containing layer, and a periphery of the semiconductor-containing layer being surrounded by an element isolation region; the first insulating film provided on the semiconductor-containing layer; and a pair of conductive layers extending from a surface of the first insulating film to reach the third insulating film via the semiconductor-containing layer, and the pair of conductive layers being in contact with part of a lower surface of the semiconductor-containing layer.

Abstract: An integrated circuit (IC) package including an IC die and a conductive ink printed circuit layer electrically connected to the IC die.