Abstract: Disclosed is a thin-film transistor array substrate including a Gate driver In Panel (GIP). The GIP includes a first wiring on a substrate, a first insulating film covering the first wiring, a second wiring on the first insulating film, a second insulating film covering the second wiring, a third insulating film over the second insulating film, first and second contact holes to expose the first and second wirings, and a third wiring on the third insulating film for connection of the first and second wirings. The third insulating film includes a first area corresponding to the first and second contact holes, a second area corresponding to a region between the first and second contact holes within a first thickness range, and a remaining third area within a second thickness range, the minimum value of the first thickness range being greater than the maximum value of the second thickness range.

Abstract: A transistor including an oxide semiconductor film, which has stable electric characteristics is provided. A transistor including an oxide semiconductor film, which has excellent on-state characteristics is also provided. A semiconductor device in which an oxide semiconductor film having low resistance is formed and the resistance of a channel region of the oxide semiconductor film is increased. Note that an oxide semiconductor film is subjected to a process for reducing the resistance to have low resistance. The process for reducing the resistance of the oxide semiconductor film may be a laser process or heat treatment at a temperature higher than or equal to 450° C. and lower than or equal to 740° C., for example. A process for increasing the resistance of the channel region of the oxide semiconductor film having low resistance may be performed by plasma oxidation or implantation of oxygen ions, for example.

Abstract: One embodiment of the present invention is to achieve high mobility in a device using an oxide semiconductor and provide a highly reliable display device. An oxide semiconductor layer including a crystal region in which c-axis is aligned in a direction substantially perpendicular to a surface is formed and an oxide insulating layer is formed over and in contact with the oxide semiconductor layer. Oxygen is supplied to the oxide semiconductor layer by third heat treatment. A nitride insulating layer containing hydrogen is formed over the oxide insulating layer and fourth heat treatment is performed, so that hydrogen is supplied at least to an interface between the oxide semiconductor layer and the oxide insulating layer.

Abstract: It is an object to provide a semiconductor device for high power application which has good properties. A means for solving the above-described problem is to form a transistor described below. The transistor includes a source electrode layer; an oxide semiconductor layer in contact with the source electrode layer; a drain electrode layer in contact with the oxide semiconductor layer; a gate electrode layer part of which overlaps with the source electrode layer, the drain electrode layer, and the oxide semiconductor layer; and a gate insulating layer in contact with an entire surface of the gate electrode layer.

Abstract: The disclosure discloses a thin film transistor and a manufacturing method thereof, an array substrate, and a display device, which can manufacture a thin film transistor with lower contents of impurity at a low temperature. The thin film transistor comprises: a substrate, and an active layer disposed on the substrate, the active layer comprising a source region, a drain region and a channel region, wherein the active layer is formed by depositing an inducing metal on an amorphous silicon layer on the substrate by an atomic layer deposition (ALD) method and then conducting heat treatment on the amorphous silicon layer deposited with the inducing metal so that metal induction crystallization and metal induction lateral crystallization take place in the amorphous silicon layer.

Abstract: An organic light emitting diode (OLED) display device and a method of fabricating the same are provided. The OLED display device includes a substrate having a thin film transistor region and a capacitor region, a buffer layer disposed on the substrate, a gate insulating layer disposed on the substrate, a lower capacitor electrode disposed on the gate insulating layer in the capacitor region, an interlayer insulating layer disposed on the substrate, and an upper capacitor electrode disposed on the interlayer insulating layer and facing the lower capacitor electrode, wherein regions of each of the buffer layer, the gate insulating layer, the interlayer insulating layer, the lower capacitor electrode, and the upper capacitor electrode have surfaces in which protrusions having the same shape as grain boundaries of the semiconductor layer are formed. The resultant capacitor has an increased surface area, and therefore, an increased capacitance.

Abstract: Reducing hydrogen concentration in a channel formation region of an oxide semiconductor is important in stabilizing threshold voltage of a transistor including an oxide semiconductor and improving reliability. Hence, hydrogen is attracted from the oxide semiconductor and trapped in a region of an insulating film which overlaps with a source region and a drain region of the oxide semiconductor. Impurities such as argon, nitrogen, carbon, phosphorus, or boron are added to the region of the insulating film which overlaps with the source region and the drain region of the oxide semiconductor, thereby generating a defect. Hydrogen in the oxide semiconductor is attracted to the defect in the insulating film. The defect in the insulating film is stabilized by the presence of hydrogen.

Abstract: A semiconductor device (100A) according to the present invention includes an oxide semiconductor layer (31a), first and second source electrodes (52a1 and 52a2), and first and second drain electrodes (53a1 and 53a2). The second source electrode (52a2) is formed to be in contact with a top surface of the first source electrode and inner to the first source electrode (52a1). The second drain electrode (53a2) is formed to be in contact with a top surface of the first drain electrode (53a1) and inner to the first drain electrode (53a1). The oxide semiconductor layer (31a) is formed to be in contact with the top surface of the first source electrode (52a1) and the top surface of the first drain electrode (53a1).

Abstract: A variation in electrical characteristics, such as a negative shift of the threshold voltage or an increase in S value, of a fin-type transistor including an oxide semiconductor material is prevented. An oxide semiconductor film is sandwiched between a plurality of gate electrodes with an insulating film provided between the oxide semiconductor film and each of the gate electrodes. Specifically, a first gate insulating film is provided to cover a first gate electrode, an oxide semiconductor film is provided to be in contact with the first gate insulating film and extend beyond the first gate electrode, a second gate insulating film is provided to cover at least the oxide semiconductor film, and a second gate electrode is provided to be in contact with part of the second gate insulating film and extend beyond the first gate electrode.

Abstract: An embodiment of the invention provides a manufacturing method of a thin film transistor substrate including: sequentially forming a gate electrode, a gate insulating layer covering the gate electrode, an active material layer, and a photo-sensitive material layer on a first substrate; performing a photolithography process by using a half tone mask to form a photo-sensitive protective layer which is above the gate electrode and has a first recess and a second recess; etching the active material layer by using the photo-sensitive protective layer as a mask to form an active layer; removing a portion of the photo-sensitive protective layer at bottoms of the first recess and the second recess to expose a first portion and a second portion of the active layer respectively; forming a first electrode connecting to the first portion; and forming a second electrode connecting to the second portion.

Abstract: A semiconductor circuit capable of controlling and holding the threshold voltage of a transistor at an optimal level and a driving method thereof are disclosed. A storage device, a display device, or an electronic device including the semiconductor circuit is also provided. The semiconductor circuit comprises a diode and a first capacitor provided in a node to which a transistor to be controlled is connected through its back gate. This structure allows the application of desired voltage to the back gate so that the threshold voltage of the transistor is controlled at an optimal level and can be held for a long time. A second capacitor connected in parallel with the diode is optionally provided so that the voltage of the node can be changed temporarily.

Abstract: An electronic device comprises at least one static induction transistor (14; 114; 214) and at least one thin film transistor (16; 116). The static induction transistor (14; 114; 214) has a first channel (14.4; 114.4; 214.4) of a semi conducting material extending between a first main electrode (14.2; 114.2; 214.2) and a second main electrode (14.3; 114.3) through a first and a second insulating layer (11, 13; 111, 113), and has a first control electrode (14.1; 114.1) surrounding the first channel and extending between the first and the second insulating layer. The thin film transistor (16; 116) has a third main electrode (16.2; 116.2) and a fourth main electrode (16.3; 116.3) coupled by a second channel (16.4; 116.4) of a semi conducting material and a second control electrode (16.1; 116.1). At least one of the first and the second insulating layer functions as a dielectric layer between the second control electrode and the second channel.

Abstract: Provided is a fin-type transistor having an oxide semiconductor in a channel formation region in which the channel formation region comprising an oxide semiconductor is three-dimensionally structured and a gate electrode is arranged to extend over the channel formation region. Specifically, the fin-type transistor comprises: an insulator protruding from a substrate plane; an oxide semiconductor film extending beyond the insulator; a gate insulating film over the oxide semiconductor film; and a gate electrode over and extending beyond the oxide semiconductor film. This structure allows the expansion of the width of the channel formation region, which enables the miniaturization and high integration of a semiconductor device having the transistor. Additionally, the extremely small off-state current of the transistor contributes to the formation of a semiconductor device with significantly reduced power consumption.

Abstract: The threshold voltage is shifted in a negative or positive direction in some cases by an unspecified factor in a manufacturing process of the thin film transistor. If the amount of shift from 0 V is large, driving voltage is increased, which results in an increase in power consumption of a semiconductor device. Thus, a resin layer having good flatness is formed as a first protective insulating film covering the oxide semiconductor layer, and then a second protective insulating film is formed by a sputtering method or a plasma CVD method under a low power condition over the resin layer. Further, in order to adjust the threshold voltage to a desired value, gate electrodes are provided over and below an oxide semiconductor layer.

Abstract: In the transistor including an oxide semiconductor film, a gate insulating film of the transistor including an oxide semiconductor film has a stacked-layer structure of the hydrogen capture film and the hydrogen permeable film. At this time, the hydrogen permeable film is formed on a side which is in contact with the oxide semiconductor film, and the hydrogen capture film is formed on a side which is in contact with a gate electrode. After that, hydrogen released from the oxide semiconductor film is transferred to the hydrogen capture film through the hydrogen permeable film by the heat treatment.

Abstract: To give favorable electrical characteristics to a semiconductor device. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a pair of electrodes over the semiconductor layer and each electrically connected to the semiconductor layer, a gate electrode over the semiconductor layer, and a gate insulating layer between the semiconductor layer and the gate electrode. The insulating layer includes an island-shaped projecting portion. A top surface of the projecting portion of the insulating layer is in contact with a bottom surface of the semiconductor layer, and is positioned on an inner side of the semiconductor layer when seen from above. The pair of electrodes covers part of a top surface and part of side surfaces of the semiconductor layer. Furthermore, the gate electrode and the gate insulating layer cover side surfaces of the projecting portion of the insulating layer.

Abstract: A display device in which variations in luminance due to variations in characteristics of transistors are reduced, and image quality degradation due to variations in resistance values is prevented. The invention comprises a transistor whose channel portion is formed of an amorphous semiconductor or an organic semiconductor, a connecting wiring connected to a source electrode or a drain electrode of the transistor, a light emitting element having a laminated structure which includes a pixel electrode, an electro luminescent layer, and a counter electrode, an insulating layer surrounding an end portion of the pixel electrode, and an auxiliary wiring formed in the same layer as a gate electrode of the transistor, a connecting wiring, or the pixel electrode. Further, the connecting wiring is connected to the pixel electrode, and the auxiliary wiring is connected to the counter electrode via an opening portion provided in the insulating layer.

Abstract: A semiconductor device includes an oxide semiconductor layer including a crystalline region over an insulating surface, a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer over the gate insulating layer in a region overlapping with the crystalline region. The crystalline region includes a crystal whose c-axis is aligned in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

Abstract: A thin-film semiconductor device according to the present disclosure includes: a substrate; a gate electrode formed above the substrate; a gate insulating film formed on the gate electrode; a channel layer that is formed of a polycrystalline semiconductor layer on the gate insulating film; an amorphous semiconductor layer formed on the channel layer and having a projecting shape in a surface; and a source electrode and a drain electrode that are formed above the amorphous semiconductor layer, and a first portion included in the amorphous semiconductor layer and located closer to the channel layer has a resistivity lower than a resistivity of a second portion included in the amorphous semiconductor layer and located closer to the source and drain electrodes.

Abstract: A metal wire included in a display device, the metal wire includes a first metal layer including a nickel-chromium alloy, a first transparent oxide layer disposed on the first metal layer, and a second metal layer disposed on the first transparent oxide layer.

Abstract: A thin film transistor array substrate capable of reducing degradation of a device due to degradation of an oxide semiconductor pattern and a method of fabricating the same are provided. The thin film transistor array substrate may include an insulating substrate on which a gate electrode is formed, a gate insulating film formed on the insulating substrate, an oxide semiconductor pattern disposed on the gate insulating film, an anti-etching pattern formed on the oxide semiconductor pattern, and a source electrode and a drain electrode formed on the anti-etching pattern. The oxide semiconductor pattern may include an edge portion positioned between the source electrode and the drain electrode, and the edge portion may include at least one conductive region and at least one non-conductive region.

Abstract: An oxide semiconductor film which has more stable electric conductivity is provided. The oxide semiconductor film comprises a crystalline region. The oxide semiconductor film has a first peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.4 nm?1 and less than or equal to 0.7 nm?1 in a region where a magnitude of a scattering vector is greater than or equal to 3.3 nm?1 and less than or equal to 4.1 nm?1. The oxide semiconductor film has a second peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.45 nm?1 and less than or equal to 1.4 nm?1 in a region where a magnitude of a scattering vector is greater than or equal to 5.5 nm?1 and less than or equal to 7.1 nm?1.

Abstract: To provide a power MISFET using oxide semiconductor. A gate electrode, a source electrode, and a drain electrode are formed so as to interpose a semiconductor layer therebetween, and a region of the semiconductor layer where the gate electrode and the drain electrode do not overlap with each other is provided between the gate electrode and the drain electrode. The length of the region is from 0.5 ?m to 5 ?m. In such a power MISFET, a power source of 100 V or higher and a load are connected in series between the drain electrode and the source electrode, and a control signal is input to the gate electrode.

Abstract: Complementary metal oxide semiconductor (CMOS) ultrasonic transducers (CUTs) and methods for forming CUTs are described. The CUTs may include monolithically integrated ultrasonic transducers and integrated circuits for operating in connection with the transducers. The CUTs may be used in ultrasound devices such as ultrasound imaging devices and/or high intensity focused ultrasound (HIFU) devices.

Abstract: An object is to provide a semiconductor device in which defects are reduced and miniaturization is achieved while favorable characteristics are maintained. A semiconductor layer is formed; a first conductive layer is formed over the semiconductor layer; the first conductive layer is etched with use of a first resist mask to form a second conductive layer having a recessed portion; the first resist mask is reduced in size to form a second resist mask; the second conductive layer is etched with use of the second resist mask to form source and drain electrodes each having a projecting portion with a tapered shape at the peripheries; a gate insulating layer is formed over the source and drain electrodes to be in contact with part of the semiconductor layer; and a gate electrode is formed in a portion over the gate insulating layer and overlapping with the semiconductor layer.

Abstract: A set of buried electrodes are embedded in a dielectric material layer, and a graphene layer having a doping of a first conductivity type are formed thereupon. A first upper electrode is formed over a center portion of each buried electrode. Second upper electrodes are formed in regions that do not overlie the buried electrodes. A bias voltage is applied to the set of buried electrodes to form a charged region including minority charge carriers over each of the buried electrodes, and to form a p-n junction around each portion of the graphene layer overlying a buried electrode. Charge carriers generated at the p-n junctions are collected by the first upper electrodes and the second upper electrodes, and are subsequently measured by a current measurement device or a voltage measurement device.

Abstract: A thin-film transistor includes a gate electrode, a capacitance compensation structure, a semiconductor layer, a dielectric layer, a drain electrode and a source electrode. The capacitance compensation structure is disposed on the substrate and electrically connected to the gate electrode. The capacitance compensation structure has a first side facing the gate electrode and a second side facing away from the gate electrode. The semiconductor layer covers a portion of the gate electrode, and at least extends to overlap the first side of the capacitance compensation structure. The dielectric layer has a first opening and a second opening. Both of the first opening and the second opening expose a portion of the semiconductor layer overlapping the gate electrode respectively. The drain electrode is in contact with the semiconductor layer though the first opening. The source electrode is in contact with the semiconductor layer though the second opening.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate, a channel layer, a gate insulation layer, a source, a drain and a silicon-aluminum-oxide layer. The gate is disposed on a substrate. The channel layer is disposed on the substrate. The channel layer overlaps the gate. The gate insulation layer is disposed between the gate and the channel layer. The source and the drain are disposed on two sides of the channel layer. The silicon-aluminum-oxide layer is disposed on the substrate and covers the source, the drain and the channel layer.

Abstract: In a thin film transistor, an increase in off current or negative shift of the threshold voltage is prevented. In the thin film transistor, a buffer layer is provided between an oxide semiconductor layer and each of a source electrode layer and a drain electrode layer. The buffer layer includes a metal oxide layer which is an insulator or a semiconductor over a middle portion of the oxide semiconductor layer. The metal oxide layer functions as a protective layer for suppressing incorporation of impurities into the oxide semiconductor layer. Therefore, in the thin film transistor, an increase in off current or negative shift of the threshold voltage can be prevented.

Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by wet etching in which an etchant is used, and a second etching step is performed by dry etching in which an etching gas is used.

Abstract: A semiconductor device having a high aperture ratio and including a capacitor capable of increasing the charge capacity is provided. A semiconductor device includes a transistor over a substrate, a first light-transmitting conductive film over the substrate, an oxide insulating film covering the transistor and having an opening over the first light-transmitting conductive film, a nitride insulating film over the oxide insulating film and in contact with the first light-transmitting conductive film in the opening, a second light-transmitting conductive film connected to the transistor and having a depressed portion in the opening, and an organic resin film with which the depressed portion of the second light-transmitting conductive film is filled.

Abstract: A semiconductor device includes a first transistor which includes a first gate electrode below its oxide semiconductor layer and a second gate electrode above its oxide semiconductor layer, and a second transistor which includes a first gate electrode above its oxide semiconductor layer and a second gate electrode below its oxide semiconductor layer and is provided so as to at least partly overlap with the first transistor. In the semiconductor device, a conductive film serving as the second gate electrode of the first transistor and the second gate electrode of the second transistor is shared between the first transistor and the second transistor. Note that the second gate electrode not only controls the threshold voltages (Vth) of the first transistor and the second transistor but also has an effect of reducing interference of an electric field applied from respective first gate electrodes of the first transistor and the second transistor.

Abstract: An organic semiconductor device includes a carrier, a source, a drain, an organic semiconductor single-crystalline channel layer, an organic insulation layer and a gate. The source and the drain are disposed on an upper surface of the carrier. The source and the drain are disposed in parallel and a portion of the carrier is exposed between the source and the drain. The organic semiconductor single-crystalline channel layer is disposed on the upper surface of the carrier and covers a portion of the source, a portion of the drain and the portion of the carrier exposed by the source and the drain. The organic insulation layer covers the carrier, the source, the drain and the organic semiconductor single-crystalline channel layer. The gate is disposed on the organic insulation layer and corresponds to a position of the portion of the carrier exposed by the source and the drain.

Abstract: The present disclosure provides a touch panel, including at least a plurality of first electrode axes, a plurality of second electrode blocks. Each first electrode axis and corresponding second electrode block are disposed at the same level, staggered and electrically isolated from each other. Each first electrode axis is an uninterrupted structure. The touch panel of the present disclosure provides a new electrode pattern, and since all electrodes are disposed at the same level, therefore the electrodes can be formed simultaneously, thereby decreasing the cost of manufacturing process.

Abstract: One or more embodiments of the disclosed technology provide a thin film transistor, an array substrate and a method for preparing the same. The thin film transistor comprises a base substrate, and a gate electrode, a gate insulating layer, an active layer, an ohmic contact layer, a source electrode, a drain electrode and a passivation layer prepared on the base substrate in this order. The active layer is formed of microcrystalline silicon, and the active layer comprises an active layer lower portion and an active layer upper portion, and the active layer lower portion is microcrystalline silicon obtained by using hydrogen plasma to treat at least two layers of amorphous silicon thin film prepared in a layer-by-layer manner.

Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.

Abstract: A semiconductor device includes a semiconductor layer made of first conductivity type SiC; a second conductivity type well region formed on the semiconductor layer and having a channel region; a first conductivity type source region formed on the well region and including a first region adjacent to the well region and a second region adjacent to the first region; a gate insulating film formed on the semiconductor layer and having a first portion that contacts the first region; a second portion that contacts the well region and that has a thickness that is the same as that of the first portion; and a third portion that contacts the second region and that has a thickness that is greater than that of the first portion; and a gate electrode formed on the gate insulating film and opposed to the channel region where a channel is formed through the gate insulating film.

Abstract: Provided is a field-effect transistor which has a high mobility and a low variation of mobility. A field-effect transistor at least comprising a substrate, a semiconductor layer, a source electrode, and a drain electrode is produced by forming the source electrode and/or the drain electrode so that the source electrode and/or the drain electrode has a taper shape in a cross-section which is parallel with a channel length direction and perpendicular to the substrate, and forming the semiconductor layer through coating process.

Abstract: A thin film transistor display panel a includes a transparent substrate; a gate electrode positioned on the substrate; a gate insulating layer positioned on the gate electrode; a semiconductor layer positioned on the gate insulating layer and including a channel region; a source electrode and a drain electrode positioned on the semiconductor layer and facing each other; and a passivation layer configured to cover the source electrode, the drain electrode, and the semiconductor layer, wherein the semiconductor layer includes a relatively thick first portion between the source electrode and the gate electrode and a relatively thinner second portion between the drain electrode and the gate electrode overlap, the relatively thick first portion being sufficiently thick to substantially reduce a charge trapping phenomenon that may otherwise occur at a gate electrode to gate dielectric interface if the first portion were as thin as the second portion.

Abstract: The present invention provides a method for producing a semiconductor laminate including a substrate having formed thereon a silicon layer with small surface unevenness and high continuity. The method of the present invention for producing a semiconductor laminate having a substrate 10 and a sintered silicon particle layer 5 on the substrate includes (a) coating a silicon particle dispersion containing a dispersion medium and silicon particles dispersed in the dispersion medium, on a substrate 10 to form a silicon particle dispersion layer 1, (b) drying the silicon particle dispersion layer 1 to form a green silicon particle layer 2, (c) stacking a light-transmitting layer 3 on the green silicon particle layer, and (d) irradiating the green silicon particle layer 2 with light through the light-transmitting layer 3 to sinter the silicon particles constituting the green silicon particle layer 2, and thereby form a sintered silicon particle layer 5.

Abstract: This disclosure provides systems, methods and apparatuses for pixel vias. In one aspect, a method of forming an electromechanical device having a plurality of pixels includes depositing an electrically conductive black mask on a substrate at each of four corners of each pixel, depositing a dielectric layer over the black mask, depositing an optical stack including a stationary electrode over the dielectric layer, depositing a mechanical layer over the optical stack, and anchoring the mechanical layer over the optical stack at each corner of each pixel. The method further includes providing a conductive via in a first pixel of the plurality of pixels, the via in the dielectric layer electrically connecting the stationary electrode to the black mask, the via disposed at a corner of the first pixel, offset from where the mechanical layer is anchored over the optical stack in an optically non-active area of the first pixel.

Abstract: An electronic device, such as a thin-film transistor, includes a semiconducting layer formed from a semiconductor composition. The semiconductor composition comprises a polymer binder and a small molecule semiconductor. The semiconducting layer has been deposited on an alignment layer that has been aligned in the direction between the source and drain electrodes. The resulting device has increased charge carrier mobility.

Abstract: By using a coating method, which is a method of manufacturing a transparent conductive film, with low-temperature heating lower than 300° C., a transparent conductive film with excellent transparency, conductivity, film strength, and resistance stability and a method of manufacturing this film are provided. In the method of manufacturing a transparent conductive film, a heat energy ray irradiating step is a step of irradiating with the energy rays while heating under an oxygen-containing atmosphere to a heating temperature lower than 300° C. to form the inorganic film, and the plasma processing step is a step of performing the plasma processing on the inorganic film under a non-oxidizing gas atmosphere at a substrate temperature lower than 300° C. to promote mineralization or crystallization of the film, thereby forming a conductive oxide fine-particle layer densely packed with conductive oxide fine particles having a metal oxide as a main component.

Abstract: A high efficiency HFET may include a substrate, a semi-insulating gallium nitride (GaN) layer formed on the substrate, an aluminum gallium nitride (AlGaN) layer formed on the GaN layer, and a silicon carbide (SixC1-x) functional layer formed on the AlGaN layer.

Abstract: To reduce oxygen vacancies in an oxide semiconductor film and the vicinity of the oxide semiconductor film and to improve electric characteristics of a transistor including the oxide semiconductor film. A semiconductor device includes a gate electrode whose Gibbs free energy for oxidation is higher than that of a gate insulating film. In a region where the gate electrode is in contact with the gate insulating film, oxygen moves from the gate electrode to the gate insulating film, which is caused because the gate electrode has higher Gibbs free energy for oxidation than the gate insulating film. The oxygen passes through the gate insulating film and is supplied to the oxide semiconductor film in contact with the gate insulating film, whereby oxygen vacancies in the oxide semiconductor film and the vicinity of the oxide semiconductor film can be reduced.

Abstract: Semiconductor devices include a first set of fins having a uniform fin pitch that is less than half a minimum fin pitch for an associated lithography process; and a second set of fins having a variable fin pitch that is less the minimum fin pitch for the associated lithography process but greater than half the minimum fin pitch for the associated lithography process.

Abstract: A thin film transistor and a method of manufacturing the same are provided. The thin film transistor includes a first gate electrode and an active layer including a crystalline oxide semiconductor which is insulated from the first gate electrode by a first insulating layer and the active layer is arranged to overlap the first gate electrode. A source electrode is formed including at least a portion overlaps the active layer, and a drain electrode is arranged being spaced apart from the source electrode and at least a portion of the drain electrode overlaps the active layer, wherein the source electrode and the drain electrode are insulated from the first gate electrode by the first insulating layer.

Abstract: The present invention aims to shorten a drying time for time for drying a coiled electrode. To this end, a drying device for drying the coiled electrode wound on a winding core includes a heating unit for heating the coiled electrode from a winding core side. Since this enables heat to be transferred from a core part toward a surface of the coiled electrode, tiny spaces can be generated between layers of an electrode and moisture can be evaporated from these spaces. Thus, moisture of the core part side, which has been difficult to evaporate, can be reliably evaporated and a drying time for the coiled electrode can be shortened.

Abstract: To suppress a decrease in on-state current in a semiconductor device including an oxide semiconductor. A semiconductor device includes an insulating film containing silicon, an oxide semiconductor film over the insulating film, a gate insulating film containing silicon over the oxide semiconductor film, a gate electrode which is over the gate insulating film and overlaps with at least the oxide semiconductor film, and a source electrode and a drain electrode which are electrically connected to the oxide semiconductor film. In the semiconductor device, the oxide semiconductor film which overlaps with at least the gate electrode includes a region in which a concentration of silicon distributed from an interface with the insulating film is lower than or equal to 1.1 at. %. In addition, a concentration of silicon contained in a remaining portion of the oxide semiconductor film except the region is lower than the concentration of silicon contained in the region.

Abstract: Embodiments of the invention relate to a TFT, a mask for manufacturing the TFT, an array substrate and a display device. A channel of the TFT is formed by using a single slit mask. The channel of the TFT has a bent portion and extension portions provided on both sides of the bent portion, and a channel width of the bent portion is larger than a channel width of the extension portion.