Abstract: An audio apparatus includes a network interface, a receiver, at least one storage, and at least one processor. The processor is configured to determine that the audio apparatus is in a state capable of communicating with the other audio apparatus via the network interface. The processor is also configured to receive audio data via the receiver transmitted from an external apparatus different from the other audio apparatus. The processor is also configured to output a sound based on the received audio data. The processor is also configured to transmit the sound emission control information stored in the at least one storage to the other audio apparatus. The sound emission control information includes one or more of a sound volume, and a frequency band.

Abstract: A package for a use in a package-on-package (PoP) device and a method of forming is provided. The package includes a substrate, a polymer layer formed on the substrate, a first via formed in the polymer layer, and a material disposed in the first via to form a first passive device. The material may be a high dielectric constant dielectric material in order to form a capacitor or a resistive material to form a resistor.

Abstract: An example multi-branch terminal for an integrated circuit (IC) package is described herein. An example multi-branch terminal of an integrated circuit (IC), may include a first branch that may include an active bonding with a chip of the IC, wherein the active bonding may include a wire bonded to the chip of the IC; and a second branch that may include a passive bonding with the chip of the IC, wherein the passive bonding may include a capacitor bonded to the second branch and a first terminal of the IC.

Abstract: A semiconductor package includes a chip stack having a plurality of semiconductor chips vertically stacked on a package substrate. A stress-equalizing chip is disposed on the chip stack, the stress-equalizing chip providing means to reduce the variation in the electrical characteristics of the plurality of semiconductor chips. An encapsulant is disposed on the package substrate and is configured to cover at least a portion of the chip stack. Each of the plurality of semiconductor chips is electrically connected to the package substrate. The stress-equalizing chip is not electrically connected to the substrate or to the plurality of semiconductor chips.

Abstract: A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die.

Abstract: A semiconductor device includes leads, a switching element, a control element that controls the switching element, and a resin member covering the switching element, the control element and parts of the respective leads. The leads include a drain lead connected to a drain electrode of the switching element, a source lead connected to a source electrode of the switching element, and at least one control lead connected to the control element. The resin member includes a drain exposed portion at which the drain lead is exposed, a source exposed portion at which the source lead is exposed, and a control exposed portion at which the control lead is exposed. The distance in a first direction between the drain exposed portion and the source exposed portion is larger than the distance in the first direction between the control exposed portion and the source exposed portion.

Abstract: A semiconductor device package is provided. The semiconductor device package includes a stack of semiconductor dies over a substrate, the substrate including a plurality of electrical contacts, and an annular lower lid disposed over the substrate and surrounding the stack of semiconductor dies. The annular lower lid includes a lower surface coupled to the substrate, an upper surface coupled to an upper lid, and an outer surface in which is formed an opening. The semiconductor device assembly further includes a circuit element disposed in the opening and electrically coupled to at least a first one of the plurality of electrical contacts. The semiconductor device assembly further includes the upper lid disposed over the annular lower lid and the stack of semiconductor dies.

Abstract: Provided is a technique for improving the durability of a semiconductor device. A semiconductor device includes a semiconductor substrate, an electrode on the semiconductor substrate, a solder-joining metal Him on the electrode, an oxidation-inhibiting metal film on the solder-joining metal film, and a solder layer on the oxidation-inhibiting metal film. The solder-joining metal film includes a first portion that does not overlap the oxidation-inhibiting metal film in plan view when the solder-joining metal film and the oxidation-inhibiting metal film are viewed from the oxidation-inhibiting metal film.

Abstract: The present invention relates to a multi-chip detector apparatus composed of multiple single detectors. An embodiment of the invention provides a multi-chip detector apparatus having a multiple number of single chips arranged in inter-chip connection on a substrate, where the multi-chip detector apparatus includes: a first single chip that has a multiple number of single detectors formed in m rows and n columns; a second single chip that is positioned at either a left side or a right side of the first single chip and is connected row-wise with the first single chip; and a third single chip that is positioned at either an upper side or a lower side of the first single chip and is connected column-wise with the first single chip, and where the second single chip and the third single chip also have multiple numbers of single detectors formed in m rows and n columns.

Abstract: A semiconductor device includes a semiconductor element, a first substrate, a first electrode, a second electrode and a sealing resin. The first substrate has a first front surface and a first back surface that are spaced apart from each other in a thickness direction. The semiconductor element is mounted on the first main surface. The first electrode includes a first conductive portion and a second conductive portion. The first conductive portion is formed on a portion of the first front surface. The second conductive portion is connected to the first conductive portion and overlaps with the first substrate as viewed in a first direction perpendicular to the thickness direction. The sealing resin covers the semiconductor element. The second electrode is exposed from the sealing resin and electrically connected to the first electrode. The second electrode is in contact with the second conductive portion.

Abstract: An electronic device has a sealing part 90, an electronic element 95 provided in the sealing part 90 and a connection body 50 having a head part 40 connected to a front surface of the electronic element 95 via a conductive adhesive 75. The head part 40 has a second projection protruding 42 toward the electronic element 95 and a first projection 41 protruding from the second projection 42 toward the electronic element 95.

Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes an insulation layer, an electronic component and a lead frame unit. The electronic component is embedded within the insulation layer and includes plural conducting terminals. The lead frame unit is embedded within the insulation layer and includes a lead frame and a metallization layer. The metallization layer having a thickness more than 10 ?m is disposed on at least a part of the lead frame and electrically connected with at least one of the plural conducting terminals of the electronic component.

Abstract: Provided is a terminal plate according to an embodiment including: a first plate portion for being connected to a first semiconductor element; a second plate portion for being connected to a second semiconductor element; a third plate portion provided above the first plate portion and the second plate portion; a first connecting portion provided between the first plate portion and the third plate portion and connecting the first plate portion and the third plate portion; a second connecting portion provided between the second plate portion and the third plate portion and connecting the second plate portion and the third plate portion; a fourth plate portion provided above the first plate portion and the second plate portion and provided on the opposite side of the third plate portion with interposing the first and second plate portions; a third connecting portion provided between the first plate portion and the fourth plate portion and connecting the first plate portion and the fourth plate portion; a fourth

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

Abstract: A semiconductor package is provided. The semiconductor package includes: a mounting substrate including at least one bonding pad; a first semiconductor chip disposed on the mounting substrate, and including a first protrusion on one side of the first semiconductor chip; a first spacer ball electrically connected to the first semiconductor chip; a first bump ball electrically connected to the first spacer ball; and a first wire which electrically connects the first bump ball and the bonding pad without contacting the first protrusion, wherein the first wire includes a first portion extending in a direction away from the bonding pad, and a second portion extending in a direction approaching the bonding pad.

Abstract: A method for forming a chip package structure is provided. The method includes forming a first redistribution structure over a first carrier substrate. The method includes bonding a chip structure to the first surface through a first conductive bump. The method includes forming a first molding layer over the first redistribution structure. The method includes removing the first carrier substrate. The method includes forming a second conductive bump over the second surface. The method includes forming a second redistribution structure over a second carrier substrate. The method includes bonding the first redistribution structure to the third surface. The method includes forming a second molding layer over the second redistribution structure. The method includes removing the second carrier substrate. The method includes removing a portion of the second redistribution structure from the fourth surface. The method includes forming a third conductive bump over the fourth surface.

Abstract: A device includes a first die, a second die, one or more redistribution layers (RDLs) electrically connected to the first die, a plurality of connectors on a surface of the one or more RDLs and a package substrate electrically connected to the first die and the second die. The package substrate is electrically connected to the first die through the one or more RDLs and the plurality of connectors. The package substrate comprises a cavity, and the second die is at least partially disposed in the cavity.

Abstract: A semiconductor device may include first and second conductor plates opposed to each other via first and second semiconductor chips, a first conductor spacer interposed between the first semiconductor chip and the second conductor plate, a second conductor spacer interposed between the second semiconductor chip and the second conductor plate, and an encapsulant provided between the first and second conductor plates. A lower surface of the second conductor plate may include a first joint area where the first conductor spacer is joined, a second joint area where the second conductor spacer is joined, an adhesion area to which the encapsulant adheres, and a separation area from which the encapsulant is separated. The adhesion area may surround the first joint area, the second joint area, and the separation area. The separation area may be located between the first and the second joint areas.

Abstract: A high resistivity wafer with a heat dissipation structure includes a high resistivity wafer and a metal structure. The high resistivity wafer includes a heat dissipation region and a device support region. The high resistivity wafer consists of an insulating material. The metal structure is only embedded within the heat dissipation region of the high resistivity wafer. The metal structure surrounds the device support region.

Abstract: An orientation-determining device to determine orientation of a vehicle includes a housing, a circuit board, and an orientation-identifying electronic device that includes an integrated accelerometer, an integrated gyroscope, and an integrated magnetometer. The orientation-identifying electronic device is coupled to the circuit board. The orientation-determining device includes a gyroscope that is coupled to the circuit board, an accelerometer that is coupled to the circuit board, and a dampening structure connected between the housing and the circuit board to isolate the circuit board, the orientation-identifying electronic device, the gyroscope, and the accelerometer from vibrations of the housing.

Abstract: Methods for hybrid bonding include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. The conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.

Abstract: A manufacturing method of a chip package includes the following steps. A light transmissive substrate is bonded to a first surface of a wafer, such that a dam element between the light transmissive substrate and the wafer covers a conductive pad of the wafer. A second surface of the wafer facing away from the first surface is etched, such that a hollow region and a trench selectively communicated with the hollow region are synchronously formed in the wafer. A first isolation layer on the conductive pad is etched to expose the conductive pad through the hollow region.

Abstract: A semiconductor chip having a core region and an I/O region which surrounds the core region is provided with a plurality of external connection pads connected to I/O cells. The plurality of external connection pads include a first pad group comprised of the external connection pads connected to the same node, and a second pad group comprised of the external connection pads connected to respective different nodes. In first and second pad groups, the external connection pads are arranged in an X direction along an external side of the semiconductor chip, and a pad arrangement pitch in the first pad group is smaller than that in the second pad group.

Abstract: A semiconductor package includes a silicon substrate including a cavity and a plurality of through holes spaced apart from the cavity, a first semiconductor chip in the cavity, a plurality of conductive vias in the plurality of through holes, a first redistribution layer on the silicon substrate and connected to the first semiconductor chip and the conductive vias, and a second redistribution layer below the silicon substrate and connected to the first semiconductor chip and the plurality of conductive vias.

Abstract: An object of the present invention is to provide a highly reliable semiconductor device that allows voids remaining in a bonding material to be reduced. The semiconductor device includes a semiconductor chip, an insulation substrate, a metal base plate, a resin section, and a bump. The semiconductor chip is warped into a concave shape. On the insulation substrate, the semiconductor chip is mounted by bonding. The metal base plate has the insulation substrate mounted thereon and has a heat dissipation property. The resin section seals the insulation substrate and the semiconductor chip. The bump is disposed in a joint between the semiconductor chip and the insulation substrate. A warp amount of the semiconductor chip warped into a concave shape is equal to or greater than 1 ?m and less than a height of the bump.

Abstract: A semiconductor package includes a semiconductor die having a semiconductor device, and first and second contact pads arranged on opposite surfaces of the die. The semiconductor die is embedded in a dielectric layer. The semiconductor package also includes one or more first package contact pads and one or more second package contact pads arranged on a first major surface of the semiconductor package. The first contact pad of the die is coupled to the one or more first package contact pads, and the second contact pad of the die is coupled to the one or more second package contact pads. In operation, the semiconductor device causes a current path between the first contact pad and the second contact pad. The package contact pads are arranged on the first major surface of the semiconductor package to provide multiple non-parallel current paths.

Abstract: A manufacturing method of a semiconductor device, includes: (a) preparing a lead frame having: a first tie bar extending in a first direction in plan view so as to couple a plurality of first leads to one another; a second tie bar extending in the first direction in plan view so as to couple a plurality of second leads to one another; a coupling portion coupled to the first tie bar and the second tie bar; a first chip mounting portion arranged between the first tie bar and the second tie bar in plan view; and a second chip mounting portion arranged between the first chip mounting portion and the second tie bar in plan view; and (b) after the (a), mounting a first semiconductor chip on the first chip mounting portion and mounting a second semiconductor chip on the second chip mounting portion.

Abstract: The method for producing a preform integrating at least one electronic chip included between insulating and/or conductive laminated internal layers; mechanically securing metal bus-bar segments at given spaced-apart positions on opposing upper and lower faces of the preform, using dielectric portions of a resin prepreg; and for each of the upper and lower opposing faces, electrodepositing a metal layer in order to interconnect bus-bar segments secured to the face in question and an electrode of the electronic chip, thereby forming an electronic power circuit comprising bus-bars forming heat sinks.

Abstract: The invention relates to a power semiconductor device comprising a pin element which passes through a housing opening, comprising a support device, further comprising an elastic sealing device which is arranged on the support device, comprising a pressure device which is arranged on the sealing device, and comprising an electrically conductive sleeve. A first pressure element of the pressure device presses a first sealing element of the sealing device against a first support element of the support device in the axial direction of the pin element causes deformation of the first sealing element so that the first sealing element presses against the housing opening wall and against the sleeve in a perpendicular direction in relation to the axial direction of the pin element.

Abstract: A semiconductor package includes a first layer of one or more first semiconductor chips each having a first surface at which one or more first pads are exposed, a second layer of one or more second semiconductor chips disposed over the first layer and each having a second surface at which one or more second pads are exposed, and a first redistribution layer between the first layer and the second layer and electrically connected to the one or more first pads. The first layer may include one or more first TPVs extending through a substrate (panel) of the first layer and electrically connected to the first redistribution layer.

Abstract: The invention relates to a power semiconductor device having a pin element which passes through a housing opening, an elastic sealing device which is arranged between a housing opening wall of the housing, where the housing opening wall delimits the housing opening and encircles the pin element. The pin element runs through the sleeve and through a sealing device opening of the sealing element. The sealing device is not connected in a materially bonded manner to the sleeve, to the housing opening wall and to the pin element and the sealing device seals off the housing opening wall from the sleeve and seals off the sleeve from the pin element. A crosslinked potting compound is arranged on the sealing device. The crosslinked potting compound is connected in a materially bonded manner to the sleeve, to the housing opening wall and to the pin element and the potting compound seals off the housing opening wall from the sleeve and seals off the sleeve from the pin element.

Abstract: A die-to-die interconnect structure includes an interconnect network including a plurality of metal interconnect layers. The interconnect network is configured to electrically couple a first die and a second die mounted on a top surface of the die-to-die interconnect structure. A first metal interconnect layer of the plurality of metal interconnect layers includes a plurality of ground lines and a plurality of signal lines distributed across the first metal interconnect layer according to a GSSG pattern. In some examples, adjacent signal lines within the first metal interconnect layer are separated by a dielectric region. In some embodiments, a second metal interconnect layer of the plurality of metal interconnect layers is disposed above the first metal interconnect layer and includes a plurality of configurable signal/ground lines. By way of example, each of the plurality of configurable signal/ground lines is disposed over the dielectric region and within the second metal interconnect layer.

Abstract: This disclosure provides a package substrate fabrication method including: providing a carrier; forming a first dielectric layer on the carrier while enabling the first dielectric layer to be patterned including an opening; forming a first conducting unit on the carrier while enabling the first conducting unit to fill up the opening, a height of the first conducting unit at the opening larger than a thickness of the first dielectric layer, and a width of the first conducting unit larger than a width of the opening; forming a second dielectric layer on the first conducting unit; forming a second conducting unit on the second dielectric layer; forming a third dielectric layer on the second conducting unit; removing the carrier and the first dielectric layer while enabling the part of the first conducting unit in the opening to be removed; and forming a fourth dielectric layer to cover the first conducting unit.

Abstract: The power module includes: a first metallic pattern; a plurality of power devices bonded on the first metallic pattern, each of the plurality of the power devices has a thickness thinner than a thickness of the metallic pattern; a frame member disposed so as to collectively enclose a predetermined number of the power devices on the first metallic pattern; a second metallic pattern disposed outside the frame member; and a resin layer configured to seal the plurality of the power devices and the first and second metallic patterns so as to include the frame member, wherein the frame member suppresses a stress according to a difference between a coefficient of thermal expansion of the metallic pattern and a coefficient of thermal expansion of the power devices. There is provided the power module easy to be fabricated, capable of suppressing the degradation of the bonded portion and improving reliability.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to merged mandrel lines and methods of manufacture. The structure includes: at least one metal line having a first dimension in a self-aligned double patterning (SADP) line array; and at least one metal line having a second dimension inserted into the SADP line array, the second dimension being different than the first dimension.

Abstract: An electronic circuit board includes: electronic components; a silicon board that is plate shaped, includes a wiring pattern provided on at least one of a surface and a reverse surface thereof, and includes recessed portions where the electronic components are individually mounted; and a supporting board that is layered over the reverse surface of the silicon board, and includes a wiring pattern provided on at least one of a surface and a reverse surface thereof. Side faces of the recessed portions are perpendicular to the surface of the silicon board, the wiring pattern is connected to at least one of the electronic components mounted in the recessed portions, via at least one of a via and a bottom surface electrode provided in of the at least one of the recessed portions, and the recessed portions penetrate through the silicon board.

Abstract: Gates of semiconductor switching elements are connected to a gate control wiring pattern. The gate control wiring pattern is further connected to a gate control terminal and a filter terminal which are connected by an element for forming a filter outside a housing. The filter terminal and the gate control terminal are connected to the gate control wiring pattern in such a manner that a section electrically connecting the filter terminal and the gate control terminal overlaps with at least a part of a section electrically connecting the gates of the semiconductor switching elements on the gate control wiring pattern.

Abstract: This semiconductor chip package has opposed first surface and second surface, and includes a semiconductor chip having a circuit part and an electrode for supplying a voltage to the circuit part, a resin layer formed in a periphery of the semiconductor chip, a substrate that is disposed to face the first surface of the semiconductor chip and the resin layer, and a plurality of external terminals that are provided on the second surface of the semiconductor chip, each of the plurality of external terminals being electrically coupled to any of the plurality of electrodes.

Abstract: The subject disclosure relates generally to a method of implementing magnetic shielding walls with specific respective dimensions to reduce crosstalk between transmission lines in wire-bonds for supercomputing chipsets. In one embodiment, the device comprises: a chip-set comprised of superconducting materials; at least one superconducting data line attached to chip-set dies by a set of wire bonds; and magnetic shielding walls that respectively isolate the set of wire bonds.

Abstract: Photonic integrated circuit packages having improved integration, and methods of manufacturing such photonic integrated circuit packages, are provided. As an example, a photonic integrated circuit package may include a substrate, a first insulating layer on the substrate, a photonic core layer on the first insulating layer, and a second insulating layer on the photonic core layer. A photonic coupling device may be in the photonic core layer, and may be, as examples, at least one of a grating coupler or a photodetector. A concave mirror may extend into at least the second insulating layer. In some embodiments, the concave mirror may extend through the second insulating layer and into the first insulating layer.

Abstract: A microelectronic assembly (300) or system (1500) includes at least one microelectronic package (100) having a microelectronic element (130) mounted face up above a first surface (108) of a substrate (102), one or more columns (138, 140) of contacts (132) extending in a first direction (142) along the microelectronic element front face. Columns (104A, 105B, 107A, 107B) of terminals (105 107) exposed at a second surface (110) of the substrate extend in the first direction. First terminals (105) exposed at surface (110) in a central region (112) thereof having width (152) not more than three and one-half times a minimum pitch (150) of the columns of terminals can be configured to carry address information usable to determine an addressable memory location. An axial plane of the microelectronic element can intersect the central region.

Abstract: In an embodiment, a quantum device includes an interposer layer comprising a set of vias. In an embodiment, the quantum device includes a dielectric layer formed on a first side of the interposer, the dielectric layer including a set of transmission lines communicatively coupled to the set of vias. In an embodiment, the quantum device includes a plurality of qubit chips coupled to an opposite side of the interposer layer, each qubit chip of the plurality of qubit chips including: a plurality of qubits on a first side of the qubit chip and a plurality of protrusions on a second side of the qubit chip. In an embodiment, the quantum device includes a heat sink thermally coupled with the plurality of qubit chips, the heat sink comprising a plurality of recesses aligned with the plurality of protrusions of the plurality of qubit chips.

Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.

Abstract: Semiconductor devices and methods of forming are provided. A molding compound extends along sidewalls of a first die and a second die. A redistribution layer is formed over the first die, the second die, and the molding compound. The redistribution layer includes a conductor overlying a gap between the first die and the second die. The conductor is routed at a first angle over an edge of the first die. The first angle is measured with respect to a straight line that extends along a shortest between the first die and the second die, and the first angle is greater than 0.

Abstract: A circuit module includes a substrate on which a first electrode and a second electrode are provided, a first electronic component, and a first resin layer. The first electrode includes a first electrode base body and a first plating film. The second electrode and the first electronic component are covered with the first resin layer. The second electrode includes a second electrode base body, a metal column, whose one end is directly connected to the second electrode base body and another end is positioned in an inner side relative to an outer surface of the first resin layer, a second plating film with a cylindrical shape covering a side surface of a connection body of the second electrode base body and the metal column, and a covering portion connected to the other end of the metal column.

Abstract: An electronic package can include modulated mesh planes for reducing crosstalk between adjacent signal wires within the electronic package. Modulated mesh planes above and below a wiring plane can include sets of adjacent wires arranged in an orientation parallel to signal wires within the wiring plane, and sets of adjacent wires arranged in an orientation perpendicular to the signal wires. The sets of wires in each of the mesh planes are each electrically interconnected and insulated by a dielectric layer from the signal wires. The electronic package also includes a region of the mesh planes having the adjacent wires that are arranged in an orientation perpendicular to the signal wires separated by a first distance, and another region of the mesh planes having adjacent wires perpendicular to the signal wires separated by a distance greater than the first distance.

Abstract: A semiconductor package structure includes a first insulating layer, a first conductive layer, a multi-layered circuit structure, a protection layer, and a semiconductor chip electrically connected to the multi-layered circuit structure. The first insulating layer defines a first through hole extending through the first insulating layer. The first conductive layer includes a conductive pad disposed in the first through hole and a trace disposed on an upper surface of the first insulating layer. The multi-layered circuit structure is disposed on an upper surface of the first conductive layer. The multi-layered circuit structure includes a bonding region disposed on the conductive pad of the first conductive layer and an extending region disposed on the trace of the first conductive layer. The protection layer covers the upper surface of the first insulating layer and the extending region of the multi-layered circuit structure, and exposes the bonding region of the multi-layered circuit structure.

Abstract: A semiconductor device provided according to an aspect of the present disclosure includes a semiconductor element, a bonding target, a first wire, a wire strip and a second wire. The bonding target is electrically connected to the semiconductor element. The first wire is made of a first metal. The first wire includes a first bonding portion bonded to the bonding target and a first line portion extending from the first bonding portion. The wire strip is made of the first metal. The wire strip is bonded to the bonding target. The second wire is made of a second metal different from the first metal. The second wire includes a second bonding portion bonded to the bonding target via the wire strip and a second line portion extending from the second bonding portion.

Abstract: An RFID label with protection of the RFID function includes an RFID transponder chip and a carrier substrate, on which the RFID transponder chip is disposed. Furthermore, at least one structure element in vertical projection is disposed laterally offset from the RFID transponder chip. The at least one structure element acts as a spacer and, in case of an external mechanical stress, prevents a direct force action on the transponder chip and a junction to an attached antenna structure.

Abstract: It is an object of the present invention to provide a semiconductor module which suppresses a break in a current path and occurrence of arc discharge when a semiconductor chip is short-circuited. A semiconductor module 100 according to the present invention includes at least one semiconductor chip 2, a housing 5 in which the semiconductor chip 2 is stored, and at least one pressurizing member which is placed between an upper electrode 2a of the semiconductor chip 2 and an upper-side electrode 3 provided in the housing 5 and electrically connects the upper electrode 2a and the upper-side electrode 3, the pressurizing member 10 is elastic, and the pressurizing member 10 includes a conductive block 12 and a plate spring member 11 including current paths 11a and 11b which are opposed to each other with at least a part of the conductive block 12 located between the current paths 11a and 11b.