Abstract: A embedded integrated circuit package is provided, the embedded integrated circuit package including: at least one chip arranged over a chip carrier, the at least one chip including a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one chip; a plurality of electrical interconnects formed through the encapsulation material, wherein each electrical interconnect is electrically connected to a chip contact pad; and a structure formed between the electrical interconnects of the embedded integrated circuit package, wherein the structure increases the creepage resistance between the electrical interconnects.

Abstract: An integrated circuit (IC) package includes an IC die having a first surface and a second surface opposite of the first surface. The IC package includes first contact members coupled to the second surface of the IC die. The IC package includes a bottom substrate having a first surface and a second surface opposite of the first surface, where the first surface of the bottom substrate is coupled to the second surface of the IC die via the first contact members. The IC package includes an interposer substrate coupled to the first surface of the IC die via an adhesive material, where the adhesive material is disposed on at least a surface of the interposer substrate. The IC package includes second contact members coupled along a periphery of the interposer substrate, where the interposer substrate is coupled to the first surface of the bottom substrate via the second contact members.

Abstract: A method of implementing use cases includes associating a use case with each of a plurality of devices capable of being used or accessed by a user. The method also includes providing a plurality of stackable blades, each providing a standard physical interface and being configured to implement a solution to the use case associated with each of the plurality of devices. The method further includes stacking the plurality of stackable blades to form an interconnected stack. Each of the plurality of stackable blades are coupled using the standard physical interface. The method also includes executing a first purpose corresponding to a first use case and executing a second purpose corresponding to a second use case. Embodiments provide an electronic ecosystem featuring ubiquitous connectivity in which a standard contact array in each component of the ecosystem assures interoperability between heterogeneous devices.

Abstract: A semiconductor device includes an insulating circuit substrate mounted with at least one semiconductor element; a resin case having a bottom surface portion attached with the insulating circuit substrate and a side surface portion enclosing a periphery of the bottom surface portion; a lead molded integrally with the resin case and provided on a periphery of the insulating circuit substrate to be positioned on a surface of the bottom surface portion inside the resin case, the lead partially extending from inside the resin case to outside the resin case; and a sealing resin filled inside the resin case. A depressed portion is formed on two sides of the lead along a peripheral edge of the bottom surface portion inside the resin case.

Abstract: Semiconductor chips are disposed on an insulating substrate with conductive patterns, and a printed circuit board with metal pins is disposed above the insulating substrate with conductive patterns, with the semiconductor chips therebetween. A plurality of external lead terminals is fixed to the insulating substrate with conductive patterns, with the plurality of external lead terminals disposed adjacent to each other in parallel. Furthermore, metal foil pieces formed on front and rear surfaces of the printed circuit board with metal pins respectively so as to face each other, are disposed above the semiconductor chips.

Abstract: Through vias extend through a substrate between a frontside surface and a backside surface, the through vias comprising active surface ends at the frontside surface. A frontside redistribution structure is coupled to the active surface ends, the frontside redistribution structure exerting force on the frontside surface, e.g., due to a difference in the thermal coefficient of expansion (TCE) between the frontside redistribution structure and the substrate. To prevent warpage of the substrate, a backside warpage control structure is coupled to the backside surface of the substrate. The backside warpage control structure exerts an equal but opposite force to the force exerted by the frontside redistribution structure thus avoiding warpage of the substrate.

Abstract: A method of manufacturing a semiconductor device includes the steps of immersing a substrate in a solution containing metal ions to adhere a metal catalyst to a surface of the substrate, immersing the substrate with the metal catalyst adhered thereto in an electroless plating solution to electrolessly plate a layer on the substrate, immersing the substrate in an electroplating solution to electroplate a layer on the electrolessly plated layer using the electrolessly plated layer as a power feeding layer, and forming a metal layer of Cu or Ag on the electroplated layer. The electroplated layer is formed of a different material than the metal layer.

Abstract: A semiconductor package with reduced warpage problem is provided, including: a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; a non-planar shaped heat spreading layer, formed over the spacer; an encapsulant layer, formed, over the circuit board, filling spaces between the non-planar shaped heat spreading layer and the circuit board; and a plurality of solder balls, formed over the second surface of the circuit board.

Abstract: A semiconductor package according to embodiments includes: a semiconductor chip including a front electrode on a front surface thereof and a back electrode on a back surface thereof; a front-side cap portion including an air gap in a portion between the semiconductor chip and the front-side cap portion and a front-side penetrating electrode, and is positioned to face the front surface of the semiconductor chip; a back-side cap portion bonded with a first cap portion to hermetically seal the semiconductor chip, includes an air gap at least in a portion between the semiconductor chip and the back-side cap portion and a back-side penetrating electrode, and is positioned to face the back surface of the semiconductor chip; a front-side connecting portion which electrically connects the front electrode and the front-side penetrating electrode; and a back-side connecting portion which electrically connects the back electrode and the back-side penetrating electrode.

Abstract: A land grid array (LGA) package including a substrate having a plurality of lands formed on a first surface of the substrate, a semiconductor chip mounted on a second surface of the substrate, a connection portion connecting the semiconductor chip and the substrate, and a support layer formed on part of a surface of a first land.

Abstract: A semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.

Abstract: A semiconductor integrated circuit device includes: a rectangular shaped semiconductor substrate; a metal wiring layer formed on or over the semiconductor substrate; and a passivation layer covering the metal wiring layer. A corner non-wiring region where no portion of the metal wiring layer is formed is disposed in a corner of the semiconductor substrate. A slit is formed in a portion of the metal wiring layer which is close to the corner of the semiconductor substrate. The passivation layer includes a first passivation layer which is formed on the metal wiring layer and a second passivation layer which is formed on the first passivation layer. The first passivation layer is formed of a material that is softer than a material of the second passivation layer.

Abstract: Disclosed herein are a semiconductor package and a method of manufacturing the same. The semiconductor package includes: a substrate including a mounting electrode formed on both sides and a wiring; a plurality of first electronic devices mounted on the substrate; a second electronic devices mounted on the substrate; and a via through which the wiring of the substrate and the second electronic devices are connected.

Abstract: A secure integrated circuit package is provided. The secure integrated circuit package includes a first substrate having an upper surface and a lower surface. A first plurality of solder balls are arranged in a pattern on the lower surface of the first substrate. A die is coupled to the upper surface of the first substrate. A second plurality of solder balls is coupled to the upper surface of the substrate and arranged in a ring surrounding the die. A mesh substrate including a mesh protection grid is coupled to the second plurality of solder balls.

Abstract: Semiconductor packages are provided that have a base plate with a matrix of pure silver or a silver alloy and reinforcement particles. The reinforcement particles can include high thermal conductivity, low CTE particles selected from the group consisting of diamond, cubic boron nitride (c-BN), silicon carbide (SiC), and any combinations thereof. In some embodiments, the base plate is entirely comprised of the composite. In other embodiments, the base plate has a core made of the composite. The core can include at least one outer layer on the core. The semiconductor package can include one or more dice or transistors on the base plate, an insulated frame on the base plate, and one or more leads on the insulated frame.

Abstract: In a semiconductor device, a conductor pattern is disposed in a position overlapped by a semiconductor chip in a thickness direction over the mounting surface (lower surface) of a wiring board. A solder resist film (insulating layer) covering the lower surface of the wiring board has apertures formed such that multiple portions of the conductor pattern are exposed. The conductor pattern has conductor apertures. The outlines of the apertures and the conductor apertures overlap with each other, in a plan view, respectively.

Abstract: A method includes providing a substrate having a seal ring region and a circuit region, forming a seal ring structure over the seal ring region, forming a first frontside passivation layer above the seal ring structure, etching a frontside aperture in the first frontside passivation layer adjacent to an exterior portion of the seal ring structure, forming a frontside metal pad in the frontside aperture to couple the frontside metal pad to the exterior portion of the seal ring structure, forming a first backside passivation layer below the seal ring structure, etching a backside aperture in the first backside passivation layer adjacent to the exterior portion of the seal ring structure, and forming a backside metal pad in the backside aperture to couple the backside metal pad to the exterior portion of the seal ring structure. Semiconductor devices fabricated by such a method are also provided.

Abstract: A semiconductor module with radiation fins includes a semiconductor module including a metal base. The metal base has an outer circumferential portion surrounding the same and a top panel portion surrounded by the outer circumferential portion. One side of the top panel portion is disposed with a plurality of semiconductor chips through a plurality of corresponding insulating substrates and the other side of the top panel portion is disposed with radiation fins. The plurality of semiconductor chips is connected to electric wiring to electrically connect to the outside of the semiconductor module. A thickness of the top panel portion is less than a thickness of the outer circumferential portion. The top panel portion between the insulating substrates includes a groove having an opening narrower than a bottom portion. The plurality of semiconductor chips is sealed together with the groove by resin.

Abstract: A semiconductor element housing package includes a rectangular ceramic package having a recess section on an upper surface thereof or a penetration section from the upper surface to a lower surface thereof, and a heat radiation plate attached to the lower surface of the ceramic package, extending from one side toward the other side of the lower surface up to a region in which the heat radiation plate overlays the recess section or the penetration section, which plate has a width on a side of the other side which is narrower than that on a side of one side. The package includes a plurality of first lead pins disposed on the lower surface of the ceramic package along the other side, and a pair of second lead pins disposed on the lower surface of the ceramic package on both sides of a narrow portion of the heat radiation plate.

Abstract: A method of fabricating a semiconductor package includes forming a plurality of terminals on a sheet carrier, molding the sheet carrier with a first molding compound, creating electrical paths for a first routing layer, plating the first routing layer, placing dice on the first routing layer, encapsulating the dice with a second molding compound, removing at least a portion of the sheet carrier, and singulating the package from other packages.

Abstract: A multilayered printed circuit board or a substrate for mounting a semiconductor device includes a semiconductor device, a first resin insulating layer accommodating the semiconductor device, a second resin insulating layer provided on the first resin insulating layer, a conductor circuit provided on the second resin insulating layer, and via holes for electrically connecting the semiconductor device to the conductor circuit, wherein the semiconductor device is accommodated in a recess provided in the first resin insulating layer, and a metal layer for placing the semiconductor device is provided on the bottom face of the recess. A multilayered printed circuit board in which the installed semiconductor device establishes electrical connection through the via holes is provided.

Abstract: A light emitting diode package including a package body with a cavity, a plurality of light emitting diode (LED) chips in the cavity, a plurality of wires connected to the plurality of LED chips, and a plurality of lead frames in the package body, wherein the lead frames comprise a first lead frame electrically connected to a first electrode of a first LED chip, a second lead frame electrically connected to a second electrode of the first LED chip and a second electrode of a second LED chip, a third lead frame electrically connected to a first electrode of the second LED chip, and fourth lead frame electrically connected to a second electrode of a third LED chip. Further, ends of the lead frames are exposed outside of the package body and penetrate the package body, and the first electrodes are P electrodes and the second electrodes are N electrodes.

Abstract: Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections have been disclosed. One exemplary embodiment comprises a PQFN semiconductor package comprising a leadframe, a driver integrated circuit (IC) coupled to the leadframe, a plurality of vertical conduction power devices coupled to the leadframe, and a plurality of wirebonds providing electrical interconnects, including at least one wirebond from a top surface electrode of one of the plurality of vertical conduction power devices to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power devices. In this manner, efficient multi-chip circuit interconnections can be provided in a PQFN package using low cost leadframes.

Abstract: A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for supporting the tab, leads having respective surfaces exposed to outer edge portions of a back surface of the sealing body, and wires connecting pads formed on the semiconductor chip and the leads. End portions of the suspension leads positioned in an outer periphery portion of the sealing body are unexposed to the back surface of the sealing body, but are covered with the sealing body. Stand-off portions of the suspending leads are not formed in resin molding. When cutting the suspending leads, corner portions of the back surface of the sealing body are supported by a flat portion of a holder portion in a cutting die having an area wider than a cutting allowance of the suspending leads, whereby chipping of the resin is prevented.

Abstract: A semiconductor package with reduced warpage problem is provided, including: a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board, having a first cross sectional dimension; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; an encapsulant layer, formed over the circuit board, covering the semiconductor chip and surrounding the spacer; a heat spreading layer, formed over the encapsulant layer and the spacer; and a plurality of solder balls, formed over the second surface of the circuit board, wherein a ratio between the first cross sectional dimension and the second cross sectional dimension is about 1:2-1:6.

Abstract: A surface-mountable electronic device free of leads has a plurality of solderable connection surfaces at its lower side, with at least one of the connection surfaces having a rectangular portion. The outline of this rectangular portion corresponds to a connection surface of the JEDEC Standard MO-236 or of any other standard according to which the respective connection surface should not extend directly up to a side edge of the lower device side. The at least one connection surface furthermore has an extension section which extends, starting from the rectangular portion, in the direction of a side edge of the lower side of the device.

Abstract: An electronic component comprises: a resin frame; a semicionductor substrate housed in the resin frame; a plate shape metal member having at least one end fixed in the resin frame at a position spaced apart from the semiconductor substrate; an electrical connection region portion formed on the surface on the side of the plate shape metal member of the semiconductor substrate with an electrically conductive material; and a solder layer formed on the surface on the side of the plate shape metal member of the electrical connection region portion, wherein the plate shape metal member supports the semiconductor substrate without contact through the solder layer and the electrical connection region portion, and is electrically connected to the electrical connection region portion.

Abstract: In various embodiments, a chip package is provided. The chip package may include at least one chip having a plurality of pressure sensor regions and encapsulation material encapsulating the chip.

Abstract: An electronic board includes conducting traces having an upper surface at least partially sunken with respect to a gluing surface of the board. A surface mount technology electronic device for mounting to the board includes insulating windows that define gluing sites within one or more pins. An electronic system is formed by one or more of such surface mount technology electronic devices mounted to electronic board. The devices are attached using a wave soldering technique that flows through channels formed by the sunken conductive traces.

Abstract: An integrated circuit package system includes a substrate having an opening provided therein, forming a conductor in the opening having a closed end at the bottom, attaching an integrated circuit die over the substrate, and connecting a die interconnect to the integrated circuit die and the closed end of the conductor.

Abstract: A semiconductor package with reduced warpage problem is provided, including: a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board, having a first cross sectional dimension; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; an encapsulant layer, formed over the circuit board, covering the semiconductor chip and surrounding the spacer; a heat spreading layer, formed over the encapsulant layer and the spacer; and a plurality of solder balls, formed over the second surface of the circuit board.

Abstract: An SMT LED device includes an LED and a circuit board carrying the LED. The circuit board has two copper pads thereon, each being provided with a solder on an inner later side thereof which faces the other copper pad. The LED includes two pins and each pin includes a horizontal protrusion and a vertical portion. The LED is mounted on the circuit board between the two copper pads. The solders securely and electrically connect the two pins of the LED with the circuit board.

Abstract: A method for fabricating a packaging structure having an embedded semiconductor element includes: providing a substrate having opposite first and second surfaces and at least an opening penetrating the first and second surfaces; forming a first metallic frame around the periphery of the opening on the first surface; forming at least an opening inside the first metallic frame by laser ablation; disposing a semiconductor chip in the opening; forming a first dielectric layer on the first and second surfaces and the chip; forming a first wiring layer on the first dielectric layer of the first surface; and forming a first built-up structure on the first dielectric layer and the first wiring layer of the first surface. A shape of the opening is precisely controlled through the first metallic frame around the periphery of the predefined opening region, thereby allowing the chip to be precisely embedded in the substrate.

Abstract: A power semiconductor device comprising a power semiconductor module and a heat sink; and a method for its manufacture. The module has a cooling plate, with an opening delimited by a lateral first surface thereof extending circumferentially around the opening. The cooling plate is arranged in the opening and has a lateral first surface which extends circumferentially around the cooling plate. The two first surfaces are at a respective angle of less than 90° with respect to a main surface of the cooling plate facing the power semiconductor components. The two first surfaces are pressed together, extending circumferentially along the first surface of the cooling plate and extending circumferentially along the first surface of the heat sink. The inventive power semiconductor device has good heat conduction from the power semiconductor components to the heat sink through which a liquid can flow, and which is reliably leaktight over the long term.

Abstract: A semiconductor package includes a wiring board; a semiconductor chip mounted on the wiring board; and a radiation plate mounted on the semiconductor chip, including an insulating member including a resin that is the same as a resin included in the wiring board, as a main constituent, a first metal foil formed on a first surface of the insulating member, a second metal foil formed on a second surface of the insulating member, the second surface being an opposite to the first surface, the radiation plate being provided with a through hole that penetrates the first metal foil, the insulating member and the second metal foil, and a metal layer formed to cover the inner surface of the through hole to thermally connect the first metal foil and the second metal foil by penetrating the insulating member in a thickness direction.

Abstract: Semiconductor packages having lead frames include a lead frame, which supports a semiconductor chip and is electrically connected to the semiconductor chip by bonding wires, and a molding layer encapsulating the semiconductor chip. The lead frame includes first lead frames extending in a first direction and second lead frames extending in a second direction. The first lead frames may run across the semiconductor chip and support the semiconductor chip and the second lead frames may run across the bottom surface of the semiconductor chip.

Abstract: A method for tracking an interposer die of a stacked silicon interconnect technology (SSIT) product includes forming a plurality of dummy components on the interposer die, and modifying one or more of the plurality of dummy components on the interposer die to form a unique identifier for the interposer die. An apparatus for a stacked silicon interconnect technology (SSIT) product includes an interposer die, and a plurality of dummy components at the interposer die. One or more of the plurality of dummy components is modifiable to form a unique identifier for the interposer die.

Abstract: A semiconductor device of the present invention comprises: an outer package; a first lead frame including a first relay lead, a first die pad with a power element mounted thereon, and a first external connection lead which has an end protruding from the outer package; and a second lead frame including a second relay lead, a second die pad with a control element mounted thereon, and a second external connection lead which has an end protruding from the outer package, wherein the first die pad and the second die pad or the first external connection lead and the second relay lead are joined to each other at a joint portion, and an end of the second relay lead extending from a joint portion with the first relay lead is located inside the outer package.

Abstract: Certain embodiments provide a semiconductor package including a base metal portion, a frame body, a plurality of wires, and a lid body. The base metal portion includes multiple grooves on a back surface, and can mount a semiconductor chip on a front surface. The frame body is arranged on the front surface of the base metal portion. The plurality of wires are arranged to penetrate through a side surface of the frame body. The lid body is arranged on the frame body.

Abstract: A BGA type packaged integrated circuit (IC) die has an exposed coronal heat spreader. The die, which is attached to a substrate, is encapsulated in a central segment of molding compound. The central segment is laterally surrounded by, and separated by a moat from a ring segment of molding compound, to a form a slot. The coronal heat spreader is inserted into the slot to cap the central segment. The coronal heat spreader is attached to the substrate and to the central segment with thermal glue. In operation, at least some of the heat generated by the die is dissipated through the coronal heat spreader.

Abstract: A semiconductor package improves reliability of heat emitting performance by maintaining a heat emitting lid stacked on a top surface of a semiconductor chip at a tightly adhered state. A highly adhesive interface material and a thermal interface material are applied to the top surface of the semiconductor chip. The highly adhesive interface material insures that the heat emitting lid is bonded to the top surface while the thermal interface material insures excellent heat transfer between the top surface and the heat emitting lid.

Abstract: A microelectronic assembly 5 can include first and second microelectronic packages 10a, 10b mounted to respective first and second opposed surfaces 61, 62 of a circuit panel 60. Each microelectronic package 10a, 10b can include a substrate 20 having first and second apertures 26a, 26b extending between first and second surfaces 21, 22 thereof, first and second microelectronic elements 30a, 30b each having a surface 31 facing the first surface of the substrate and a plurality of contacts 35 exposed at the surface of the respective microelectronic element and aligned with at least one of the apertures, and a plurality of terminals 25a exposed at the second surface in a central region 23 thereof. The apertures 26a, 26b of each substrate 20 can have first and second parallel axes 29a, 29b extending in directions of the lengths of the respective apertures. The central region 23 of the second surface 22 of each substrate 20 can be disposed between the first and second axes 29a, 29b of the respective substrate 20.

Abstract: The preferred embodiment of the present invention can prevent signal distortions such as stress, or the like, occurring at the time of power delivery due to the difference in the lengths of the metal wires for electrically connecting each of the plurality of semiconductor chips formed on the dual die package substrate.

Abstract: A package structure is disclosed, which includes: a carrier having a recessed portion formed on a lower side thereof and filled with a dielectric material; a semiconductor element disposed on an upper side of the carrier and electrically connected to the carrier; and an encapsulant formed on the upper side of the carrier for encapsulating the semiconductor element. Therein, the dielectric material is exposed from the encapsulant. As such, when the carrier is disposed on a circuit board, the dielectric material is sandwiched between the lower side of the carrier and the circuit board to form a decoupling capacitor, thereby improving the power integrity.

Abstract: A power semiconductor device comprises a lead frame unit, a control die, a first MOSFET die and a second MOSFET die, wherein the lead frame unit comprises at least a die paddle for mounting the first and second MOSFET dies, a first pin and a second pin for connecting to top electrodes of the first and second MOSFET dies, a first row of carrier pins and a second row of carrier pins disposed in-line with the first and second pins respectively for the control die to mount thereon.

Abstract: A semiconductor device has a base substrate having a plurality of metal traces and a plurality of base vias. An opening is formed through the base substrate. At least one die is attached to the first surface of the substrate and positioned over the opening. A cover substrate has a plurality of metal traces. A cavity in the cover substrate forms side wall sections around the cavity. The cover substrate is attached to the base substrate so the at least one die is positioned in the interior of the cavity. Ground planes in the base substrate are coupled to ground planes in the cover substrate to form an RF shield around the at least one die.

Abstract: An integrated circuit package system including: providing a die pad with a top, sides, and a bottom, the bottom having a relief with a flat surface and defining a wall and a center pad; mounting a barrier under the bottom of the die pad; mounting an integrated circuit die on the top of the die pad; encapsulating the integrated circuit die and the top and sides of the die pad with the wall preventing encapsulation from flowing along the barrier to reach the center pad; and mounting an external interconnect on the center pad.

Abstract: A photovoltaic cell manufacturing method is disclosed. Methods include manufacturing a photovoltaic cell having a selective emitter and buried contact (electrode) structure utilizing nanoimprint technology. The methods include providing a semiconductor substrate having a first surface and a second surface opposite the first surface; forming a first doped region in the semiconductor substrate adjacent to the first surface; performing a nanoimprint process and an etching process to form a trench in the semiconductor substrate, the trench extending into the semiconductor substrate from the first surface; forming a second doped region in the semiconductor substrate within the trench, the second doped region having a greater doping concentration than the first doped region; and filling the trench with a conductive material. The nanoimprint process uses a mold to define a location of an electrode line layout.

Abstract: A structure may include a spacer element overlying a first portion of a first surface of a substrate; first terminals at a second surface of the substrate opposite the first surface; and second terminals overlying a third surface of the spacer element facing away from the first surface. Traces extend from the second terminals along an edge surface of the spacer element that extends from the third surface towards the first surface, and may be electrically coupled between the second terminals and the first terminals or electrically conductive elements at the first surface. The spacer element may at least partially define a second portion of the first surface, which is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some of the conductive elements are at the second portion and may permit connection with such microelectronic element.

Abstract: An advantageous method and system for realizing electrically very reliable and mechanically extremely stable vias for components whose functionality is realized in a layer construction on a conductive substrate. The via (Vertical Interconnect Access), which is led to the back side of the component and which is used for the electrical contacting of functional elements realized in the layer construction, includes a connection area in the substrate that extends over the entire thickness of the substrate and is electrically insulated from the adjoining substrate by a trench-like insulating frame likewise extending over the entire substrate thickness. According to the present system, the trench-like insulating frame is filled up with an electrically insulating polymer.