Abstract: In a vertically integrated microelectronic package, a first microelectronic device is coupled to an upper surface of a circuit platform in a wire bond-only surface area thereof. Wire bond wires are coupled to and extends away from an upper surface of the first microelectronic device. A second microelectronic device in a face-down orientation is coupled to upper ends of the wire bond wires in a surface mount-only area. The second microelectronic device is located above and at least partially overlaps the first microelectronic device. A protective layer is disposed over the circuit platform and the first microelectronic device. An upper surface of the protective layer has the surface mount-only area. The upper surface of the protective layer has the second microelectronic device disposed thereon in the face-down orientation in the surface mount-only area for coupling to the upper ends of the first wire bond wires.

Abstract: The semiconductor chip package comprises a semiconductor chip, and an encapsulation body encapsulating the semiconductor chip, wherein the encapsulation body comprises a semiconductor chip; an encapsulation body encapsulating the semiconductor chip, wherein the encapsulation body comprises two opposing main faces and side faces which connect the two main faces with each other, wherein the side face have a smaller surface area than the main faces, respectively, and wherein a marking is provided on at least one of the side faces.

Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

Abstract: Structures and formation methods of a chip package are provided. The method includes forming multiple conductive structures over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes disposing a mold over the carrier substrate. The method further includes forming a protection layer between the mold and the carrier substrate to surround the semiconductor die and the conductive structures. In addition, the method includes removing the mold.

Abstract: A semiconductor package structure includes a conductive structure, at least two semiconductor elements and an encapsulant. The conductive structure has a first surface and a second surface opposite the first surface. The semiconductor elements are disposed on and electrically connected to the first surface of the conductive structure. The encapsulant covers the semiconductor elements and the first surface of the conductive structure. The encapsulant has a width ‘L’ and defines at least one notch portion. A minimum distance ‘d’ is between a bottom surface of the notch portion and the second surface of the conductive structure. The encapsulant has a Young's modulus ‘E’ and a rupture strength ‘Sr’, and L/(K×d)>E/Sr, wherein ‘K’ is a stress concentration factor with a value of greater than 1.2.

Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

Abstract: A method of forming a packaged semiconductor device includes providing a conductive frame structure. The conductive frame structure includes a first frame having leadfingers configured for directly attaching to a semiconductor device, such as an integrated power semiconductor device that includes both power devices and logic type devices. The leadfingers are further configured to provide high current capacity and a high thermal dissipation capacity for the power device portion of the semiconductor device. In one embodiment, the conductive frame structure further includes a second frame joined to the first frame. The second frame includes a plurality of leads configured to electrically connect to low power device portions of the semiconductor device. A package body is formed to encapsulate the semiconductor device and at least portions of the leadfingers and leads.

Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

Abstract: Some embodiments relate to an electronic package. The electronic package includes a substrate and a die attached to the substrate. The electronic package further includes an underfill positioned between the die and the substrate due to capillary action. A support surrounds the die. The support provides the same beneficial fillet geometry on all die edges. Therefore, the support provides similar stress reduction on all die edges. Other embodiments relate to method of fabricating an electronic package. The method includes attaching a die to a substrate and inserting an underfill between the die and the substrate using capillary action. The method further includes placing a support around the die such that the support surrounds the die.

Abstract: An electronic device may include leads, an IC having first and second bond pads, and an encapsulation material adjacent the leads and the IC so the leads extend to a bottom surface of the encapsulation material defining first contact pads. The electronic device may include bond wires between the first bond pads and corresponding ones of the leads, and conductors extending from corresponding ones of the second bond pads to the bottom surface of the encapsulation material defining second contact pads.

Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

Abstract: An embodiment a device package includes a semiconductor die, a molding compound extending along sidewalls of the semiconductor die, and a planarizing polymer layer over the molding compound and extending along the sidewalls of the semiconductor die. The molding compound includes first fillers, and the planarizing polymer layer includes second fillers smaller than the first fillers. The device package further includes one or more fan-out redistribution layers (RDLs) electrically connected to the semiconductor die, wherein the one or more fan-out RDLs extend past edges of the semiconductor die onto a top surface of the planarizing polymer layer.

Abstract: A molded sensor package includes a leadframe having a sensor die attached to the leadframe, a magnet aligned with the sensor die and a single molding compound encasing the sensor die and attaching the magnet to the leadframe. A method of manufacturing the molded sensor package includes loading the magnet and the leadframe into a molding tool so that the magnet is aligned with the sensor die in the molding tool, molding the magnet and the sensor die with the same molding compound while loaded in the molding tool and curing the molding compound so that the magnet is attached to the leadframe by the same molding compound that encases the sensor die.

Abstract: A semiconductor device includes a die pad, a semiconductor chip with a bonding pad being formed, a lead one end of which is located in the vicinity of the semiconductor chip, a coupling wire that connects an electrode and the lead, and a sealing body that seals the semiconductor chip, the coupling wire, a part of the lead, and a part of the die pad. A lower surface of the die pad is exposed from a lower surface of the sealing body, the die pad and the coupling wire are comprised of copper, and a thickness of the semiconductor chip is larger than the sum of a thickness of the die pad and a thickness from an upper surface of the semiconductor chip to an upper surface of the sealing body.

Abstract: An organic light emitting diode (OLED) display includes a substrate, a thin film transistor (TFT) on the substrate, an OLED connected to the TFT and configured to emit white light, and a capping layer on the OLED. The capping layer includes a first high refractive index layer, a first low refractive index layer, a second high refractive index layer, and a second low refractive index layer that are sequentially stacked.

Abstract: A semiconductor package includes a substrate comprising a chip area and a peripheral area, at least one semiconductor chip mounted on the chip area, a plurality of stubs respectively on a plurality of pads arranged in the peripheral area, and a molding unit configured to cover at least a partial area of the at least one semiconductor chip and at least a partial area of the plurality of stubs on the substrate while exposing an upper surface of at least one of the plurality of stubs to outside of the molding unit, wherein at least a partial area of the upper surface of at least one of the plurality of stubs is substantially flat.

Abstract: It has been discovered that poor TDDB reliability of microelectronic device capacitors with organic polymer material in the capacitor dielectric is due to water molecules infiltrating the organic polymer material when the microelectronic device is exposed to water vapor in the operating ambient. Water molecule infiltration from water vapor in the ambient is effectively reduced by a moisture barrier comprising a layer of aluminum oxide formed by an atomic layer deposition (ALD) process. A microelectronic device includes a capacitor with organic polymer material in the capacitor dielectric and a moisture barrier with a layer of aluminum oxide formed by an ALD process.

Abstract: A chip package including a first device substrate is provided. The first device substrate is attached to a first surface of a second device substrate. A third device substrate is attached to a second surface of the second device substrate opposite to the first surface. An insulating layer covers the first, second and third device substrates and has at least one opening therein. At least one bump is disposed under a bottom of the opening. A redistribution layer is disposed on the insulating layer and electrically connected to the bump through the opening. A method for forming the chip package is also provided.

Abstract: An electronic package that includes a substrate and a die attached to the substrate. A plurality of supports attached to the substrate adjacent to the die. At least one support in the plurality of supports is positioned adjacent to at least one corner of the die such that the at least one corner of the die is positioned adjacent to the at least one support. Other example forms relate to a method of fabricating an electronic package. The method includes securing a die to a substrate and securing a plurality of supports to the substrate such that at least one support is adjacent to at least one corner of the die.

Abstract: Pre-encapsulated lead frames suitable for use in microelectronic device packages are disclosed. Individual lead frames can include a set of multiple lead fingers arranged side by side with neighboring lead fingers spaced apart from each other by a corresponding gap. An encapsulating compound at least partially encapsulates the set of lead fingers without encapsulating a microelectronic device. The encapsulating compound can generally fill the plurality of gaps between two adjacent lead fingers.

Abstract: A package structure includes a first member that surrounds a semiconductor device, a heat insulating material that surrounds an outer side of the first member, and a second member that surrounds an outer side of the head insulating material. The heat insulating material has a density and a thermal conductivity lower than those of the first and second members. The first member has a heat capacity larger than that of the second member.

Abstract: A method includes providing a first and a second joining partner each having a first main surface, wherein at least a portion of the first main surfaces of the first and joining partners each comprise a metal layer. The method further includes applying a plurality of solder preforms to the metal layer of the first main surface of at least one of the first and second joining partners, positioning the first and second joining partners so that the solder preforms contact the metal layers of the first main surfaces of the first and second joining partners, and melting the plurality of solder preforms under pressure to form a single continuous thin layer area interconnect comprising a diffusion solder bond which bonds together the metal layers of the of the first main surfaces of the first and second joining partners.

Abstract: Provided is a power semiconductor module wherein stress generated at a soldering section of a relay terminal is relaxed. A power semiconductor module (1) is provided with a substrate (2), relay terminals (9, 10), external connecting terminals (13, 14) and a relay terminal holding member (6). The relay terminals (9, 10) are connected to the substrate (2) with a solder (4) therebetween. The external connecting terminals (13, 14) are bonded to the relay terminals (9, 10), respectively. The non-conductive relay terminal holding member (6) holds end portions of the relay terminals (9, 10) said end portions being on the side bonded to the solder (4).

Abstract: A power semiconductor module includes: a plurality of semiconductor element substrates disposed on the same plane, each of which includes an insulating substrate with a front-side electrode formed on one of the surfaces of an insulator plate and a back-side electrode formed on the other surface of the insulator plate and a power semiconductor element fixed on a surface of the front-side electrode; and a wiring member that electrically connects with each other the semiconductor element substrates adjacent to each other; and the semiconductor element substrates and the wiring member are molded with mold resin; wherein the mold resin is provided with a recessed part, between the insulating substrates adjacent to each other, which is not filled with the resin constituting the mold resin to a predetermined depth from the side of the back-side electrode.

Abstract: It will be understood by those skilled in the art that there is disclosed in the present application a biometric sensor that may comprise a plurality of a first type of signal traces formed on a first surface of a first layer of a multi-layer laminate package; at least one trace of a second type, formed on a second surface of the first layer or on a first surface of a second layer of the multi-layer laminate package; and connection vias in at least the first layer electrically connecting the signal traces of the first type or the signal traces of the second type to respective circuitry of the respective first or second type contained in an integrated circuit physically and electrically connected to one of the first layer, the second layer or a third layer of the multi-layer laminate package.

Abstract: A picking-up and placement process for electronic devices comprising: (a) providing a first substrate having a plurality of electronic devices formed thereon, the electronic devices being arranged in an array, and each of the electronic devices comprising a magnetic portion; (b) selectively picking-up parts of the electronic devices from the first substrate via a magnetic force generated from an electric-programmable magnetic module; and (c) bonding the parts of the electronic devices picked-up by the electric-programmable magnetic module with a second substrate.

Abstract: A method of manufacturing an optical apparatus is provided. The method includes arranging a photo device above a substrate with an adhesive located between the photo device and the substrate, forming a bonding member that bonds the substrate and the photo device by curing the adhesive, and arranging, above the photo device, a transparent plate and a sealing member. The sealing member covers the photo device and is located between the transparent plate and the substrate. An elastic modulus of the bonding member is 1 GPa or less.

Abstract: A method of fabricating a semiconductor package includes mounting a plurality of semiconductor devices on a substrate; forming a molding member that covers a top surface of the substrate, top surfaces of the semiconductor devices, and sidewall surfaces of the semiconductor devices; sawing the molding member and the substrate along pre-scribing lines of the substrate; and spraying a metallic epoxy material on the sawn molding members using a sprayer to form an antistatic layer on sidewall surfaces and a top surface of each of the sawn molding members.

Abstract: The semiconductor device can prevent damages on a semiconductor chip even when a soldering material is used for bonding the back surface of the semiconductor chip to the junction plane of a chip junction portion such as an island or a die pad. This semiconductor device includes a semiconductor chip and a chip junction portion having a junction plane that is bonded to the back surface of the semiconductor chip with a soldering material. The junction plane is smaller in size than the back surface of the semiconductor chip. This semiconductor device may further include a plurality of extending portions which extend respectively from the periphery of the junction plane to directions parallel with the junction plane.

Abstract: A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise forming a back end of line layer on a dummy substrate, completing at least a first portion of an assembly, and removing the dummy substrate.

Abstract: A chip includes a semiconductor substrate, an electrical connector over the semiconductor substrate, and a molding compound molding a lower part of the electrical connector therein. A top surface of the molding compound is lower than a top end of the electrical connector. A recess extends from the top surface of the molding compound into the molding compound.

Abstract: A semiconductor package includes terminals, each having an exposed surface that is flush with a bottom surface of the semiconductor package, and a layer of interconnection routings disposed within the semiconductor package. At least one interconnection routing is electrically coupled with a terminal and extends planarly therefrom. The semiconductor package also includes at least one die coupled with the layer of interconnection routings. In some embodiments, the semiconductor package also includes one or more additional intermediary layers. Each intermediary layer includes a via layer and an associated routing layer. The associated routing layer includes associated routings. At least one associated routing is electrically coupled with a terminal and extends planarly therefrom. Each via layer couples two routing layers. The semiconductor package also includes a locking mechanism for fastening a package compound with the interconnection routings and the terminals.

Abstract: A semiconductor device includes a first semiconductor chip having a pad electrode formed on an upper surface thereof; a resin section sealing the first semiconductor chip with the upper surface and a side surface of the first semiconductor chip being covered and a lower surface of the first semiconductor chip being exposed; a columnar electrode communicating between the upper surface and the lower surface of the resin section with the upper surface and the lower surface of the columnar electrode being exposed on the resin section and at least a part of the side surface of the columnar electrode being covered; and a bonding wire connecting the pad electrode and the columnar electrode with a part of the bonding wire being embedded in the columnar electrode as one end of the bonding wire being exposed on the lower surface of the columnar electrode and the remaining part of the bonding wire being covered with the resin section, and a method for manufacturing the same.

Abstract: A light emitting apparatus includes a substrate, a light emitter mounted on the substrate, and a lens at least partially covering the light emitter, the lens defining a space about the light emitter. A heat sink is attached to the substrate. The heat sink is configured to dissipate heat from the light emitter via the substrate. The substrate includes an opening communicated with the space. A vent passage is at least partially defined between the heat sink and the substrate, the vent passage communicating the opening in the substrate with an exterior of the heat sink.

Abstract: An EMI shielding package structure includes a substrate unit having a first surface with a die mounting area and a second surfaces opposite to the first surface, metallic pillars formed on the first surface, a chip mounted on and electrically connected to the die-mounting area, an encapsulant covering the chip and the first surface while exposing a portion of each of the metallic pillars from the encapsulant, and a shielding film enclosing the encapsulant and electrically connecting to the metallic pillars. A fabrication method of the above structure by two cutting processes is further provided. The first cutting process forms grooves by cutting the encapsulant. After a shielding film is formed in the grooves and electrically connected to the metallic pillars, the complete package structure is formed by the second cutting process, thereby simplifying the fabrication process while overcoming inferior grounding of the shielding film as encountered in prior techniques.

Abstract: A method of making a multi-level micro-wire structure includes imprinting first micro-channels in a curable first layer over a substrate with a first stamp, curing the first layer, and locating and curing a curable conductive ink in the first micro-channels to form first micro-wires. Second micro-channels are imprinted in a curable second layer in contact with the first layer with a second stamp, the second layer is cured, and a curable conductive ink is located and cured in the second micro-channels to form second micro-wires. At least one of the second micro-channels contacts at least one first micro-wire and a second micro-wire in at least one of the second micro-channels is in electrical contact with at least one first micro-wire.

Abstract: Provided is a chip on film (COF) type semiconductor package. The COF type semiconductor device includes a flexible film, an electrode pattern formed on the flexible film, a semiconductor device disposed on the electrode pattern, a conductive pad disposed between the electrode pattern and the semiconductor device to electrically connect the semiconductor device with the electrode pattern, and a first protective layer which seals the conductive pad and the semiconductor device and is formed on a portion of the electrode pattern and the semiconductor device. The first protective layer includes a heat conductive material for dissipating heat generated from the semiconductor device.

Abstract: A semiconductor module is provided for shortening a manufacturing tact time, reducing manufacturing costs and for ensuring reliability of a bonding portion. The semiconductor module includes a substrate formed of a metal, an insulating layer formed on the substrate, a plurality of wiring patterns formed on the insulating layer, a bare-chip transistor mounted on one wiring pattern via a solder, and copper connectors that connect electrodes formed on the bear-chip transistor and other wiring patterns via a solder. The copper connectors have a bridge shape, have a width-reduced portion formed in the vicinity of the bonding face to the electrodes, and have a stress-reducing portion formed on the bonding face bonded to the electrode.

Abstract: Chip cracking that occurs when a dicing step using a blade is carried out to acquire semiconductor chips with the reduced thickness of a semiconductor wafer is suppressed. When the semiconductor wafer is cut at the dicing step for the semiconductor wafer, a blade is advanced as follows: in dicing in a first direction (Y-direction in FIG. 12) along a first straight line, the blade is advanced from a first point to a second point. The first point is positioned in a first portion and the second point is opposed to the first point with a second straight line running through the center point of the semiconductor wafer in between.

Abstract: A semiconductor wafer contains a plurality of semiconductor die. A plurality of bumps is formed on the semiconductor wafer. The bumps are electrically connected to contact pads on an active surface of the die. The bumps can also be pillars or stud bumps. A first encapsulant is deposited over the bumps. The semiconductor wafer is singulated to separate the die by cutting channels partially through the wafer and back grinding the wafer down to the channels. A second encapsulant is deposited over the die. A first interconnect structure is formed over a first surface of the second encapsulant. The first interconnect structure is electrically connected to the bumps. A second interconnect structure is formed over a second surface of the second encapsulant. Secondary semiconductor components can be stacked over the second interconnect structure. A third encapsulant is deposited over the stacked secondary components and second interconnect structure.

Abstract: A first area of a first surface of an encapsulated component can be thinned, the component including: a semiconductor chip having an active surface opposite the first surface, and an encapsulant extending outwardly from edges of the semiconductor chip. An entire area of the active surface may be aligned with the first area. After the abrading, a second area of the encapsulated component beyond the first area may have a thickness greater than a thickness of the first area. The second area can be configured to fully support the abraded encapsulated component in a state of the encapsulated component being manipulated by handling equipment.

Abstract: A method for manufacturing a semiconductor device includes providing a carrier and a semiconductor wafer having a first side and a second side opposite to the first side. The method includes applying a dielectric material to the carrier or the semiconductor wafer and bonding the semiconductor wafer to the carrier via the dielectric material. The method includes processing the semiconductor wafer and removing the carrier from the semiconductor wafer such that the dielectric material remains on the semiconductor wafer to provide a semiconductor device comprising the dielectric material.

Abstract: A surface of a power semiconductor chip, mounted within a power semiconductor module and not being opposed to a wiring thin film, and a surface of a bonding wire are sealed with a resin that does not contain a thermally-conductive filler, and the resin that does not contain a thermally-conductive filler is sealed with a resin that contains a thermally-conductive filler.

Abstract: A method includes aligning a top package to a bottom package using an alignment mark in the bottom package, and placing the top package over the bottom package, wherein the top package is aligned to the bottom package after the placing the top package over the bottom package. A reflow is then performed to bond the top package to the bottom package.

Abstract: Various embodiments provide a baseplate for an electronic module, wherein the baseplate comprises a conductive material; and a recess formed in one main surface of the baseplate and being adapted to accommodate an electronic chip.

Abstract: A preassembly semiconductor device comprises chip soldering structures on a semiconductor chip and substrate soldering structures on a substrate corresponding to the chip soldering structures. The substrate soldering structures extend toward the chip soldering structures for forming solder connections with the chip soldering structures. The chip and the substrate are in preassembly positions relative to one another. The height of the substrate soldering structures is greater than the height of the chip soldering structures. A pre-applied underfill is contiguous with the substrate and is sufficiently thick so as to extend substantially no further than the full height of the substrate soldering structures.

Abstract: A method of making a thermally curable solder-resistant ink, which comprises the following steps: polymerizing an aliphatic diamine monomer having a long carbon chain, an aromatic dianhydride monomer, an aromatic diamine monomer having a carboxylic acid group, and an anhydride monomer having a carboxylic acid group in an aprotic solvent to obtain a polyamine acid; cyclizing the polyamine acid to obtain a polyimide; and mixing the polyimide and a curing agent to obtain the thermally curable solder-resistant ink. By the steps mentioned above, the thermally curable solder-resistant ink made from the method has a dielectric constant less than 3.00 and a dielectric loss less than 0.01 and thereby is applicable to high frequency electronic equipments. Also, the thermally curable solder-resistant ink has good electrical properties, folding endurance, solder resistance, warpage resistance, flame resistance, acid endurance, alkali endurance, good solvent resistance and low water absorption.

Abstract: Systems and methods for preventing warpage of a semiconductor substrate in a semiconductor package. A continuous or uninterrupted stiffener structure is designed with a recessed groove, such that passive components, such as, high density capacitors are housed within the recessed groove. The stiffener structure with the recessed groove is attached to the semiconductor substrate using anisotropic conductive film (ACF) or anisotropic conductive paste (ACP). The stiffener structure with the recessed groove surrounds one or more semiconductor devices that may be formed on the semiconductor substrate. The stiffener structure with the recessed groove does not extend beyond horizontal boundaries of the semiconductor substrate.

Abstract: Embodiments include but are not limited to apparatuses and systems including microelectronic devices including a package substrate, a plurality of electronic components disposed on and electrically coupled with the package substrate at one or more sides of the package substrate, one or more hollow cavity sheet molds surrounding the plurality of electronic components and coupled with one or more sides of the package substrate, and a plurality of through-mold vias to couple the package substrate with an external surface of at least one of the one or more hollow cavity sheet molds. The microelectronic device may be a chip-scale package or module. Methods and systems for making the same also are described.

Abstract: Various embodiments of semiconductor assemblies with multi-level substrates and associated methods of manufacturing are described below. In one embodiment, a substrate for carrying a semiconductor die includes a first routing level, a second routing level, and a conductive via between the first and second routing levels. The conductive via has a first end proximate the first routing level and a second end proximate the second routing level. The first routing level includes a terminal and a first trace between the terminal and the first end of the conductive via. The second routing level includes a second trace between the second end of the conductive via and a ball site. The terminal of the first routing level and the ball site of the second routing level are both accessible for electrical connections from the same side of the substrate.