Abstract: A method for forming a capacitor of a semiconductor device includes forming a first capacitor in a storage node contact region to form a two-stage structured capacitor, thereby increasing the height and the capacitance of the capacitor.

Abstract: A device fabricated on a chip is disclosed. The device generally includes (A) a first pattern and a second pattern both created in an intermediate conductive layer of the chip, (B) at least one via created in an insulating layer above the intermediate conductive layer and (C) a first bump created in a top conductive layer above the insulating layer. The first pattern generally establishes a first of a plurality of plates of a first capacitor. The via may be aligned with the second pattern. The first bump may (i) be located directly above the first plate, (ii) establish a second of the plates of the first capacitor, (iii) be suitable for flip-chip bonding and (iv) connect to the second pattern through the via such that both of the plates of the first capacitor are accessible in the intermediate conductive layer.

Abstract: A chip-type solid electrolytic capacitor comprises capacitor elements. A cathode terminal comprising a plate-like conductor is interposed between cathode layers of the capacitor elements. The capacitor elements are bonded to each other by a bonding agent such as a solder or a conductive adhesive. The cathode terminal is provided with a through hole formed at a portion to be brought into contact with each of the capacitor elements. Bonding surfaces of the capacitor elements are directly connected at the through hole.

Abstract: A method for fabricating a semiconductor device includes forming a fuse line over a first region of a substrate, forming a first insulation layer over the fuse line and the substrate, forming a capacitor including an electrode over a second region of the substrate, such that a conductive layer for the electrode is patterned over the first insulation layer of the first region to overlap with the fuse line, forming a second insulation layer over the capacitor, etching the second insulation layer using the patterned conductive layer of the first region as an etch stop layer, and etching the patterned conductive layer and the first insulation layer to make a portion of the first insulation layer remain over the fuse line at a certain thickness.

Abstract: A glass substrate has a pair of main surfaces opposite to each other. Two island-shaped portions made of silicon are buried in the glass substrate. The tow island-shaped portions are exposed from the two main surfaces of the glass substrate, respectively. An electrode is formed on one main surface of the glass substrate so as to be electrically connected to one exposed portion of one island-shaped portion, and another electrode is formed thereon so as to be electrically connected to one exposed portion of the other island-shaped portion. Still another electrode is formed on the other main surface of the glass substrate so as to be electrically connected to the other exposed portion of the one island-shaped portion. A silicon substrate having a pressure sensing diaphragm is bonded to the other main surface of the glass substrate.

Abstract: A method of producing a polymer capacitor includes forming a first electrode on a surface of a first ion exchange resin solid and coating a mixture of an ion exchange resin solution and a salt on the other surface of the first resin; putting a second ion exchange resin solid which has a second electrode formed on a surface thereof on the coated layer and conducting lamination of the resulting structure to produce a composite; dissolving the salt to form pores; and filling the pores with an electrolytic solution.

Abstract: Methods for fabricating conductive structures on contact pads of semiconductor device components or other electronic components and for securing conductive structures to contact pads include directing consolidating energy toward unconsolidated conductive material. Alternatively, an unconsolidated material that will consolidate without additional consolidating energy may be used to form such conductive structures, in which case layers of the unconsolidated material are merely defined. Consolidating energy may be directed or layers of unconsolidated conductive material defined by recognizing the locations or orientations of one or more features, such as a contact, of the semiconductor device component or other electronic component. The conductive elements may include, but are not limited to, discrete conductive structures that protrude from the contacts, conductive traces that extend laterally from the contacts, or vias of circuit boards, interposers, or semiconductor devices.

Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.

Abstract: A storage capacitor plate for a semiconductor assembly comprising a substantially continuous porous conductive storage plate comprising silicon nanocrystals residing along a surface of a conductive material and along a surface of a coplanar insulative material adjacent the conductive material, a capacitor cell dielectric overlying the silicon nanocrystals and an overlying conductive top plate. The conductive storage plate is formed by a semiconductor fabrication method comprising forming silicon nanocrystals on a surface of a conductive material and on a surface of an insulative material adjacent the conductive material, wherein silicon nanocrystals contain conductive impurities and are adjoined to formed a substantially continuous porous conductive layer.

Abstract: One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM capacitor embedded isolation structure.

Abstract: It is an object of the present invention to provide a porous body containing an oxide semiconductor in which more efficient photocatalytic reactions and photoelectrode reactions occur. The present invention relates to a porous body having a network structure skeleton wherein 1) the aforementioned skeleton is composed of an inner part and a surface part, 2) the aforementioned inner part is substantially made of carbon material, and 3) all or part of the aforementioned surface part is an oxide semiconductor, and to a manufacturing method therefor.

Abstract: A method is provided to suppress detachment between semiconductor packages while preventing dislocation at the time of mounting a stacked semiconductor package on a motherboard. Semiconductor packages PK1 and PK2 are bonded to each other through protruding electrodes and resin is provided between the semiconductor packages PK1 and PK2. The resin is provided in the peripheries of the protruding electrodes so as to contact each of the protruding electrodes while not contacting a semiconductor chip.

Abstract: A method of manufacturing electric double layer capacitors is disclosed. The method assumes a model in which solute is dissolved in solvent before preparing electrolyte, and estimates a withstanding voltage through a simulation. The electrolyte, of which withstanding voltage is expected to exceed a target value, is selectively prepared. The method adjusts respective surface areas of the positive electrode and the negative electrode of the capacitor for making full use of the withstanding voltage of the electrolyte. According to this method, a time for developing electrolyte can be substantially shortened, and an electric double layer capacitor having a high withstanding voltage can be efficiently developed.

Abstract: Deposition of a metal-containing reagent solution or suspension onto a conductive substrate by various pad-printing techniques is described. The result in a pseudocapacitive oxide coating, nitride coating, carbon nitride coating, or carbide coating having an acceptable surface area for incorporation into an electrolytic capacitor, such as one have a tantalum anode.

Abstract: Semiconductor devices with copper interconnections and MIM capacitors and methods of fabricating the same are provided. The device includes a lower electrode composed of a first copper layer. A first insulation layer covers a lower electrode. A window is formed in the first insulation layer to expose a portion of the lower electrode. A capacitor includes a lower barrier electrode, a dielectric layer, and an upper barrier electrode, which are sequentially formed to cover a sidewall and a bottom of the window. An intermediate electrode composed of a second copper layer fills a remaining space of an inside of the capacitor. A second insulation layer is formed on the intermediate electrode. A connection hole is formed in the second insulation layer to expose a portion of the intermediate electrode. A connection contact plug composed of a third copper layer fills the connection hole.

Abstract: The present application discloses process comprising providing a wafer, the wafer comprising an inter-layer dielectric (ILD) having a feature therein, an under-layer deposited on the ILD, and a barrier layer deposited on the under-layer, and a conductive layer deposited in the feature, placing the wafer in an electrolyte, such that at least the barrier layer is immersed in the electrolyte, and applying an electrical potential between the electrode and the wafer.

Abstract: A metal/insulator/metal capacitor and a fabrication method thereof are presented. The method includes forming a first electrode on an insulation film; forming a side wall made of insulating material on a side surface of the first electrode; forming an interlayer insulation film on the top surface of the insulation film including the first electrode and the side wall; forming a via hole to expose the first electrode by selectively etching the interlayer insulation film such that an edge area at which a side surface and a bottom of the via hole intersect is positioned on a top surface of the side wall; forming a dielectric layer on an inner wall of the via hole; forming a second electrode on the dielectric layer such that the via hole is filled; and forming a metal wire on the second electrode such that the metal wire is electrically connected to the second electrode.

Abstract: A semiconductor device and method for fabricating same according to an embodiment of the invention includes: preparing a semiconductor substrate having a first contact pad and a second contact pad; forming a first insulating film on the substrate; etching the first insulating film to form a groove-shaped bit line pattern and a contact exposing the first contact pad and the second contact pad, respectively; simultaneously forming a contact plug and a bit line in the contact and the bit line pattern, respectively, the contact plug and the bitline having upper surfaces that are coplanar; and forming a bottom electrode for a capacitor that is connected to the first contact pad.

Abstract: A transistor having a gate electrode with a T-shaped cross section is fabricated from a single layer of conductive material using an etching process. A two process etch is performed to form side walls having a notched profile. The notches allow source and drain regions to be implanted in a substrate and thermally processed without creating excessive overlap capacitance with the gate electrode. The reduction of overlap capacitance increases the operating performance of the transistor, including drive current.

Abstract: A separator sheet for manufacturing an electric double layer capacitor, and a method for manufacturing the electric double layer capacitor using the same, are provided. According to an embodiment, the separator sheet for manufacturing the electric double layer capacitor comprises: a plurality of separators; and a resin film holding the plurality of separators, wherein the separators are disposed in the resin film at a predetermined interval.

Abstract: An integrated capacitor on a packaging substrate. The integrated capacitor comprises a conductor plane, a first dielectric layer and a signal transmission layer. The conductor plane has an extrusion layer of a first thickness. The first extrusion layer and the conductor plane are made of the same material. The first dielectric layer is formed on the conductor plane. The signal transmission layer is formed on the first dielectric layer.

Abstract: The present invention intends to provide a technique that can improve the capacitance density while securing the withstand voltage of a capacitor element. In order to achieve the above object, the present inventive manufacturing method of a semiconductor device includes forming a metal film on a silicon oxide film, forming a SiN film on the metal film, forming a metal film on the SiN film, etching the upper most metal film with a photoresist film as a mask to form an upper electrode, thereafter forming a silicon oxide film that covers the upper electrode, patterning by etching the silicon oxide film and the SiN film with a photoresist film as a mask to form a capacitor insulating film and sputter-etching the lowermost metal film with the patterned silicon oxide film as a mask to form a lower electrode.

Abstract: A process for forming portions of a compound material within an electronic circuit includes the formation of a cavity having at least one opening facing onto an access surface. The cavity furthermore has an internal wall with at least one region made of an initial material (for example, silicon). A metal is deposited close to the region of initial material. The circuit is then heated to form a portion of the compound material (for example, a silicide) in the region of initial material inside the cavity. The compound material is formed from elements of the initial material and from some of the metal deposited. The excess metal that has not formed some of the compound material is then removed from the cavity.

Abstract: Provided are a nitride-based light emitting device and a method of manufacturing the same. The nitride-based light emitting device has a structure in which at least an n-cladding layer, an active layer, and a p-cladding layer are sequentially formed on a substrate. The light emitting device further includes an ohmic contact layer composed of a zinc (Zn)-containing oxide containing a p-type dopant formed on the p-cladding layer. The method of manufacturing the nitride-based light emitting device includes forming an ohmic contact layer composed of Zn-containing oxide containing a p-type dopant on the p-cladding layer, the ohmic contact layer being made and annealing the resultant structure. The nitride-based light emitting device and manufacturing method provide excellent I–V characteristics by improving ohmic contact with a p-cladding layer while significantly enhancing light emission efficiency of the device due to high light transmittance of a transparent electrode.

Abstract: Methods of forming a capacitor of a semiconductor device can include forming a lower electrode of a capacitor on a semiconductor substrate and forming a dielectric material layer of Ba(Ti1-xSnx)O3 (BTS) or Ba(Ti1-xZrx)O3 (BTZ) on the lower electrode. An amorphous layer can be formed on the dielectric material layer. An upper electrode of the capacitor can be formed on the amorphous layer.

Abstract: A method for manufacturing a ferroelectric capacitor includes successively disposing a lower electrode, at least one intermediate electrode and an upper electrode over a base substrate, and providing ferroelectric films between the electrodes, respectively. In the step of forming the intermediate electrode, (a) a first metal film is formed by a sputter method over the ferroelectric film, and (b) a second metal film is formed by a vapor deposition method over the first metal film.

Abstract: A method of manufacturing an ultra-thin PZT pyrochlore film comprises providing a structure comprising a base layer, and forming on the base layer, a titanium layer and a PZT layer in mutual contact. The structure is annealed to form a PZT pyrochlore layer on said base layer. Novel devices with an ultra-thin PZT layer may thereby be manufactured.

Abstract: A method for integrating a metal-insulator-metal (MIM) capacitor in back end of line (BEOL) wiring levels of a semiconductor device includes forming an isolating layer over a lower wiring level, forming a bottom electrode of the capacitor on the isolating layer, and forming an interlevel dielectric material on the isolating layer and the bottom electrode. A capacitor dielectric is formed on the bottom electrode and a top electrode of the capacitor is formed on the capacitor dielectric, wherein the top electrode is formed concurrently with an upper wiring level, the upper level being the next successive wiring level with respect to the lower wiring level.

Abstract: A multilayer copper structure has been provided for improving the adhesion of copper to a diffusion barrier material, such as TiN, in an integrated circuit substrate. The multilayer copper structure comprises a thin high-resistive copper layer to provide improved adhesion to the underlying diffusion barrier layer, and a low-resistive copper layer to carry the electrical current with minimum electrical resistance. The invention also provides a method to form the multilayer copper structure.

Abstract: The present invention relates to a method for fabricating a capacitor of a semiconductor device.

Abstract: The disclosure provides a capacitor including a lower electrode, a surface of which can be formed of Pt, and an inner part of which can be formed of metal having good antioxidant properties. The inner part of the lower electrode can be formed by depositing Ru or Ir with an electro plating process. It is possible to improve the leakage current characteristics by forming the surface of the lower electrode with Pt. Also it is possible to perform a thermal treatment at a high temperature in an oxygen atmosphere, because the inner part of the lower electrode resists or prevents diffusion of oxygen, so that a high dielectric layer can be obtained.

Abstract: The present invention relates to a method of forming an electrode of an apparatus for manufacturing a liquid crystal display (LCD) device, wherein the electrode has a substantially flat surface. A method of forming an electrode of an apparatus for manufacturing a liquid crystal display device includes milling an aluminum plate, wherein the milling comprises roughing, rest roughing and finishing, polishing an upper surface of the aluminum plate by using fine ceramic powder, and anodizing the aluminum plate.