Abstract: A method for modulating the stress caused by bird beak formation of small width devices by a nitrogen plasma treatment. The nitrogen plasma process forms a nitride liner about the trench walls that serves to prevent the formation of bird beaks in the isolation region during a subsequent oxidation step. In one embodiment, the plasma nitridation process occurs after trench etching, but prior to trench fill. In yet another embodiment, the plasma nitridation process occurs after trench fill. In yet another embodiment, a block mask is formed over predetermined active areas of the etched substrate prior to the plasma nitridation process. This embodiment is used in protecting the PFET device area from the plasma nitridation process thereby providing a means to form a PFET device area in which stress caused by bird beak formation increases the device performance of the PFET.

Abstract: Disclosed is a structure and method for tuning silicide stress and, particularly, for developing a tensile silicide region on a gate conductor of an n-FET in order to optimize n-FET performance. More particularly, a first metal layer-protective cap layer-second metal layer stack is formed on an n-FET structure. However, prior to the deposition of the second metal layer, the protective layer is exposed to air. This air break step alters the adhesion between the protective cap layer and the second metal layer and thereby, effects the stress imparted upon the first metal layer during silicide formation. The result is a more tensile silicide that is optimal for n-FET performance.

Abstract: Disclosed is a method for manufacturing a semiconductor device having recess channels and asymmetrical junctions. The method includes forming an impurity region for adjusting the threshold voltage by implanting ions into a bit line junction of a semiconductor substrate, which includes storage nodes junction, the bit line junction, and channel regions between the source and bit line junctions, and portions of the channel regions of the semiconductor substrate adjacent to the bit line junction; forming recess channel trenches by etching the channel regions of the semiconductor substrate to a designated depth; forming a gate stack on the semiconductor substrate provided with the recess channel trenches; and forming the storage nodes junction and the bit line junction on the semiconductor substrate provided with the gate stack via ion implantation.

Abstract: It is an object of the present invention to improve the usability of a material, and to provide a display device which can be manufactured by simplifying the manufacturing process and a manufacturing technique thereof. It is also an object of the invention to provide a technique in which a pattern of a wiring or the like constituting these display devices can be formed to have a desired shape with favorable controllability. One feature of a droplet discharge device of the invention comprises: a discharge means for discharging a composition including a pattern forming material; and a shape means for shaping the shape of the composition before the composition is attached to a formation region, in which the shape means is provided between the discharge means and the formation region.

Abstract: A semiconductor device incorporating an alloy layer formed on a substrate; a gate electrode, a source electrode, and a drain electrode formed on the alloy layer at predetermined intervals therebetween; a gate insulating layer formed on the gate electrode in a gate electrode region; a first conductive layer formed on the substrate, including the source electrode and the drain electrode; and a second conductive layer and a metal silicide layer sequentially stacked on the first conductive layer and gate insulating layer.

Abstract: A method is provided for processing a substrate including providing a processing gas comprising an organosilicon compound comprising a phenyl group to the processing chamber, and reacting the processing gas to deposit a low k silicon carbide barrier layer useful as a barrier layer in damascene or dual damascene applications with low k dielectric materials.

Abstract: A method is disclosed for depositing silicon with high deposition rates and good step coverage. The process is performed at high pressures, including close to atmospheric pressures, at temperatures of greater than about 650° C. Silane and hydrogen are flowed over a substrate in a single-wafer chamber. Advantageously, the process maintains good step coverage and high deposition rates (e.g., greater that 50 nn/min) even when dopant gases are added to the process, resulting in commercially practicable rates of deposition for conductive silicon. Despite the high deposition rates, step coverage is sufficient to deposit polysilicon into extremely deep trenches and vias with aspect ratios as high as 40:1, filling such structures without forming voids or keyholes.

Abstract: A method for fabricating a transistor of a semiconductor device is provided. The method includes: forming device isolation layers in a substrate including a bottom structure, thereby defining an active region; etching the active region to a predetermined depth to form a plurality of recess structures each of which has a flat bottom portion with a critical dimension (CD) larger than that of a top portion; and sequentially forming a gate oxide layer and a metal layer on the recess structures; and patterning the gate oxide layer and the metal layer to form a plurality of gate structures.

Abstract: A method of forming a conductive line suitable for decreasing a sheet resistance of the conductive lines. The method comprises steps of providing a material layer having a conductive layer formed thereon and forming a patterned mask layer on the conductive layer. In addition, a portion of the conductive layer is removed by using the patterned mask layer as a mask and a spacer is formed on a sidewall of the patterned mask layer and the conductive layer. A portion of the conductive layer is removed until the material layer is exposed to form a conductive line, wherein the spacer and the patterned mask layer serve as a mask.

Abstract: In a method of forming a metal line and a method of manufacturing a display substrate, a channel layer and a metal layer are successively formed on a base substrate. A photoresist pattern is formed in a wiring area. The metal layer is etched by using the photoresist pattern to form a metal line. The photoresist pattern is removed by a predetermined thickness to form a residual photoresist pattern on the metal line. The channel layer is etched by using the metal line to form an undercut under the metal line. The protruding portion of the metal line is removed by using the residual photoresist pattern. The protruding portion relatively protrudes by formation of the undercut. Thus, an aperture ratio is increased, an afterimage is prevented, and the display quality is improved.

Abstract: Methods of forming metal lines in semiconductor devices are disclosed. One example method may include forming lower metal lines and forming an insulation layer on the lower metal lines; etching said insulation layer to a depth; and depositing a material for upper metal lines on the entire surface of said insulation layer and planarizing the material for the upper metal lines to form said upper metal lines. The example method may also include exposing the lower metal lines by etching said upper metal lines and the insulation layer and depositing a material for contact plugs on the entire surfaces of said upper metal lines and said insulation layer and planarizing the material for said contact plugs to form the contact plugs.

Abstract: In a method of manufacturing a semiconductor device, a first trench is formed in a first region of a substrate and a second trench is formed in a second region of the substrate different from the first region. A depth of the first trench is less than that of the second trench. An insulation layer is formed in the second trench, so that semiconductor structures in the first trench are electrically isolated, and a conductive layer fills the first trench and extends above the first trench.

Abstract: Disclosed in a method of forming a copper wiring in a semiconductor device. A copper layer buries a damascene pattern in which an interlayer insulating film of a low dielectric constant. The copper layer is polished by means of a chemical mechanical polishing process to form a copper wiring within a damascene pattern. At this time, the chemical mechanical polishing process is overly performed so that the top surface of the copper wiring is concaved and is lower than the surface of the interlayer insulating film of the low dielectric constant neighboring it. Furthermore, an annealing process is performed so that the top surface of the copper wiring is changed from the concaved shape to a convex shape while stabilizing the copper wiring. A copper anti-diffusion insulating film is then formed on the entire structure including the top surface of the copper wiring having the convex shape.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a silicided gate electrode (150) located over a substrate (110), the silicided gate electrode (150) having gate sidewall spacers (160) located on sidewalls thereof. The semiconductor device (100) further includes source/drain regions (170) located in the substrate (110) proximate the silicided gate electrode (150), and silicided source/drain regions (180) located in the source/drain regions (170) and at least partially under the gate sidewall spacers (160).

Abstract: The present invention relates to a method for cladding a simple or complex surface, electrically conducting or semiconducting, by means of an organic film from at least one precursor of said organic film, characterized in that the cladding of the surface by the organic film is carried out by electro-initiated grafting of said, at least one, precursor of said surface by applying at least one potential sweep on this surface carried out in such a way that at any point of said surface the maximum potential of each potential sweep, in absolute value and relative to a reference electrode, is greater than or equal to the value of the potential (vbloc) from which the curves of a graph expressing the quantity of electro-grafted precursor on a surface identical to said surface in function of the number of potential sweeps are all superposed and independent of this vbloc potential.

Abstract: On a substrate, the pattern of the first conductive layer is defined, that is, a gate line combination including gate pads, scanning lines and gate electrodes. A gate insulating layer, a semiconductor layer, a doped semiconductor layer and a second conductive layer are deposited on the substrate and the above-mentioned gate line combination in sequence. A photoresist layer is overlaid on the second conductive layer. The photoresist layer within the aperture areas is fully exposed. Using a half-tone mask or a slit pattern to make parts of the photoresist layer lying on the gate pads and the gate electrodes are not exposed to its full depth. As a result, the photoresist pattern formed varies in thickness. After being processed with drying etching and wet etching for several times, all the layers previously deposited within the aperture areas can be totally etched and removed.

Abstract: SiGe or SiC films are selectively grown on source/drain regions, followed by selectively growing silicon. A monocrystalline film having a high dislocation density or a polycrystalline film can be grown in growing the silicon film by making the C or Ge concentration higher than a predetermined level. The silicon layer on each of the source/drain regions is not monocrystalline or, even if monocrystalline, has a high density of dislocation. Therefore, the silicon film formed thereon is in the form of a monocrystalline silicon film having a high dislocation density or a polycrystalline silicon film. It is possible to suppress an impurity diffusion to reach a deep region caused by channeling of ions generated in the doping step by means of an ion implantation.