Abstract: In an embodiment, a device includes: an interconnect structure including a first contact pad, a second contact pad, and an alignment mark; a light emitting diode including a cathode and an anode, the cathode connected to the first contact pad; an encapsulant encapsulating the light emitting diode; a first conductive via extending through the encapsulant, the first conductive via including a first seed layer, the first seed layer contacting the second contact pad; a second conductive via extending through the encapsulant, the second conductive via including a second seed layer, the first seed layer and the second seed layer including a first metal; and a hardmask layer between the second seed layer and the alignment mark, the hardmask layer including a second metal, the second metal different from the first metal.

Abstract: In a method of cutting a fine pattern, a line structure is formed on a substrate. The line structure extends in a first direction, and includes a pattern and a first mask. The pattern and the first mask include different materials. A sacrificial layer is formed on the substrate to cover the line structure. The sacrificial layer is partially etched to form a first opening partially overlapping the line structure in a vertical direction. A portion of the first mask, an upper portion of the pattern and/or a portion of the sacrificial layer under the first opening are partially etched using an etching gas having no etching selectivity among the pattern, the first mask and the sacrificial layer. A lower portion of the pattern under the upper portion thereof is removed to divide the pattern into a plurality of pieces spaced apart from each other in the first direction.

Abstract: Provided is a semiconductor device including: a drift region of first conductivity type provided in a semiconductor substrate; a base region of second conductivity type provided in the semiconductor substrate; an emitter region of first conductivity type provided at a front surface of the semiconductor substrate; a contact region of second conductivity type provided on the base region and having a higher doping concentration than the base region; a contact trench portion provided at the front surface of the semiconductor substrate; a first barrier layer provided at a side wall and a bottom surface of the contact trench portion; and a second barrier layer provided in contact with the contact region at the side wall of the contact trench portion.

Abstract: A semiconductor device includes a first insulating layer disposed on a substrate, a first wiring disposed in the first insulating layer, a first insulating barrier layer disposed on the first insulating layer, an etch-stop layer disposed on the first insulating barrier layer and having an area smaller than an area of the first insulating barrier layer in a plan view, a resistive metal pattern disposed on the etch-stop layer, a second insulating barrier layer disposed on the resistive metal pattern, a second insulating layer covering the first and second insulating barrier layers, a second wiring disposed in the second insulating layer, and a first conductive via disposed between the resistive metal pattern and the second wiring to penetrate through the second insulating barrier layer and the second insulating layer and electrically connect the resistive metal pattern and the second wiring.

Abstract: A multi-layer thin film composite is formed by applying a thin film formed from non-single-crystalline oxide onto a substrate; applying a protection film onto the thin film; and supplying energy to the thin film through at least one of the protection film or the substrate.

Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for enhancing wafer bonding includes positioning a substrate assembly on a unipolar electrostatic chuck in direct contact with an electrode, electrically coupling a conductor to a second substrate positioned on top of the first substrate, and applying a voltage to the electrode, thereby creating a potential differential between the first substrate and the second substrate that generates an electrostatic force between the first and second substrates.

Abstract: The present disclosure provides many different embodiments of an IC device. The IC device includes a gate stack disposed over a surface of a substrate and a spacer disposed along a sidewall of the gate stack. The spacer has a tapered edge that faces the surface of the substrate while tapering toward the gate stack. Therefore the tapered edge has an angle with respect to the surface of the substrate.

Abstract: A method for producing a via in a wafer includes providing a wafer, comprising silicon. The method includes producing a conductive region, in the form of a conductor track, preferably composed of polycrystalline silicon, in the wafer. The method includes producing a hole in the wafer such that the hole is fluidically connected to the conductive region and the sidewalls of the hole comprise silicon. The method includes applying a tungsten hexafluoride-resistant protective layer, produced from silicon oxide, in the region of the surface of the hole that is to be produced or has been produced, such that an opening of the hole is free of a protective layer. The method includes applying tungsten hexafluoride to the hole and the region of the opening of the hole by a reducing-agent-free vapor phase deposition process, preferably in the form of a CVD process, for producing the via.

Abstract: The process for growing at least one semiconductor nanowire (3), said growth process comprising a step of forming, on a substrate (1), a nucleation layer (2) for the growth of the nanowire (3) and a step of growth of the nanowire (3). The step of formation of the nucleation layer (2) comprises the following steps: deposition onto the substrate (1) of a layer of a transition metal (4) chosen from Ti, V, Cr, Zr, Nb, Mo, Hf, Ta; nitridation of at least a part (2) of the transition metal layer so as to form a transition metal nitride layer having a surface intended for growing the nanowire (3).

Abstract: The present disclosure provides a manufacturing method for the semiconductor structure, including forming a bottom metal layer including copper, forming a planar memory layer over the bottom metal layer, forming an electrode over the planar memory layer by a self-aligning operation, and defining a memory cell by patterning the planar memory layer.

Abstract: A semiconductor device includes a substrate having an upper surface layer of a second conduction type formed at an upper surface side, a drift layer of a first conduction type formed under the upper surface layer, a buffer layer of the first conduction type formed under the drift layer, and a lower surface layer of the second conduction type formed under the buffer layer, the buffer layer includes a plurality of upper buffer layers provided apart from each other, and a plurality of lower buffer layers provided apart from each other between the plurality of upper buffer layers and the lower surface layer, wherein the plurality of upper buffer layers are formed so that average impurity concentrations in first sections each extending from the upper end of one of the upper buffer layers to the next lower buffer layer are unified as a first concentration.

Abstract: In one embodiment, an IGBT is formed to include a region of semiconductor material. Insulated gate structures are disposed in region of semiconductor material extending from a first major surface. An n-type field stop region extends from a second major surface into the region of semiconductor material. A p+ type polycrystalline semiconductor layer is disposed adjacent to the field stop region and provides an emitter region for the IGBT. An embodiment may include a portion of the p+ type polycrystalline semiconductor being doped n-type.

Abstract: A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy.

Abstract: Device and methods for forming a device are presented. The method includes providing a substrate. The substrate includes a resistor region defined by a resistor isolation region. A resistor gate is formed on the resistor isolation region. An implant mask with an opening exposing the resistor region is formed. Resistor well dopants are implanted to form a resistor well in the substrate. The resistor well is disposed in the substrate below the resistor isolation region. Resistor dopants are implanted into the resistor gate to define the sheet resistance of the resistor gate. Terminal dopants are implanted to form first and second resistor terminals at sides of the resistor gate. A central portion of the resistor gate sandwiched by the resistor terminals serves as a resistive portion.

Abstract: A method of sealing a first wafer and a second wafer each made of semiconducting materials, including: implanting a metallic species in at least the first wafer, assembling the first wafer and the second wafer by molecular bonding, and after the molecular bonding, forming a metallic ohmic contact including alloys formed between the implanted metallic species and the semiconducting materials of the first wafer and the second wafer, the metallic ohmic contact being formed at an assembly interface between the first wafer and the second wafer, wherein the forming includes causing the implanted metallic species to diffuse towards the interface between the first wafer with the second wafer and beyond the interface.

Abstract: A solar cell, comprising: a doped silicon substrate, the silicon substrate comprising a front surface and a rear surface; a front phosphorous diffusion layer formed on the front surface; a front anti-reflective layer formed on the front phosphorous diffusion layer; a front metal electrode on the front surface in ohmic contact with the front phosphorous diffusion layer through the front anti-reflective layer; a rear passivation layer formed on the rear surface; a rear metal electrode in a pattern on the rear surface passing through the rear passivation layer; and a rear p+ diffusion area on the rear surface between the rear passivation layer and a boron-doped region of the silicon substrate, the rear p+ diffusion area surrounding the rear metal electrode.

Abstract: In accordance with one or more embodiments, a semiconductor structure includes a semiconductor substrate, a first semiconductor material over the semiconductor substrate, and a second semiconductor material over a portion the first semiconductor material, wherein the second semiconductor material comprises silicon-germanium-carbon (SiGeC) and wherein the first semiconductor material is a silicon epitaxial layer. The semiconductor structure further includes an active device, wherein a portion of the active device is formed in the second semiconductor material and a dielectric structure extending from the first surface of the first semiconductor material into the semiconductor substrate through the first semiconductor material.

Abstract: A semiconductor device including polysilicon (poly-Si) and method of manufacturing the same are provided. The semiconductor device includes a TaNx material layer and a poly-Si layer formed on the TaNx material layer. The semiconductor device including poly-Si may be manufactured by forming a TaNx material layer and forming a poly-Si layer by depositing silicon formed on the TaNx material layer and annealing silicon.

Abstract: A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating film, which may be a refractive metal nitride film, is formed on the at least one PFET by a blanket deposition and patterning. An encapsulating dielectric film is deposited over the compress stress generating film. The stress is transferred from both the tensile stress generating film and the compressive stress generating film into the underlying semiconductor structures. The magnitude of the transferred compressive stress from the refractory metal nitride film may be from about 5 GPa to about 20 GPa. The stress is memorized during an anneal and remains in the semiconductor devices after the stress generating films are removed.

Abstract: Provided is a semiconductor element including: a semiconductor having an active layer; a gate insulating film which is in contact with the semiconductor, a gate electrode opposite to the active layer through the gate insulating film; a first nitride insulating film formed over the active layer; a photosensitive organic resin film formed on the first nitride insulating film; a second nitride insulating film formed on the photosensitive organic resin film; and a wiring provided on the second nitride insulating film, in which a first opening portion is provided in the photosensitive organic resin film, an inner wall surface of the first opening portion is covered with the second nitride insulating film, a second opening portion is provided in a laminate including the gate insulating film, the first nitride insulating film, and the second nitride insulating film inside the first opening portion, and the semiconductor is connected with the wiring through the first opening portion and the second opening portion.

Abstract: An etchant, a method for fabricating a multi-layered interconnection line using the etchant, and a method for fabricating a thin film transistor (TFT) substrate using the etchant. The etchant for the multi-layered line comprised of molybdenum/copper/molybdenum nitride illustratively includes 10-20 wt % hydrogen peroxide, 1-5 wt % organic acid, a 0.1-1 wt % triazole-based compound, a 0.01-0.5 wt % fluoride compound, and deionized water as the remainder.

Abstract: Spaced apart bonding surfaces are formed on a first substrate. A second substrate is bonded to the bonding surfaces of the first substrate and cleaved to leave respective semiconductor regions from the second substrate on respective ones of the spaced apart bonding surfaces of the first substrate. The bonding surfaces may include surfaces of at least one insulating region on the first substrate, and at least one active device may be formed in and/or on at least one of the semiconductor regions. A device isolation region may be formed adjacent the at least one of the semiconductor regions.

Abstract: A method of forming a wiring for a semiconductor memory device includes obtaining a semiconductor substrate, depositing at least one conductive layer on the semiconductor substrate under controlled conditions, such as substrate temperature and atmosphere temperature, to provide a conductive layer exhibiting a reduced surface roughness as compared to a comparable conductive layer deposited under uncontrolled conditions, and patterning the conductive layer to form a wiring.

Abstract: The present invention discloses a method for forming germanides on substrates with exposed germanium and exposed dielectric(s) topography, thereby allowing for variations in the germanide forming process. The method comprises the steps of depositing nickel on a substrate having topography, performing a first thermal step to convert substantially all deposited nickel in regions away from the topography into a germanide, selectively removing the unreacted nickel, and performing a second thermal step to lower the resistance of formed germanide.

Abstract: The invention concerns a method for depositing a layer consisting of a doped semiconductor material on a substrate, as well as a device for implementing said method. According to said method, the doped semiconductor material contains at least one semiconductor matrix material and at least one doping material. Said method consists in vaporizing a mixture of the semiconductor material(s) and of the doping material(s) using a vaporizing source, then in depositing said mixture on the substrate.

Abstract: A method of manufacturing a semiconductor device comprises the steps of forming a first insulating film 9, 10 above a semiconductor substrate 1; forming a capacitor Q having a lower electrode 11a, a dielectric film 13a, and an upper electrode 14c on the first insulating film 9, 10; forming a second insulating film 15, 15a, 16 coating the capacitor Q; and forming a stress-controlling insulating film 30 on the rear surface of the semiconductor substrate 1 after the second insulating film 15, 15a, 16 have been formed.