Abstract: Methods of processing a substrate are provided herein. In some embodiments, a method of processing a substrate may include providing a substrate to a process chamber comprising a dielectric layer having a feature formed therein. A barrier layer may be formed within the feature. A coating of a first conductive material may be formed atop the barrier layer. A seed layer of the first conductive material may be formed atop the coating. The feature may be filled with a second conductive material. In some embodiments, the seed layer may be formed while maintaining the substrate at a temperature of greater than about 40 degrees Celsius.

Abstract: Recessed features on a Damascene substrate are filled with metal using plasma PVD. Recessed features having widths of less than about 300 nm, e.g., between about 30-300 nm can be filled with metals (e.g., copper and aluminum), without forming voids. In one approach, the deposition is performed by exposing the substrate to a high-density plasma characterized by high fractional ionization of metal. Under these conditions, the metal is deposited within the recess, without forming large overhang at the opening of the recess. In some embodiments, the metal is deposited within the recess, while diffusion barrier material is simultaneously etched from the field region. In a second approach, recessed features are filled by performing a plurality of profiling cycles, wherein each cycle includes a net etching and a net depositing operation. Etching and depositing parameters are adjusted such that the recessed features are filled without forming overhangs and voids.

Abstract: Disclosed are embodiments of an improved high aspect ratio electroplated metal structure (e.g., a copper or copper alloy interconnect, such as a back end of the line (BEOL) or middle of the line (MOL) contact) in which the electroplated metal fill material is free from seams and/or voids. Also, disclosed are embodiments of a method of forming such an electroplated metal structure by lining a high aspect ratio opening (e.g., a high aspect ratio via or trench) with a metal-plating seed layer and, then, forming a protective layer over the portion of the metal-plating seed layer adjacent to the opening sidewalls so that subsequent electroplating occurs only from the bottom surface of the opening up.

Abstract: Herein disclosed an electronic component having a passivation layer in which an opening that exposes a part of a pad electrode is formed, an underlying metal layer formed on the pad electrode and the passivation layer, and a barrier metal layer formed on the underlying metal layer for an external connection electrode, the electronic component including a recess or/and a projection configured to be provided under the barrier metal layer outside or/and inside the opening, the underlying metal layer being formed on the recess or/and the projection and having a surface shape that follows the recess or/and the projection.

Abstract: A solder bump confinement system is provided including providing a substrate, patterning a contact material on the substrate, depositing an inner passivation layer over the contact material and the substrate, forming an under bump material defining layer over the contact material by sputtering, and forming a system interconnect over the contact material and on the under bump material defining layer.

Abstract: An iPVD system is programmed to deposit uniform material, such as a metallic material, into high aspect ratio nano-sized features on semiconductor substrates using a process that enhances the feature filling compared to the field deposition, while maximizing the size of the grain features in the deposited material opening at the top of the feature during the process. Sequential deposition and etching are provided by controlling DC and high density power levels and other parameters.

Abstract: An iPVD system uses a high density inductively coupled plasma (ICP) at high pressure of at least 50 mTorr to deposit uniform ultra-thin layer of a tantalum nitride material barrier material onto the sidewalls of high aspect ratio nano-size features on semiconductor substrates, preferably less than 2 nm thick with less than 4 nm in the field areas. The process includes depositing an ultra-thin TaN barrier layer having a high nitrogen concentration that produces high resistivity, preferably at least 1000 micro-ohm-cm. The ultra-thin TaN film is deposited by a low deposition rate process of less than 20 nm/minute, preferably 2-10 nm/min, to produce the high N/Ta ratio layer without nitriding the tantalum target. The layer provides a barrier to copper (Cu) diffusion and a high etch resistant etch-stop layer for subsequent deposition-etch processes.

Abstract: Provided is an organic thin film transistor that can prevents damage to source and drain electrodes when patterning an organic semiconductor layer, and a method of manufacturing an organic light emitting display device having the organic thin film transistor. The organic thin film transistor includes a source electrode and a drain electrode; an organic semiconductor layer that contacts the source and drain electrodes, and has an ashed surface except a channel area between the source and drain electrodes; a gate electrode insulated from the source electrode, the drain electrode, and the organic semiconductor layer; and a gate insulating film that insulates the gate electrode from the source electrode, the drain electrode, and the organic semiconductor layer.

Abstract: A method of forming a semiconductor device that includes heating a wafer on which an Al—Cu sputtering thin film is formed before patterning the Al—Cu sputtering thin film. The heating is performed at a temperature no less than a solid solution temperature of copper or at a temperature between 300° C. and 600° C. The process temperature in heating the process wafer is not higher than the flow temperature of aluminum or is the temperature at which a reflow process can be performed.

Abstract: Metal seed layers are deposited on a semiconductor substrate having recessed features by a method that involves at least three operations. In this method, a first layer of metal is deposited onto the substrate to cover at least the bottom portions of the recessed features. The first layer of metal is subsequently redistributed to improve sidewall coverage of the recessed features. Next, a second layer of metal is deposited on at least the field region of the substrate and on the bottom portions of the recessed features. The method can be implemented using a PVD apparatus that allows deposition and resputtering operations. This sequence of operations can afford seed layers with improved step coverage. It also leads to decreased formation of voids in interconnects, and to improved resistance characteristics of formed IC devices.

Abstract: Interconnect structures including liner layers that are non-planar with at least the adjacent insulating layer and at least one capping layer on conductive features embedded in the insulating layer. The interconnect structure includes an insulating layer of a dielectric material having a top surface and a bottom surface between the top surface and a substrate. An opening, such as a trench, has sidewalls extending from the top surface of the insulating layer toward the bottom surface and is at least partially filled by a conductive feature. A capping layer is disposed on at least a top surface of the conductive feature. A conductive liner layer is disposed between the insulating layer and the conductive feature along at least the sidewalls of the opening. The conductive liner layer has sidewall portions projecting above the top surface of the insulating layer adjacent to the sidewalls of the opening.

Abstract: A method and resultant produce of forming barrier layer based on ruthenium tantalum in a via or other vertical interconnect structure through a dielectric layer in a multi-level metallization. The RuTa layer in a RuTa/RuTaN bilayer, which may form discontinuous islands, is actively oxidized, preferably in an oxygen plasma, to thereby bridge the gaps between the islands. Alternatively, ruthenium tantalum oxide is reactive sputtered onto the RuTaN or directly onto the underlying dielectric by plasma sputtering a RuTa target in the presence of oxygen.

Abstract: A method for forming barrier layers comprises steps of providing a conductive layer, forming a first dielectric layer on the conductive layer, the first dielectric layer having a via therein, forming a first metal layer covering the first dielectric layer and the conductive layer, forming a layer of metallized materials on the first metal layer, removing the layer of metallized materials above the via bottom in the first dielectric layer, and leaving the layer of metallized materials remaining on a sidewall of the via in the first dielectric layer; and forming a second metal layer covering the layer of metallized materials. The accomplished barrier layers will have lower resistivity in the bottom via of the first dielectric layer and they are capable of preventing copper atoms from diffusing into the dielectric layer.

Abstract: Methods of depositing thin seed layers that improve continuity of the seed layer as well as adhesion to the barrier layer are provided. According to various embodiments, the methods involve performing an etchback operation in the seed deposition chamber prior to depositing the seed layer. The etch step removes barrier layer overhang and/or oxide that has formed on the barrier layer. It some embodiments, a small deposition flux of seed atoms accompanies the sputter etch flux of argon ions, embedding metal atoms into the barrier layer. The embedded metal atoms create nucleation sites for subsequent seed layer deposition, thereby promoting continuous seed layer film growth, film stability and improved seed layer-barrier layer adhesion.

Abstract: Embodiments as described herein provide a method for depositing barrier layers and tungsten materials on substrates. In one embodiment, a method for depositing materials is provided which includes forming a barrier layer on a substrate, wherein the barrier layer contains a cobalt silicide layer and a metallic cobalt layer, exposing the barrier layer to a soak gas containing a reducing gas during a soak process, and forming a tungsten material over the barrier layer. In one example, the barrier layer may be formed by depositing a cobalt-containing material on a dielectric surface of the substrate and annealing the substrate to form the cobalt silicide layer from a lower portion of the cobalt-containing material and the metallic cobalt layer from an upper portion of the cobalt-containing material.

Abstract: A magnetron sputter reactor for sputtering deposition materials such as tantalum, tantalum nitride and copper, for example, and its method of use, in which self-ionized plasma (SIP) sputtering and inductively coupled plasma (ICP) sputtering are promoted, either together or alternately, in the same or different chambers. Also, bottom coverage may be thinned or eliminated by ICP resputtering in one chamber and SIP in another. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. ICP is provided by one or more RF coils which inductively couple RF energy into a plasma. The combined SIP-ICP layers can act as a liner or barrier or seed or nucleation layer for hole. In addition, an RF coil may be sputtered to provide protective material during ICP resputtering. In another chamber an array of auxiliary magnets positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target.

Abstract: Embodiments of the invention generally provide methods for depositing and compositions of tantalum carbide nitride materials. The methods include deposition processes that form predetermined compositions of the tantalum carbide nitride material by controlling the deposition temperature and the flow rate of a nitrogen-containing gas during a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD. In one embodiment, a method for forming a tantalum-containing material on a substrate is provided which includes heating the substrate to a temperature within a process chamber, and exposing the substrate to a nitrogen-containing gas and a process gas containing a tantalum precursor gas while depositing a tantalum carbide nitride material on the substrate.

Abstract: A method of forming barrier layers in a via hole extending through an inter-level dielectric layer and including a preformed first barrier coated onto the bottom and sidewalls of the via holes. In a single plasma sputter reactor, a first step sputters the wafer rather than the target with high energy ions to remove the barrier layer from the bottom of the via but not from the sidewalls and a second step sputter deposits a second barrier layer, for example of Ta/TaN, onto the via bottom and sidewalls. The two steps may be differentiated by power applied to the target, by chamber pressure, or by wafer bias. The second step may include the simultaneous removal of the first barrier layer from the via bottom and sputter deposition of the second barrier layer onto the via sidewalls.

Abstract: A liquid crystal display panel manufacturing method includes forming at least one thin film on a flexible plastic substrate by sputtering at a temperature of about 80° C. to about 150° C. Sputtering can be in a chamber evacuated to about 1×10?6 Torr to about 9×10?6 Torr. Sputtering targets and films sputtered on substrates include materials that are conductive or insulating, organic or inorganic, metal or metal alloy, reflective metal or transparent conductive, or combinations thereof. Thin film and pattern formation employ photolithography with laminated or liquid films. Films may be sputtered on opposing sides of a substrate and may be multilayered.

Abstract: A salicide process contains providing a silicon substrate that comprises at least a predetermined salicide region, performing a cluster ion implantation process to form an amorphized layer in the predetermined salicide region of the silicon substrate near, forming a metal layer on the surface of the amorphized layer, and reacting the metal layer with the amorphized layer to form a silicide layer on the surface of the silicon substrate.

Abstract: A method of depositing a duffusion barrier layer with overlying conductive layer or fill which lowers resistivity of a semiconductor device interconnect. The lower resistivity is achieved by inducing the formation of alpha tantalum within a tantalum-comprising barrier layer.

Abstract: A method of forming a semiconductor device that includes heating a wafer on which an Al—Cu sputtering thin film is formed before patterning the Al—Cu sputtering thin film. The heating is performed at a temperature no less than a solid solution temperature of copper or at a temperature between 300° C. and 600° C. The process temperature in heating the process wafer is not higher than the flow temperature of aluminum or is the temperature at which a reflow process can be performed.

Abstract: The invention includes an electrically conductive line, methods of forming electrically conductive lines, and methods of reducing titanium silicide agglomeration in the fabrication of titanium silicide over polysilicon transistor gate lines. In one implementation, a method of forming an electrically conductive line includes providing a silicon-comprising layer over a substrate. An electrically conductive layer is formed over the silicon-comprising layer. An MSixNy-comprising layer is formed over the electrically conductive layer, where “x” is from 0 to 3.0, “y” is from 0.5 to 10, and “M” is at least one of Ta, Hf, Mo, and W. An MSiz-comprising layer is formed over the MSixNy-comprising layer, where “z” is from 1 to 3.0. A TiSia-comprising layer is formed over the MSiz-comprising layer, where “a” is from 1 to 3.0.

Abstract: A semiconductor device includes a first semiconductor chip having first pads arranged at first interval, a second semiconductor chip having second pads arranged at second interval, the second interval being larger than the first interval and a relay substrate arranged between the first semiconductor chip and the second semiconductor chip, the relay substrate having first relay pads and second relay pads, the first relay pads arranged at first interval being formed along a side facing the first semiconductor chip and the second relay pads arranged at second interval being formed along a side facing the second semiconductor chip, in which the first semiconductor chip and the second semiconductor chip are connected to each other through the relay substrate.

Abstract: A biased pulse DC reactor for sputtering of oxide films is presented. The biased pulse DC reactor couples pulsed DC at a particular frequency to the target through a filter which filters out the effects of a bias power applied to the substrate, protecting the pulsed DC power supply. Films deposited utilizing the reactor have controllable material properties such as the index of refraction. Optical components such as waveguide amplifiers and multiplexers can be fabricated using processes performed on a reactor according to the present inention.

Abstract: The present invention relates to a method for fabricating a metal interconnection line with use of a barrier metal layer formed in a low temperature. The method includes the steps of: forming an inter-layer insulation layer on a substrate; etching predetermined regions of the inter-layer insulation layer to form a plurality of contact openings; forming an ohmic metal layer on the contact openings and the etched inter-layer insulation layer; forming a seed layer on the ohmic metal layer; forming a metal layer on the seed layer and nitriding the metal layer in a repeated number of times to form a barrier metal layer; and forming a metal interconnection line on the barrier metal layer by burying the contact openings.

Abstract: The present invention provides a method for forming an interconnect on a semiconductor substrate 100. The method includes forming an opening 230 over an inner surface of the opening 130, the depositing forming a reentrant profile near a top portion of the opening 130. A portion of barrier 230 is etched, which removes at least a portion of the barrier 230 to reduce the reentrant profile. The etching also removes at least a portion of the barrier 230 layer at the bottom of the opening 130.

Abstract: A barrier layer is formed in an integrated circuit by providing a metal target near a ceiling of the chamber and a wafer support pedestal facing the target near a floor of the chamber. A process gas is introduced into the vacuum chamber. A target-sputtering plasma is maintained at the target to produce a stream of principally neutral atoms flowing from the target toward the wafer for vapor deposition. A wafer-sputtering plasma is maintained near the wafer support pedestal to produce a stream of sputtering ions toward the wafer support pedestal for re-sputtering. The sputtering ions are accelerated across a plasma sheath at the wafer in a direction normal to a surface of the wafer to render the sputter etching highly selective for horizontal surfaces.

Abstract: A method and mesh reference applications are provided for implementing Z-axis cross-talk reduction. A mesh reference plane including a grid of mesh traces is formed with the mesh traces having selected thickness and width dimensions effective for reference current-flow distribution. An electrically conductive coating is deposited to fill the mesh electrical holes in the mesh reference plane to reduce cross-talk, substantially without affecting mechanical flexibility.

Abstract: In forming a thin conductive layer in an interconnect structure by sputter deposition including a re-sputtering step, a flash deposition step is performed after the re-sputtering step to provide a sufficient layer thickness at critical locations, such as at positions of structure irregularities. The flash deposition step may be performed for a fixed process time so that less effort in process control is required while, at the same time, an increased reliability may be obtained compared to conventional approaches without a flash deposition.