Final Conductor Layer Next To Insulator Being Silicon E.g., Polysilicon, With Or Without Impurities (epo) Patents (Class 257/E21.197)
  • Patent number: 10840382
    Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a tunneling oxide layer, a floating gate, a dielectric layer, and a control gate. The tunneling oxide layer is formed on a substrate. The floating gate is formed on the tunneling oxide layer, and includes a first polysilicon layer, a second polysilicon layer, and a nitrogen dopant. A grain of the first polysilicon layer has a first grain size, and a grain of the second polysilicon layer has a second grain size that is greater than the first grain size. The nitrogen dopant is formed in interstices between the grains of the first polysilicon layer. The dielectric layer includes a first nitride film, an oxide layer, a nitride layer, and an oxide layer conformally formed on the floating gate. The control gate is formed on the dielectric layer.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: November 17, 2020
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Chu-Chun Hsieh, Tse-Mian Kuo
  • Patent number: 10586709
    Abstract: Methods for fabricating a semiconductor device are provided including sequentially forming a first hard mask layer, a second hard mask layer and a photoresist layer on a target layer, patterning the photoresist layer to form a photoresist pattern, sequentially patterning the second hard mask layer and the first hard mask layer using the photoresist pattern as an etching mask to form a first hard mask pattern and a second hard mask pattern on the first hard mask pattern, and etching the target layer using the first hard mask pattern and the second hard mask pattern as an etching mask, wherein the second hard mask layer includes impurity-doped amorphous silicon.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: March 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Min Ko, Hyuk Woo Kwon, Jun-Won Lee
  • Patent number: 10553476
    Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a first polysilicon structure over the substrate. The first polysilicon structure has a first grain size. The semiconductor device further includes a first barrier layer over the first polysilicon structure. At least one grain boundary of the first polysilicon structure contacts the first barrier layer. The semiconductor device further includes a second polysilicon structure over the first barrier layer. The second polysilicon layer has a second grain size smaller than the first grain size.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: J. J. Lee, Chun-Tse Tsai, M. C. Hang
  • Patent number: 10096453
    Abstract: A plasma etching apparatus includes an etching chamber and at least one processor. The etching chamber is configured to support a target therein. The at least one processor is configured to: determine a process condition for plasma etching the target before execution of a plasma etching process; and control an aspect of the chamber according to the process condition. The process condition includes a unit etching time over which the plasma etching process is to be continuously performed.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: October 9, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kijong Park, Jun-Youl Yang, Yongsun Ko, Kyunghyun Kim, Taeheon Kim, Jae Jin Shin
  • Patent number: 9824915
    Abstract: The invention relates to a structure for radiofrequency applications comprising: a monocrystalline substrate, a polycrystalline silicon layer directly on the monocrystalline substrate, and an active layer on the polycrystalline silicon layer intended to receive radiofrequency components. At least a first portion of the polycrystalline silicon layer extending from an interface of the polycrystalline silicon layer with the monocrystalline substrate layer includes carbon and/or nitrogen atoms located at the grain boundaries of the polycrystalline silicon layer at a concentration of between 2% and 20%. A process for manufacturing such a structure includes, during deposition of at least a first portion of such a polycrystalline silicon layer located at the interface with the monocrystalline substrate, depositing carbon and/or atoms in the at least a first portion.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: November 21, 2017
    Assignees: Soitec, Peregrine Semiconductor Corporation
    Inventors: Bich-Yen Nguyen, Christophe Maleville, Sinan Goktepeli, Anthony Mark Miscione, Alain Duvallet
  • Patent number: 9608089
    Abstract: Provided is a method of manufacturing a thin-film transistor substrate, the method includes forming a semiconductor pattern layer on a substrate. A first insulating film is formed on the semiconductor pattern layer. A metal pattern layer including a gate electrode and first and second alignment electrodes respectively spaced apart from two sides of the gate electrode is formed on the first insulating film. A cover layer covering the gate electrode is formed. The first and second alignment electrodes are removed. A first doping process is performed by doping the semiconductor pattern layer with a first impurity by using the cover layer as a mask. The cover layer is removed. A second doping process is performed by doping the semiconductor pattern layer with a second impurity having a lower impurity concentration than the first impurity by using the gate electrode as a mask.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: March 28, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jongyun Kim, Waljun Kim, Junghyun Kim, Kiwan Ahn
  • Patent number: 9583608
    Abstract: A nitride semiconductor device of the present invention has a source-electrode-side insulator protection film layer disposed between a source electrode and a drain electrode on a second nitride semiconductor layer and formed at least partially covering the source electrode, a drain-electrode-side insulator protection film layer disposed separately from the source-electrode-side insulator protection film layer and formed at least partially covering the drain electrode, and a gate layer formed in contact with the second nitride semiconductor layer between the source-electrode-side insulator protection film layer and the drain-electrode-side insulator protection film layer and made of a p-type metal oxide semiconductor, and the gate layer has regions opposite to the second nitride semiconductor layer across each of the source-electrode-side insulator protection film layer and the drain-electrode-side insulator protection film layer and a region in contact with the second nitride semiconductor layer.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: February 28, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yasuhiro Yamada, Yoshiharu Anda, Asamira Suzuki
  • Patent number: 9553159
    Abstract: A semiconductor device including a gate insulation pattern on a substrate, and a semiconductor gate pattern including an amorphous silicon pattern and a polycrystalline silicon pattern stacked on a side of the gate insulation pattern opposite to the substrate. The amorphous silicon pattern includes anti-diffusion impurities that suppress diffusion of impurity ions in the semiconductor gate pattern.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: January 24, 2017
    Assignee: SK HYNIX INC.
    Inventors: Kyong Bong Rouh, Yong Seok Eun, Young Jin Son
  • Patent number: 8921888
    Abstract: A method for fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, and a first region, a second region and a third region are defined thereon. Then, a first well having a first conductive type is formed in the semiconductor substrate of the first region and the second region, respectively. A semiconductor layer partially overlapping the first well of the second region is formed. Furthermore, a second well having a second conductive type is formed in the semiconductor substrate of the third region and the first well of the second region respectively, where the second well of the second region is disposed underneath the semiconductor layer.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: December 30, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Yuan-Hsiang Chang, Sung-Bin Lin
  • Patent number: 8846540
    Abstract: A semiconductor device includes a semiconductor substrate having an etch target layer provided on the surface thereof, and a hard mask layer formed over the etch target layer and including silicon, wherein the hard mask layer includes a dual structure including a first area and a second area having a larger etch rate than the first area, in order to increase an etching selectivity of the hard mask layer.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: September 30, 2014
    Assignee: SK Hynix Inc.
    Inventors: Sung-Kwon Lee, Jun-Hyeub Sun, Young-Kyun Jung
  • Publication number: 20140099751
    Abstract: The present invention provides a method of forming a doping region. A substrate is provided, and a poly-silicon layer is formed on the substrate. A silicon oxide layer is formed on the poly-silicon layer. An implant process is performed to form a doping region in the poly-silicon layer. The present invention further provides a method for forming a MOS.
    Type: Application
    Filed: October 8, 2012
    Publication date: April 10, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hao Su, Hang Hu, Hong Liao
  • Patent number: 8685826
    Abstract: A method for forming a nanocrystalline silicon structure for the manufacture of integrated circuit devices, e.g., memory, dynamic random access memory, flash memory, read only memory, microprocessors, digital signal processors, application specific integrated circuits. The method includes providing a semiconductor substrate including a surface region. The method forms an insulating layer (e.g., silicon dioxide, silicon nitride, silicon oxynitride) overlying the surface region. In a specific embodiment, the method includes forming an amorphous silicon material of a determined thickness of less than twenty nanometers overlying the insulating layer using a chloro-silane species. The method includes subjecting the amorphous silicon material to a thermal treatment process to cause formation of a plurality of nanocrystalline silicon structures derived from the thickness of amorphous silicon material less than twenty nanometers.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: April 1, 2014
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Mieno Fumitake
  • Patent number: 8551837
    Abstract: Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-high-k/metal gate wafers and production tools. In some embodiments, the method comprises forming an interfacial layer over a semiconductor substrate on a front side of the substrate; forming a high-k dielectric layer and a capping layer over the interfacial layer; forming a metal layer over the high-k and capping layers; forming a polysilicon layer over the metal layer; and forming a dielectric layer over the semiconductor substrate on a back side of the substrate.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: October 8, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yih-Ann Lin, Ryan Chia-Jen Chen, Chien-Hao Chen, Kuo-Tai Huang, Yi-Hsing Chen, Jr Jung Lin, Yu Chao Lin
  • Patent number: 8546249
    Abstract: A method of depositing polycrystalline silicon exclusively on monocrystalline first silicon surface portions of a substrate surface which besides the first surface portions additionally has insulator surface portions, comprising the steps of depositing boron on the first silicon surface portions in an amount which in relation to the first silicon surface portions respectively corresponds to more than a monolayer of boron, and depositing silicon on the first silicon surface portions treated in that way.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: October 1, 2013
    Assignee: IHP GmbH—Innovations for High Performance
    Inventors: Bernd Tillack, Bernd Heinemann, Yuji Yamamoto
  • Patent number: 8471338
    Abstract: A dual polysilicon gate of a semiconductor device includes a substrate having a first region, a second region, and a third region, a channel region with a recessed structure formed in the first region of the substrate, a gate insulating layer formed over the substrate, a first polysilicon layer filled into the channel region, and formed over the gate insulating layer of the first and second regions, a second polysilicon layer formed over the gate insulating layer of the third region, and an insulating layer doped with an impurity, and disposed inside the first polysilicon layer in the channel region.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: June 25, 2013
    Assignee: Hynix Semiconductor
    Inventors: Kwan-Yong Lim, Heung-Jae Cho, Min-Gyu Sung
  • Patent number: 8450813
    Abstract: There is provided a fin transistor structure and a method of fabricating the same. The fin transistor structure comprises a fin formed on a semiconductor substrate, wherein a bulk semiconductor material is formed between a portion of the fin serving as the channel region of the transistor structure and the substrate, and an insulation material is formed between remaining portions of the fin and the substrate. Thereby, it is possible to reduce the current leakage while maintaining the advantages of body-tied structures.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: May 28, 2013
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Zhijiong Luo, Haizhou Yin, Huilong Zhu
  • Patent number: 8445973
    Abstract: There is provided a fin transistor structure and a method of fabricating the same. The fin transistor structure comprises a fin formed on a semiconductor substrate, wherein an insulation material is formed between a portion of the fin serving as the channel region of the transistor structure and the substrate, and a bulk semiconductor material is formed between remaining portions of the fin and the substrate. Thereby, it is possible to reduce the current leakage while maintaining the advantages such as low cost and high heat transfer.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: May 21, 2013
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Zhijiong Luo, Huilong Zhu, Haizhou Yin
  • Patent number: 8410554
    Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a structure which comprises a high-leakage dielectric formed in a divot on each side of a segmented FET comprised of active silicon islands and gate electrodes thereon, and a low-leakage dielectric on the surface of the active silicon islands, adjacent the high-leakage dielectric, wherein the low-leakage dielectric has a lower leakage than the high-leakage dielectric. Also provided is a structure and method of fabricating the structure.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: April 2, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Publication number: 20120326162
    Abstract: A repair layer forming process includes the following steps. Firstly, a substrate is provided, and a gate structure is formed on the substrate, wherein the gate structure at least includes a gate dielectric layer and a gate conductor layer. Then, a nitridation process is performed to form a nitrogen-containing superficial layer on a sidewall of the gate structure. Then, a thermal oxidation process is performed to convert the nitrogen-containing superficial layer into a repair layer. Moreover, a metal-oxide-semiconductor transistor includes a substrate, a gate dielectric layer, a gate conductor layer and a repair layer. The gate dielectric layer is formed on the substrate. The gate conductor layer is formed on the gate dielectric layer. The repair layer is at least partially formed on a sidewall of the gate conductor layer.
    Type: Application
    Filed: June 27, 2011
    Publication date: December 27, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Liang LIN, Ying-Wei Yen, Yu-Ren Wang
  • Patent number: 8237221
    Abstract: The semiconductor device according to the present invention includes a semiconductor layer, a trench formed by digging the semiconductor layer from the surface thereof, a gate insulating film formed on the inner surface of the trench, and a gate electrode made of silicon embedded in the trench through the gate insulating film. The gate electrode has a high-conductivity portion formed to cover the gate insulating film with a relatively high conductivity and a low-conductivity portion formed on a region inside the high-conductivity portion with a relatively low conductivity.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: August 7, 2012
    Assignee: Rohm Co., Ltd.
    Inventors: Ryotaro Yagi, Isamu Nishimura, Takahisa Yamaha
  • Patent number: 8193051
    Abstract: The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: June 5, 2012
    Assignee: International Business Machines Corporation
    Inventors: Nestor A. Bojarczuk, Jr., Cyril Cabral, Jr., Eduard A. Cartier, Matthew W. Copel, Martin M. Frank, Evgeni P. Gousev, Supratik Guha, Rajarao Jammy, Vijay Narayanan, Vamsi K. Paruchuri
  • Patent number: 7989362
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include a hafnium lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The hafnium lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a hafnium lanthanide oxynitride film.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: August 2, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn, Arup Bhattacharyya
  • Patent number: 7964514
    Abstract: A method for the deposition of a dielectric film including forming silicon nitride on the surface of the substrate, oxidizing the silicon nitride on the surface of the substrate, exposing the surface of the substrate to a hydrogen-free nitrogen source, and annealing the substrate. A method for the deposition of a dielectric film including forming silicon nitride on the surface of the substrate, oxidizing the silicon nitride on the surface of the substrate, including exposing the surface of the substrate to a gas selected from the group of oxygen, nitric oxide, and nitrous oxide, and exposing the surface of the substrate to a hydrogen-free nitrogen source, wherein the hydrogen-free nitrogen source is a gas selected from the group of nitrogen, nitric oxide, and nitrous oxide.
    Type: Grant
    Filed: March 2, 2006
    Date of Patent: June 21, 2011
    Assignee: Applied Materials, Inc.
    Inventor: Thai Cheng Chua
  • Patent number: 7892961
    Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a metal-containing layer on the gate dielectric; and forming a composite layer over the metal-containing layer. The step of forming the composite layer includes forming an un-doped silicon layer substantially free from p-type and n-type impurities; and forming a silicon layer adjoining the un-doped silicon layer. The step of forming the silicon layer comprises in-situ doping a first impurity. (or need to be change to: forming a silicon layer first & then forming un-doped silicon layer) The method further includes performing an annealing to diffuse the first impurity in the silicon layer into the un-doped silicon layer.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: February 22, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Cheng-Tung Lin, Liang-Gi Yao
  • Patent number: 7875518
    Abstract: A method for forming a semiconductor device includes, in order, consecutively depositing a gate insulating film and a silicon layer on a semiconductor substrate, implanting boron into the silicon layer, diffusing the boron by heat-treating the silicon layer, implanting phosphorous into the silicon layer, diffusing at least the phosphorous by heat-treating the silicon layer, and patterning the silicon layer by using a dry etching technique.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: January 25, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Satoru Yamada, Ryo Nagai
  • Patent number: 7858479
    Abstract: An object is to provide a semiconductor device in which uniform properties are intended and high yields are provided. Process steps are provided in which variations are adjusted in doping and annealing process steps that are subsequent process steps so as to cancel in-plane variations in a substrate caused by dry etching to finally as well provide excellent in-plane consistency in a substrate.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: December 28, 2010
    Assignee: Panasonic Corporation
    Inventors: Bunji Mizuno, Yuichiro Sasaki, Ichiro Nakayama, Hiroyuki Ito, Tomohiro Okumura, Cheng-Guo Jin, Katsumi Okashita, Hisataka Kanada
  • Patent number: 7842579
    Abstract: Various illustrative embodiments of methods for manufacturing a semiconductor device are described. These methods may include, for example, forming a first polysilicon layer above a substrate, wherein the first polysilicon layer comprises a doped portion, and forming a second polysilicon layer over a surface of the first polysilicon layer. Also, various illustrative embodiments of semiconductor devices are described that may be manufactured such as by the various methods described herein.
    Type: Grant
    Filed: January 22, 2007
    Date of Patent: November 30, 2010
    Assignee: Infineon Technologies AG
    Inventors: Haoren Zhuang, Matthias Lipinski, Jingyu Lian, Chandrasekhar Sarma
  • Patent number: 7808014
    Abstract: A semiconductor device includes a semiconductor layer including a base region of a second conductive type formed in a first surface of the semiconductor layer, an emitter region of the first conductive type formed in the base region, a buffer layer of the first conductive type formed on a second surface of the semiconductor layer, and a collector layer of the second conductive type formed on the buffer layer. The buffer layer has a maximal concentration of the first conductive type impurity of approximately 5 ×1015 cm?3 or less, and the collector layer has a maximal concentration of the second conductive type impurity of approximately 1×1017 cm?3 or more. The ratio of the maximal concentration of the collector layer to that of the buffer layer is greater than 100. The collector layer has a thickness of approximately 1 ?m or more.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: October 5, 2010
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Eisuke Suekawa
  • Patent number: 7737505
    Abstract: A semiconductor device may include, but is not limited to, a single crystal silicon diffusion layer, a polycrystal silicon conductor, and a diffusion barrier layer. The diffusion barrier layer separates the polycrystal silicon conductor from the single crystal silicon diffusion layer. The diffusion barrier layer prevents a diffusion of at least one of silicon-interstitial and silicon-vacancy between the single crystal silicon diffusion layer and the polycrystal silicon conductor.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: June 15, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Kensuke Okonogi, Kiyonori Ohyu
  • Patent number: 7714366
    Abstract: Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting CMOS transistor may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size may be directed to maximize dopant activation in the polysilicon near the gate dielectric and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. A region of polycrystalline silicon may have a varying grain size as a function of a distance measured from a surface of the dielectric film.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: May 11, 2010
    Assignee: International Business Machines Corporation
    Inventors: Arne W. Ballantine, Kevin K. Chan, Jeffrey D. Gilbert, Kevin M. Houlihan, Glen L. Miles, James J. Quinlivan, Samuel C. Ramac, Michael B. Rice, Beth A. Ward
  • Patent number: 7704823
    Abstract: To form a semiconductor device, an electrode layer is formed over a semiconductor body. The electrode layer includes an amorphous portion. A liner, e.g., a stress-inducing liner, is deposited over the electrode layer. The electrode layer is annealed to recrystallize the amorphous portion of the electrode layer. The liner can then be removed and an electronic component (e.g., a transistor) that includes a feature (e.g., a gate) formed from the electrode layer can be formed.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: April 27, 2010
    Assignee: Infineon Technologies AG
    Inventor: Richard Lindsay
  • Patent number: 7629219
    Abstract: A dual polysilicon gate of a semiconductor device includes a substrate having a first region, a second region, and a third region, a channel region with a recessed structure formed in the first region of the substrate, a gate insulating layer formed over the substrate, a first polysilicon layer filled into the channel region, and formed over the gate insulating layer of the first and second regions, a second polysilicon layer formed over the gate insulating layer of the third region, and an insulating layer doped with an impurity, and disposed inside the first polysilicon layer in the channel region.
    Type: Grant
    Filed: December 30, 2006
    Date of Patent: December 8, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kwan-Yong Lim, Heung-Jae Cho, Min-Gyu Sung
  • Publication number: 20090291548
    Abstract: A method for preparing a P-type polysilicon gate structure comprises the steps of forming a gate oxide layer on a substrate, forming an N-type polysilicon layer on the gate oxide layer, performing a first implanting process to convert the N-type polysilicon layer into a P-type polysilicon layer, performing a second implanting process to implant P-type dopants into a portion of the P-type polysilicon layer near the interface between the gate oxide layer and the P-type polysilicon layer, and performing a thermal treating process at a predetermined temperature for a predetermined period to complete the P-type polysilicon gate structure.
    Type: Application
    Filed: May 20, 2008
    Publication date: November 26, 2009
    Applicant: PROMOS TECHNOLOGIES INC.
    Inventors: YUAN MING CHANG, CHENG DA WU, DA YU CHUANG, YEN TA CHEN
  • Patent number: 7622383
    Abstract: A method of forming a conductive polysilicon thin film and a method of manufacturing a semiconductor device using the same are provided. The method of forming a conductive polysilicon thin film may comprise simultaneously supplying a Si precursor having halogen elements as a first reactant and a dopant to a substrate to form a first reactant adsorption layer that is doped with impurities on the substrate and then supplying a second reactant having H (hydrogen) to the first reactant adsorption layer to react the H of the second reactant with the halogen elements of the first reactant to form a doped Si atomic layer on the substrate.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: November 24, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Gyun Kim, Ki-Hyun Hwang, Jin-Tae Noh, Hong-Suk Kim, Sung-Hae Lee
  • Patent number: 7592240
    Abstract: A fabrication method for forming a gate structure through an amorphous silicon layer includes providing a substrate layer, forming an amorphous silicon layer of a selected thickness on the substrate layer at a reaction temperature between about 520° C. and 560° C., and forming a doped amorphous silicon layer in a upper portion of the amorphous silicon layer at a reaction temperature between about 520° C. and 560° C.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: September 22, 2009
    Assignee: Mosel Vitelic, Inc.
    Inventors: Jen Chieh Chang, Shih-Chi Lai, Yi Fu Chung, Tun-Fu Hung
  • Patent number: 7563730
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include a hafnium lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The hafnium lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a hafnium lanthanide oxynitride film.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: July 21, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn, Arup Bhattacharyya
  • Patent number: 7547621
    Abstract: A gate hard mask is deposited on a gate structure using low pressure chemical vapor deposition (LPCVD). By doing so, the wet etch removal ratio (WERR) of the gate hard mask relative to the underlying polysilicon gate layer is increased when compared to prior art hard masks. The LPCVD gate hard mask will not only etch faster than prior art hard masks, but it will also reduce undercutting of the gate oxide. To provide additional control of the wet etch rate, the LPCVD hard mask can be annealed. The annealing can be tailored to achieve the desired etching rate.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: June 16, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Rajesh Kanuri, Chorng-Ping Chang, Christopher Dennis Bencher, Hoiman Hung
  • Patent number: 7544604
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include a tantalum lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The tantalum lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a tantalum lanthanide oxynitride film.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: June 9, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn, Arup Bhattacharyya
  • Patent number: 7538001
    Abstract: A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited in an as-deposited material from which the lower metal layer of the second gate originates. However, the first gate's lower metal layer exhibits a modified work function different from a work function exhibited by the second gate's lower metal layer. The first gate's lower metal layer may contain less oxygen and/or carbon in comparison to the second gate's lower metal layer. The first gate's lower metal layer may contain more nitrogen in comparison to the second gate's lower metal layer. The first gate may be a n-channel gate and the second gate may be a p-channel gate.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: May 26, 2009
    Assignee: Micron Technology, Inc.
    Inventors: D. V. Nirmal Ramaswamy, Ravi Iyer
  • Patent number: 7476627
    Abstract: Methods are provided herein for treating substrate surfaces in preparation for subsequent nucleation-sensitive depositions (e.g., polysilicon or poly-SiGe) and adsorption-driven deposition (e.g. atomic layer deposition or ALD). Prior to depositing, the surface is treated with non-depositing plasma products. The treated surface more readily nucleates polysilicon and poly-SiGe (such as for a gate electrode), or more readily adsorbs ALD reactants (such as for a gate dielectric). The surface treatment provides surface moieties more readily susceptible to a subsequent deposition reaction, or more readily susceptible to further surface treatment prior to deposition. By changing the surface termination of the substrate with a low temperature radical treatment, subsequent deposition is advantageously facilitated without depositing a layer of any appreciable thickness and without significantly affecting the bulk properties of the underlying material.
    Type: Grant
    Filed: May 9, 2006
    Date of Patent: January 13, 2009
    Assignee: ASM America, Inc.
    Inventors: Christophe F. Pomarede, Jeff Roberts, Eric J. Shero
  • Patent number: 7476600
    Abstract: The invention includes a method of fabricating a gate structure for a field effect transistor and the gate structure. The method includes providing a crystalline silicon substrate and epitaxially growing a gate insulating layer of crystalline rare earth insulating material on the crystalline silicon substrate. A gate stack of crystalline silicon is then epitaxially grown on the layer of crystalline rare earth insulating material and doped to provide a desired type of conductivity. The gate insulating layer and the gate stack are etched and a metal electrical contact is deposited on the epitaxially grown gate stack of crystalline silicon to define a gate structure.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: January 13, 2009
    Assignee: Translucent, Inc.
    Inventor: Petar B. Atanackovic
  • Publication number: 20080290395
    Abstract: A method of realizing a flash floating poly gate using an MPS process can include forming a tunnel oxide layer on an active region of a semiconductor substrate; and then forming a first floating gate on and contacting the tunnel oxide layer; and then forming second and third floating gates on and contacting the first floating gate, wherein the second and third floating gates extend perpendicular to the first floating gate; and then forming a poly meta-stable polysilicon layer on the first, second and third floating gates; and then forming a control gate on the semiconductor substrate including the poly meta-stable polysilicon layer. Therefore, it is possible to increase the surface area of the capacitor by a limited area in comparison with a flat floating gate. As a result, it is possible to improve the coupling ratio essential to the flash memory device and to improve the yield and reliability of the semiconductor device.
    Type: Application
    Filed: May 16, 2008
    Publication date: November 27, 2008
    Inventor: Tae-Woong Jeong
  • Publication number: 20080206975
    Abstract: For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.
    Type: Application
    Filed: May 2, 2008
    Publication date: August 28, 2008
    Inventors: Takeshi SAKAI, Yasushi Ishii, Tsutomu Okazaki, Masaru Nakamichi, Toshikazu Matsui, Kyoya Nitta, Satoru Machida, Munekatsu Nakagawa, Yuichi Tsukada
  • Patent number: 7365027
    Abstract: The use of atomic layer deposition (ALD) to form an amorphous dielectric layer of titanium oxide (TiOx) doped with lanthanide elements, such as samarium, europium, gadolinium, holmium, erbium and thulium, produces a reliable structure for use in a variety of electronic devices. The dielectric structure is formed by depositing titanium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing a layer of a lanthanide dopant, and repeating to form a sequentially deposited interleaved structure. Such a dielectric layer may be used as the gate insulator of a MOSFET, as a capacitor dielectric, or as a tunnel gate insulator in flash memories, because the high dielectric constant (high-k) of the film provides the functionality of a thinner silicon dioxide film, and because the reduced leakage current of the dielectric layer when the percentage of the lanthanide element doping is optimized.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: April 29, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7224026
    Abstract: Diode devices with superior and pre-settable characteristics and of nanometric dimensions, comprise etched insulative lines (8, 16, 18) in a conductive substrate to define between the lines charge carrier flow paths, formed as elongate channels (20) at least 100 nm long and less than 100 nm wide. The current-voltage characteristic of the diode devices are similar to a conventional diode, but both the threshold voltage (from 0V to a few volts) and the current level (from nA to ?A) can be tuned by orders of magnitude by changing the device geometry. Standard silicon wafers can be used as substrates. A full family of logic gates, such as OR, AND, and NOT, can be constructed based on this device solely by simply etching insulative lines in the substrate.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: May 29, 2007
    Assignee: The University of Manchester
    Inventors: Amin Song, Pär Omling