Conductor Comprising Metal Or Metallic Silicide Formed By Deposition E.g., Sputter Deposition, I.e., Without Silicidation Reaction (epo) Patents (Class 257/E21.2)
  • Patent number: 11201227
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first insulating layer over a substrate. A first metal layer is formed in the first insulating layer and over the substrate. A silicon- and fluorine-containing barrier layer is formed between the first insulating layer and the first metal layer and between the substrate and the first metal layer. The silicon- and fluorine-containing barrier layer has a silicon content in a range from about 5% to about 20%.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Yun Hsu, Hsiao-Kuan Wei
  • Patent number: 11107902
    Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Gang Chen, Tai-Chun Huang, Yi-Ting Fu, Ming-Chang Wen, Shu-Yuan Ku, Fu-Kai Yang, Tze-Liang Lee, Yung-Cheng Lu
  • Patent number: 10879305
    Abstract: An image sensor includes a semiconductor substrate, a gate dielectric layer over the semiconductor substrate, a gate electrode over the gate dielectric layer, and a protection oxide film in contact with a top surface of the gate electrode. A top surface of the protection oxide film is free from contact with a hard mask comprising nitrogen.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Wei Chia, Chun-Hao Chou, Kai-Chun Hsu, Kuo-Cheng Lee, Shyh-Fann Ting
  • Patent number: 10811272
    Abstract: A method of forming a dielectric layer includes the following steps. A substrate including a first area and a second area is provided. A plurality of patterns on the substrate of the first area and a blanket stacked structure on the substrate of the second area are formed. An organic dielectric layer covers the patterns, the blanket stacked structure and the substrate. The blanket stacked structure is patterned by serving the organic dielectric layer as a hard mask layer, thereby forming a plurality of stacked structures. The organic dielectric layer is removed. A dielectric layer blanketly covers the patterns, the stacked structures, and the substrate.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: October 20, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Hsin Liu, Ta-Wei Chiu, Chia-Lung Chang, Po-Chun Chen, Hong-Yi Fang, Yi-Wei Chen
  • Patent number: 10651039
    Abstract: A method of forming a semiconductor device includes forming source regions and drain regions in a semiconductor substrate, and a gate electrode over said semiconductor substrate and between said source and drain regions. The gate electrode is formed from a first semiconductor gate electrode layer deposited on said gate dielectric layer at a first substrate temperature. A second semiconductor gate electrode layer is deposited on the first semiconductor gate electrode layer at a second substrate temperature greater than said first temperature. The two gate electrode layers may be annealed to form a homogenous polycrystalline layer with improved grain size distribution, thereby improving transistor matching in a semiconductor device.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 12, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pushpa Mahalingam, Umamaheswari Aghoram
  • Patent number: 10644064
    Abstract: An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-M RAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Kevin J. Lee, Tahir Ghani, Joseph M. Steigerwald, John H. Epple, Yih Wang
  • Patent number: 10546924
    Abstract: A field effect transistor including a dielectric layer on a substrate, a nano-structure material (NSM) layer on the dielectric layer, a source electrode and a drain electrode formed on the NSM layer, a gate dielectric formed on at least a portion of the NSM layer between the source electrode and the drain electrode, a T-shaped gate electrode formed between the source electrode and the drain electrode, where the NSM layer forms a channel of the FET, and a doping layer on the NSM layer extending at least from the sidewall of the source electrode to a first sidewall of the gate dielectric, and from a sidewall of the drain electrode to a second sidewall of the gate dielectric.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sarunya Bangsaruntip, Michael Engel, Shu-Jen Han
  • Patent number: 10504727
    Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits. More particularly, the implementations described herein provide techniques for deposition of thick hardmask films on a substrate. In one implementation, a method of forming a hardmask layer on a substrate is provided. The method comprises applying a chucking voltage to a substrate positioned on an electrostatic chuck in a processing chamber, forming a seed layer comprising boron on a film stack disposed on a substrate by supplying a seed layer gas mixture in the processing chamber while maintaining the chucking voltage, forming a transition layer comprising boron and tungsten on the seed layer by supplying a transition layer gas mixture in the processing chamber and forming a bulk hardmask layer on the transition layer by supplying a main deposition gas mixture in the processing chamber.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: December 10, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jiarui Wang, Prashant Kumar Kulshreshtha, Eswaranand Venkatasubramanian, Susmit Singha Roy, Kwangduk Douglas Lee
  • Patent number: 10428427
    Abstract: A fabrication method for two-dimensional materials of the present invention includes the following steps: forming a thin film having at least one two-dimensional element on a substrate; forming at least one capping layer on the thin film; annealing the thin film to form a two-dimensional material film after the capping layer is formed.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: October 1, 2019
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Tuo-Hung Hou, Jyun-Hong Huang
  • Patent number: 10411100
    Abstract: A semiconductor structure including a substrate, a dielectric layer and a polysilicon layer is provided. The dielectric layer is disposed on the substrate. The polysilicon layer is disposed on the dielectric layer. A fluorine dopant concentration in the polysilicon layer presents Gaussian distributions from a top portion to a bottom portion of the polysilicon layer. Fluorine dopant peak concentrations of the Gaussian distributions are progressively decreased from the top portion to the bottom portion of the polysilicon layer.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: September 10, 2019
    Assignee: United Microelectronics Corp.
    Inventor: Chen-Wei Pan
  • Patent number: 10256311
    Abstract: A fin field effect transistor (FinFET) is provided. The FinFET includes a first gate having top and bottom portions of different widths, the top portion of the first gate being disposed above the bottom portion of the first gate. The FinFET also includes a second gate having top and bottom portions of different widths, the top portion of the second gate being disposed above the bottom portion of the second gate. A first inter-layer dielectric layer is disposed between the first gate and the second gate in an interposed manner. The first inter-layer dielectric layer has a thickness equal to a height of the bottom portions of the first and second gates. A second inter-layer dielectric layer is patterned over the first inter-layer dielectric layer.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: April 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsueh-Wen Tsau, Chia-Ching Lee, Mrunal A. Khaderbad, Da-Yuan Lee
  • Patent number: 10164055
    Abstract: Vertical channel field effect transistors and methods of forming the same include forming one or more vertical channels on a bottom source/drain layer. A seed layer is deposited on horizontal surfaces around the one or more vertical channels. A metal gate is deposited on the seed layer. A top source/drain layer is deposited above the one or more vertical channels and the metal gate.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: December 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10163656
    Abstract: Embodiments of methods for etching cobalt metal using fluorine radicals are provided herein. In some embodiments, a method of etching a cobalt layer in a substrate processing chamber includes: forming a plasma from a process gas comprising a fluorine-containing gas; and exposing the cobalt layer to fluorine radicals from the plasma while maintaining the cobalt layer at a temperature of about 50 to about 500 degrees Celsius to etch the cobalt layer.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: December 25, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Bhushan N. Zope, Avgerinos V. Gelatos
  • Patent number: 10043669
    Abstract: A method for fabricating a metal gate structure includes following steps. A substrate is provided and followed by forming a high-K dielectric layer on the substrate. Then, an oxygen-containing titanium nitride layer is formed on the high-K dielectric layer. Next, an amorphous silicon layer is formed on the oxygen-containing titanium nitride layer and followed by performing an annealing process to drive oxygen in the oxygen-containing titanium nitride layer to the high-K dielectric layer.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: August 7, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Shao-Ping Chen
  • Patent number: 9960335
    Abstract: Cracking in a thermoelectric element made of a filled-skutterudite-type alloy is suppressed. A p-type thermoelectric element includes: a p-type thermoelectric conversion layer made of an alloy having a filled-skutterudite structure containing antimony; a p-side first metal layer that contains titanium simple substances and iron simple substances, and is laminated on the p-type thermoelectric conversion layer; and a p-side second metal layer that contains titanium simple substances, and is laminated on the p-side first metal layer.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: May 1, 2018
    Assignee: SHOWA DENKO K.K.
    Inventors: Yasutaka Yoshida, Kenichiro Nakajima
  • Patent number: 9935168
    Abstract: A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ILD) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed. The gate spacers are recessed until a height of the gate spacers is less than a height of the gate structure. An isolation liner is deposited above the gate spacers and the first conductive material. A portion of the isolation liner is removed so that a top surface of the first conductive material is exposed. A second conductive material is deposited in a contact hole created above the first conductive material and the gate spacers to form a gate contact.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: April 3, 2018
    Assignees: International Business Machines Corporation, GLOBALFOUNDRIES INC.
    Inventors: David V. Horak, Shom S. Ponoth, Balasubramanian Pranatharthiharan, Ruilong Xie
  • Patent number: 9761694
    Abstract: Vertical channel field effect transistors and methods of forming the same include forming one or more vertical channels on a bottom source/drain layer. A seed layer is deposited on horizontal surfaces around the one or more vertical channels. A metal gate is deposited on the seed layer. A top source/drain layer is deposited above the one or more vertical channels and the metal gate.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: September 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 9755051
    Abstract: An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress into the channel regions of the NMOS transistors and compressive stress into the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: September 5, 2017
    Assignee: STMicroelectronics, Inc.
    Inventors: John H. Zhang, Pietro Montanini
  • Patent number: 9754827
    Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: September 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chun-Han Tsao, Chih-Ming Chen, Han-Yu Chen, Szu-Yu Wang, Lan-Lin Chao, Cheng-Yuan Tsai
  • Patent number: 9653545
    Abstract: A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: May 16, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mahaveer Sathaiya Dhanyakumar, Wei-Hao Wu, Tsung-Hsing Yu, Chia-Wen Liu, Tzer-Min Shen, Ken-Ichi Goto, Zhiqiang Wu
  • Patent number: 9614047
    Abstract: A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ILD) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed. The gate spacers are recessed until a height of the gate spacers is less than a height of the gate structure. An isolation liner is deposited above the gate spacers and the first conductive material. A portion of the isolation liner is removed so that a top surface of the first conductive material is exposed. A second conductive material is deposited in a contact hole created above the first conductive material and the gate spacers to form a gate contact.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: April 4, 2017
    Assignees: International Business Machines Corporation, GlobalFoundries, Inc.
    Inventors: David V. Horak, Shom S. Ponoth, Balasubramanian Pranatharthiharan, Ruilong Xie
  • Patent number: 9466720
    Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: October 11, 2016
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Qing Liu, Nicolas Loubet
  • Patent number: 9461137
    Abstract: Embodiments of the present disclosure include tungsten silicide nitride films and methods for depositing tungsten silicide nitride films. In some embodiments, a thin film microelectronic device includes a semiconductor substrate having a tungsten gate electrode stack comprising a tungsten silicide nitride film having a formula WxSiyNz, wherein x is about 19 to about 22 atomic percent, y is about 57 to about 61 atomic percent, and z is about 15 to about 20 atomic percent. In some embodiments, a method of processing a substrate disposed in physical vapor deposition (PVD) chamber, includes: exposing a substrate having a gate insulating layer to a plasma formed from a first process gas comprising nitrogen and argon; sputtering silicon and tungsten material from a target disposed within a processing volume of the PVD chamber; depositing atop the gate insulating layer a tungsten silicide nitride layer as described above; and depositing a bulk tungsten layer atop the tungsten silicide nitride layer.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: October 4, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jothilingam Ramalingam, Rajkumar Jakkaraju, Jianxin Lei, Zhiyong Wang
  • Patent number: 9406779
    Abstract: An integrated circuit may be formed by removing source/drain spacers from offset spacers on sidewalls of MOS transistor gates, forming a contact etch stop layer (CESL) spacer layer on lateral surfaces of the MOS transistor gates, etching back the CESL spacer layer to form sloped CESL spacers on the lateral surfaces of the MOS transistor gates with heights of ¼ to ¾ of the MOS transistor gates, forming a CESL over the sloped CESL spacers, the MOS transistor gates and the intervening substrate, and forming a PMD layer over the CESL.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: August 2, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Tom Lii
  • Patent number: 9388038
    Abstract: A MEMS device formed by a body; a cavity, extending above the body; mobile and fixed structures extending above the cavity and physically connected to the body via anchoring regions; and electrical-connection regions, extending between the body and the anchoring regions and electrically connected to the mobile and fixed structures. The electrical-connection regions are formed by a conductive multilayer including a first semiconductor material layer, a composite layer of a binary compound of the semiconductor material and of a transition metal, and a second semiconductor material layer.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: July 12, 2016
    Assignee: STMicroelectronics S.r.l.
    Inventors: Roberto Campedelli, Raffaella Pezzuto, Stefano Losa, Marco Mantovani, Mikel Azpeitia Urquia
  • Patent number: 9349598
    Abstract: A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ILD) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed. The gate spacers are recessed until a height of the gate spacers is less than a height of the gate structure. An isolation liner is deposited above the gate spacers and the first conductive material. A portion of the isolation liner is removed so that a top surface of the first conductive material is exposed. A second conductive material is deposited in a contact hole created above the first conductive material and the gate spacers to form a gate contact.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: May 24, 2016
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: David V. Horak, Shom S. Ponoth, Balasubramanian Pranatharthiharan, Ruilong Xie
  • Patent number: 9269777
    Abstract: The present disclosure provides a semiconductor device including a gate stack disposed over a substrate, a source/drain (S/D) feature at least partially embedded within the substrate adjacent the gate stack. The S/D feature includes a first semiconductor material layer, a second semiconductor material layer disposed over the first semiconductor material layer. The second semiconductor material layer is different to the first semiconductor material layer. The S/D also includes a third semiconductor material layer disposed over the second semiconductor material layer, which includes a tin (Sn) material.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: February 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, Kun-Mu Li, Chii-Horng Li, Tze-Liang Lee
  • Patent number: 8841217
    Abstract: In one implementation, a chemical sensor is described. The chemical sensor includes a chemically-sensitive field effect transistor including a floating gate conductor having an upper surface. A dielectric material defines an opening extending to the upper surface of the floating gate conductor. A conductive element on a sidewall of the opening and extending over an upper surface of the dielectric material.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 23, 2014
    Assignee: Life Technologies Corporation
    Inventors: Keith Fife, James Bustillo, Jordan Owens
  • Patent number: 8802492
    Abstract: Methods for producing RRAM resistive switching elements having reduced forming voltage include doping to create oxygen deficiencies in the dielectric film. Oxygen deficiencies in a dielectric film promote formation of conductive pathways.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: August 12, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Jinhong Tong, Randall Higuchi, Imran Hashim, Vidyut Gopal
  • Patent number: 8664029
    Abstract: A process for fabricating a capacitance type tri-axial accelerometer comprises of preparing a wafer having an upper layer, an intermediate layer and a lower layer, etching the lower layer of the wafer to form an isolated proof mass having a core and four segments extending from the core, etching the upper layer of the wafer to form a suspension and four separating plates, etching away a portion of the intermediate layer located between the four segments of the proof mass and the plates of the upper layer, and disposing an electrical conducting means to pass through the intermediate layer from the suspension to the core of the proof mass.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: March 4, 2014
    Assignee: Domintech Co., Ltd.
    Inventor: Ming-Ching Wu
  • Patent number: 8664065
    Abstract: A method for forming a transistor having insulated gate electrodes and insulated shield electrodes within trench regions includes forming dielectric stack overlying a substrate. The dielectric stack includes a first layer of one material overlying the substrate and a second layer of a different material overlying the first layer. Trench regions are formed adjacent to the dielectric stack. After the insulated shield electrodes are formed, the method includes removing the second layer and then forming the insulated gate electrodes. Portions of gate electrode material are removed to form first recessed regions, and spacers are formed within the first recessed regions. Enhancements regions are then formed in the gate electrode material self-aligned to the spacers.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: March 4, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Gordon M. Grivna
  • Patent number: 8658485
    Abstract: There is provided a semiconductor device and a method of fabricating the same. The method of fabricating a semiconductor device according to the present invention comprises: forming a transistor structure including a gate, and source and drain regions on a semiconductor substrate; carrying out a first silicidation to form a first metal silicide layer on the source and drain regions; depositing a first dielectric layer on the substrate, the top of the first dielectric layer being flush with the top of the gate region; forming contact holes at the portions corresponding to the source and drain regions in the first dielectric layer; and carrying out a second silicidation to form a second metal silicide at the gate region and in the contact holes, wherein the first metal silicide layer is formed to prevent silicidation from occurring at the source and drain regions during the second silicidation.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: February 25, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Zhijiong Luo, Haizhou Yin, Huilong Zhu
  • Patent number: 8592305
    Abstract: Provided are methods of providing aluminum-doped TaSix films. Doping TaSix films allows for the tuning of the work function value to make the TaSix film better suited as an N-metal for NMOS applications. One such method relates to soaking a TaSix film with an aluminum-containing compound. Another method relates to depositing a TaSix film, soaking with an aluminum-containing compound, and repeating for a thicker film. A third method relates to depositing an aluminum-doped TaSix film using tantalum, aluminum and silicon precursors.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: November 26, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Xinliang Lu, Seshadri Ganguli, Shih Chung Chen, Atif Noori, Maitreyee Mahajani, Mei Chang
  • Patent number: 8569170
    Abstract: It is an object of the present invention to obtain a transistor with a high ON current including a silicide layer without increasing the number of steps. A semiconductor device comprising the transistor includes a first region in which a thickness is increased from an edge on a channel formation region side and a second region in which a thickness is more uniform than that of the first region. The first and second region are separated by a line which is perpendicular to a horizontal line and passes through a point where a line, which passes through the edge of the silicide layer and forms an angle ? (0°<?<45°) with the horizontal line, intersects with an interface between the silicide layer and an impurity region, and the thickness of the second region to a thickness of a silicon film is 0.6 or more.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: October 29, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromichi Godo, Hajime Tokunaga
  • Patent number: 8492259
    Abstract: A method of forming metal gate structure includes providing a substrate; forming a gate dielectric layer, a material layer and a polysilicon layer stacked on the substrate; forming a first mask layer, a second mask layer and a patterned photoresist on the polysilicon layer; removing portions of the second mask layer and the first mask layer to form a hard mask by utilizing the patterned photoresist as an etching mask; removing the patterned photoresist, and next utilizing the hard mask as an etching mask to remove parts of the polysilicon layer and parts of the material layer. Thus, a gate stack is formed. Since the patterned photoresist is removed before forming the gate stack, the gate stack is protected from damages of the photoresist-removing process. The photoresist-removing process does not attack the sidewalls of the gate stack, so a bird's beak effect of the gate dielectric layer is prevent.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: July 23, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Che-Hua Hsu, Shao-Hua Hsu, Zhi-Cheng Lee, Cheng-Guo Chen
  • Patent number: 8389417
    Abstract: An object is to provide a semiconductor device with a novel structure. A semiconductor device includes a first transistor, which includes a channel formation region provided in a substrate including a semiconductor material, impurity regions, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode, and a second transistor, which includes an oxide semiconductor layer over the substrate including the semiconductor material, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode. The second source electrode and the second drain electrode include an oxide region formed by oxidizing a side surface thereof, and at least one of the first gate electrode, the first source electrode, and the first drain electrode is electrically connected to at least one of the second gate electrode, the second source electrode, and the second drain electrode.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: March 5, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 8362570
    Abstract: This method for making complementary p and n MOSFET transistors with Schottky source and drain electrodes controlled by a gate electrode, comprising: making source and drain electrodes from a single silicide for both p and n transistors; segregating first impurities from groups II and III of the periodic table at the interface between the silicide and the channel of the p transistor, the complementary n transistor being masked; and segregating second impurities from groups V and VI of the periodic table, at the interface between the silicide and the channel of the n transistor, and the complementary p transistor being masked.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: January 29, 2013
    Assignee: Centre National de la Recherche Scientifique (C.N.R.S.)
    Inventors: Guilhem Larrieu, Emmanuel Dubois
  • Patent number: 8330234
    Abstract: In a semiconductor device, a gate electrode having a uniform composition prevents deviation in a work function. Controlling a Vth provides excellent operation properties. The semiconductor device includes an NMOS transistor and a PMOS transistor with a common line electrode. The line electrode includes electrode sections (A) and (B) and a diffusion barrier region formed over an isolation region so that (A) and (B) are kept out of contact. The diffusion barrier region meets at least one of: (1) The diffusion coefficient in the above diffusion barrier region of the constituent element of the above electrode section (A) is lower than the interdiffusion coefficient of the constituent element between electrode section (A) materials; and (2) The diffusion coefficient in the above diffusion barrier region of the constituent element of the above electrode section (B) is lower than the interdiffusion coefficient of the constituent element between electrode section (B) materials.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: December 11, 2012
    Assignee: NEC Corporation
    Inventor: Takashi Hase
  • Patent number: 8304841
    Abstract: A gate-last method for forming a metal gate transistor is provided. The method includes forming an opening within a dielectric material over a substrate. A gate dielectric structure is formed within the opening and over the substrate. A work function metallic layer is formed within the opening and over the gate dielectric structure. A silicide structure is formed over the work function metallic layer.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: November 6, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeff J. Xu, Cheng-Tung Lin, Hsiang-Yi Wang, Wen-Chin Lee, Betty Hsieh
  • Patent number: 8247257
    Abstract: A method for providing a semiconductor material for photovoltaic devices, the method includes providing a sample of iron disilicide comprising approximately 90 percent or greater of a beta phase entity. The sample of iron disilicide is characterized by a substantially uniform first particle size ranging from about 1 micron to about 10 microns. The method includes combining the sample of iron disilicide and a binding material to form a mixture of material. The method includes providing a substrate member including a surface region and deposits the mixture of material overlying the surface region of the substrate. In a specific embodiment, the mixture of material is subjected to a post-deposition process such as a curing process to form a thickness of material comprising the sample of iron disilicide overlying the substrate member. In a specific embodiment, the thickness of material is characterized by a thickness of about the first particle size.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: August 21, 2012
    Assignee: Stion Corporation
    Inventors: Howard W. H. Lee, Frederic Victor Mikulec, Bing Shen Gao, Jinman Huang
  • Patent number: 8158473
    Abstract: To provide a semiconductor device which can reduce an electrical resistance between a plug and a silicide region, and a manufacturing method thereof. At least one semiconductor element having a silicide region, is formed over a semiconductor substrate. An interlayer insulating film is formed over the silicide region. A through hole having an inner surface including a bottom surface comprised of the silicide regions is formed in the interlayer insulating film. A Ti(titanium) film covering the inner surface of the hole is formed by a chemical vapor deposition method. At least a surface of the Ti film is nitrided so as to form a barrier metal film covering the inner surface. A plug is formed to fill the through hole via the barrier metal film.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: April 17, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuhito Ichinose, Yukari Imai
  • Patent number: 8058092
    Abstract: A method for providing a semiconductor material for photovoltaic devices, the method includes providing a sample of iron disilicide comprising approximately 90 percent or greater of a beta phase entity. The sample of iron disilicide is characterized by a substantially uniform first particle size ranging from about 1 micron to about 10 microns. The method includes combining the sample of iron disilicide and a binding material to form a mixture of material. The method includes providing a substrate member including a surface region and deposits the mixture of material overlying the surface region of the substrate. In a specific embodiment, the mixture of material is subjected to a post-deposition process such as a curing process to form a thickness of material comprising the sample of iron disilicide overlying the substrate member. In a specific embodiment, the thickness of material is characterized by a thickness of about the first particle size.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: November 15, 2011
    Assignee: Stion Corporation
    Inventors: Howard W. H. Lee, Frederic Victor Mikulec, Bing Shen Gao, Jinman Huang
  • Patent number: 7858518
    Abstract: A process for the in situ formation of a selective contact and a local interconnect on a semiconductor substrate. The exposed semiconductor substrate regions of a semiconductor device structure may be treated in a plasma to enhance the adhesiveness of a selective contact thereto. The semiconductor device structure is positioned within a reaction chamber, wherein a selective contact is deposited onto the exposed semiconductor substrate regions. Any residual selective contact material may be removed from oxide surfaces either intermediately or after selective contact deposition. While the semiconductor device remains in the reaction chamber, a local interconnect is deposited over the semiconductor device structure. The local interconnect may then be patterned. Subsequent layers may be deposited over the local interconnect. The present invention also includes semiconductor device structures formed by the inventive process.
    Type: Grant
    Filed: February 4, 2002
    Date of Patent: December 28, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Christopher W. Hill, Weimin Li, Gurtej S. Sandhu
  • Patent number: 7737018
    Abstract: A process of forming an electronic device can include forming a gate electrode layer and forming a patterned masking layer. In a first aspect, a process operation is performed before removing substantially all of a lower portion of the gate electrode layer. In a second aspect, a gate dielectric layer is formed prior to forming the gate electrode layer, and a portion of the gate dielectric layer is exposed after removing the patterned masking layer and prior to forming another masking layer. A portion of the gate electrode layer remains covered during a process where some or all of the portion would be otherwise removed or consumed. By forming the electronic device using such a process, damage to the gate electrode structure while performing subsequent processing can be significantly reduced.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: June 15, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, Voon-Yew Thean, Vishal P. Trivedi
  • Patent number: 7687389
    Abstract: A method for fabricating a semiconductor device includes forming a gate insulation layer over a substrate, forming a first gate conductive layer over the gate insulation layer, forming a barrier metal over the first gate conductive layer, sequentially forming a second gate conductive layer and a gate hard mask over the barrier metal, patterning the gate hard mask, the second gate conductive layer, the barrier metal, the first gate conductive layer, and the gate insulation layer to form a gate pattern, and performing a plasma selective gate re-oxidation process on the gate pattern.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: March 30, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Kwan-Yong Lim, Min-Gyu Sung, Heung-Jae Cho, Hong-Seon Yang
  • Patent number: 7655557
    Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: February 2, 2010
    Assignee: International Business Machines Corporation
    Inventors: Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Jr., Richard D. Kaplan, Jakub T. Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda C. Mocuta, Vijay Narayanan, An L. Steegen, Maheswaren Surendra
  • Patent number: 7632744
    Abstract: Formation of an WNx film 24 constituting a barrier layer of a gate electrode 7A having a polymetal structure is effected in an atmosphere containing a high concentration nitrogen gas, whereby release of N (nitrogen) from the WNx film 24 is suppressed in the heat treatment step after the formation of the gate electrode 7A.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: December 15, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Naoki Yamamoto, Yoshikazu Tanabe, Hiroshige Kogayu, Takehiko Yoshida
  • Patent number: 7601635
    Abstract: For improving the reliability of a semiconductor device having a stacked structure of a polycrystalline silicon film and a tungsten silicide film, the device is manufactured by forming a polycrystalline silicon film, a tungsten silicide film and an insulating film successively over a gate insulating film disposed over the main surface of a semiconductor substrate, and patterning them to form a gate electrode having a stacked structure consisting of the polycrystalline silicon film and tungsten silicide film. The polycrystalline silicon film has two regions, one region formed by an impurity-doped polycrystalline silicon and the other one formed by non-doped polycrystalline silicon. The tungsten silicide film is deposited so that the resistivity of it upon film formation would exceed 1000 ??cm.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: October 13, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Kentaro Yamada, Masato Takahashi, Tatsuyuki Konagaya, Takeshi Katoh, Masaki Sakashita, Koichiro Takei, Yasuhiro Obara, Yoshio Fukayama
  • Patent number: 7592256
    Abstract: A method of forming a tungsten film on a surface of an object to be processed in a vessel capable of being vacuumized, includes the steps of forming a tungsten film by alternately repeating a reduction gas supplying process for supplying a reduction gas and a tungsten gas supplying process for supplying a tungsten-containing gas with an intervening purge process therebetween for supplying an inert gas while vacuumizing the vessel. A reduction gas supplying period of a reduction gas supplying process among the repeated reduction gas supplying processes is set to be longer than that of the remaining reduction gas supplying processes.
    Type: Grant
    Filed: August 7, 2002
    Date of Patent: September 22, 2009
    Assignee: Tokyo Electron Limited
    Inventors: Kazuya Okubo, Mitsuhiro Tachibana, Cheng Fang, Kohichi Sato, Hotaka Ishizuka
  • Patent number: 7585771
    Abstract: Method for manufacturing a semiconductor device, includes: forming a layer of dicobalt monosilicide (Co2Si) or of cobalt (Co) on a device-forming surface of a silicon substrate in a sputter apparatus, by utilizing a predetermined temperature profile; elevating a temperature of the silicon substrate to a predetermined temperature T2, which is equal to or higher than 600° C., conducted after forming the layer of Co or Co2Si; and forming a layer of monocobalt monosilicide (CoSi) on the device-forming surface of the silicon substrate at a temperature equal to or higher than T2, conducted after heating the silicon substrate to T2, wherein, the silicon substrate is elevated to a temperature between a highest reachable temperature T1 of the silicon substrate during forming the layer of Co or Co2Si and the temperature T2 at a temperature ramp rate of equal to or higher than 50° C./sec.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: September 8, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Tomoko Matsuda, Takamasa Itou