Conductor Comprising At Least Another Nonsilicon Conductive Layer (epo) Patents (Class 257/E21.198)
  • Patent number: 11038035
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate. The gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode structure. In addition, the first portion of the gate electrode structure is located over the second portion of the gate electrode structure, and a width of a top surface of the first portion of the gate electrode structure is greater than a width of a bottom surface of the second portion of the gate electrode structure.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Wen Hsieh, Wen-Jia Hsieh, Yi-Chun Lo, Mi-Hua Lin
  • Patent number: 10930754
    Abstract: Replacement metal gate structures with improved chamfered workfunction metal and self-aligned contact and methods of manufacture are provided. The method includes forming a replacement metal gate structure in a dielectric material. The replacement metal gate structure is formed with a lower spacer and an upper spacer above the lower spacer. The upper spacer having material is different than material of the lower spacer. The method further includes forming a self-aligned contact adjacent to the replacement metal gate structure by patterning an opening within the dielectric material and filling the opening with contact material. The upper spacer prevents shorting with the contact material.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: February 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 10326001
    Abstract: A semiconductor devices and methods of forming the same include forming a layer of activating material on sidewalls of a stack of alternating layers of channel material and sacrificial material. The layer of activating material is annealed to cause the activating material to react with the sacrificial material and to form insulating spacers at ends of the layers of sacrificial material. The layer of activating material is etched away to expose ends of the layers of channel material. Source/drain regions are formed on the ends of the layers of channel material.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robinhsinku Chao, ChoongHyun Lee, Heng Wu, Chun W. Yeung, Jingyun Zhang
  • Patent number: 10304941
    Abstract: Replacement metal gate structures with improved chamfered workfunction metal and self-aligned contact and methods of manufacture are provided. The method includes forming a replacement metal gate structure in a dielectric material. The replacement metal gate structure is formed with a lower spacer and an upper spacer above the lower spacer. The upper spacer having material is different than material of the lower spacer. The method further includes forming a self-aligned contact adjacent to the replacement metal gate structure by patterning an opening within the dielectric material and filling the opening with contact material. The upper spacer prevents shorting with the contact material.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: May 28, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 10276562
    Abstract: According to an exemplary embodiment, a chip is provided. The chip includes a first vertical device having a first threshold and second vertical device having a second threshold. The first vertical device includes a first source; a first channel over the first source; a first drain over the first channel; a first conductive layer adjacent to the first channel; and a first gate adjacent to the first conductive layer. The second vertical device includes a second source; a second channel over the second source; a second drain over the second channel; a second conductive layer adjacent to the second channel; and a second gate adjacent to the second conductive layer.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Ting Wang, Teng-Chun Tsai, Cheng-Tung Lin, De-Fang Chen, Hui-Cheng Chang
  • Patent number: 10177256
    Abstract: Replacement metal gate structures with improved chamfered workfunction metal and self-aligned contact and methods of manufacture are provided. The method includes forming a replacement metal gate structure in a dielectric material. The replacement metal gate structure is formed with a lower spacer and an upper spacer above the lower spacer. The upper spacer having material is different than material of the lower spacer. The method further includes forming a self-aligned contact adjacent to the replacement metal gate structure by patterning an opening within the dielectric material and filling the opening with contact material. The upper spacer prevents shorting with the contact material.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: January 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 10096512
    Abstract: Implementations described herein relate to methods for forming gap fill materials. After the gap fill material is deposited and before a CMP process is performed on the gap fill material, one or more ion implantation processes are utilized to treat the deposited gap fill material. The one or more ion implantation processes include implanting a first ion species in the gap fill material using a first ion energy, and then implanting a second ion species in the gap fill material using a second ion energy that's lower than the first ion energy. The one or more ion implantation processes minimize CMP dishing and improve recess profile.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: October 9, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Erica Chen, Ludovic Godet, Srinivas D. Nemani, Ellie Y. Yieh
  • Patent number: 10056489
    Abstract: Replacement metal gate structures with improved chamfered workfunction metal and self-aligned contact and methods of manufacture are provided. The method includes forming a replacement metal gate structure in a dielectric material. The replacement metal gate structure is formed with a lower spacer and an upper spacer above the lower spacer. The upper spacer having material is different than material of the lower spacer. The method further includes forming a self-aligned contact adjacent to the replacement metal gate structure by patterning an opening within the dielectric material and filling the opening with contact material. The upper spacer prevents shorting with the contact material.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: August 21, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 9916982
    Abstract: Structures for use in a replacement gate process involving a field-effect transistor and methods for forming such structures. A first dielectric layer is formed adjacent to a dummy gate structure, and a second dielectric layer is formed on the first dielectric layer. After the second dielectric layer is formed, a portion of the dummy gate structure is removed with an etching process to cut the dummy gate structure into disconnected segments. The second dielectric layer caps the first dielectric layer when the portion of the dummy gate structure is removed. The second dielectric layer has a higher etch rate selectivity than the first dielectric layer to the etching process.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: March 13, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xusheng Wu, Haigou Huang, John Zhang
  • Patent number: 9824920
    Abstract: One method disclosed includes, among other things, forming a first plurality of gate cavities in a first dielectric layer. A work function material layer is formed in the first plurality of gate cavities. A first conductive material is formed in at least a subset of the first plurality of gate cavities above the work function material layer to define a first plurality of gate structures. A first contact recess is formed in the first dielectric layer between two of the first plurality of gate structures. A second conductive material is formed in the first contact recess. The work function material layer is recessed selectively to the first and second conductive materials to define a plurality of cap recesses. A cap layer is formed in the plurality of cap recesses.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: November 21, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Chanro Park, Ruilong Xie, Hoon Kim, Min Gyu Sung
  • Patent number: 9685347
    Abstract: A semiconductor device comprises a semiconductor body with a front face and a back face, having an active zone located at the front face, a front surface metallization layer having a front face and a back face directed towards the active zone, the front surface metallization layer being provided on the front face of the semiconductor body and being electrically connected to the active zone, and a first barrier layer, comprising amorphous metal nitride, located between the active zone and the metallization layer. Further, a method for producing such a device is provided.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: June 20, 2017
    Assignee: Infineon Technologies AG
    Inventors: Jochen Hilsenbeck, Jens Peter Konrath, Stefan Krivec
  • Patent number: 9685532
    Abstract: Replacement metal gate structures with improved chamfered workfunction metal and self-aligned contact and methods of manufacture are provided. The method includes forming a replacement metal gate structure in a dielectric material. The replacement metal gate structure is formed with a lower spacer and an upper spacer above the lower spacer. The upper spacer having material is different than material of the lower spacer. The method further includes forming a self-aligned contact adjacent to the replacement metal gate structure by patterning an opening within the dielectric material and filling the opening with contact material. The upper spacer prevents shorting with the contact material.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: June 20, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 9324662
    Abstract: A semiconductor device and a manufacturing method thereof is provided. The method comprises: providing a substrate for the semiconductor device with a gate structure and a first dielectric interlayer being formed thereon, said gate structure comprising a metal gate and an upper surface of said first dielectric interlayer being substantially flush with an upper surface of said gate; forming an interface layer to cover at least the upper surface of said gate such that the upper surface of said gate is protected from being oxidized; and forming a second dielectric interlayer on said interface layer.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: April 26, 2016
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Xinpeng Wang, Yi Huang, Shih-Mou Chang
  • Patent number: 8536040
    Abstract: Generally, the present disclosure is directed to techniques for using material substitution processes to form replacement metal gate electrodes, and for forming self-aligned contacts to semiconductor devices made up of the same. One illustrative method disclosed herein includes removing at least a dummy gate electrode to define a gate cavity, forming a work-function material in said gate cavity, forming a semiconductor material above said work-function material, and performing a material substitution process on said semiconductor material to substitute a replacement material for at least a portion of said semiconductor material.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: September 17, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Chang Seo Park
  • Patent number: 8124515
    Abstract: Improved semiconductor devices comprising metal gate electrodes are formed with reduced performance variability by reducing the initial high dopant concentration at the top portion of the silicon layer overlying the metal layer. Embodiments include reducing the dopant concentration in the upper portion of the silicon layer, by implanting a counter-dopant into the upper portion of the silicon layer, removing the high dopant concentration portion and replacing it with undoped or lightly doped silicon, and applying a gettering agent to the upper surface of the silicon layer to form a thin layer with the gettered dopant, which layer can be removed or retained.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: February 28, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Man Fai Ng, Rohit Pal
  • Patent number: 7915128
    Abstract: A transistor suitable for high-voltage applications and a method of manufacture is provided. A first device is formed by depositing a dielectric layer and a conductive layer over a substrate. A hard mask is deposited over the conductive layer and patterned using photolithography techniques. The photoresist material is removed prior to etching the underlying conductive layer and dielectric layer. The hard mask is also used as an implant mask. Another mask may be deposited and formed over the conductive layer to form other devices in other regions of the substrate. The other mask is preferably removed from over the hard mask prior to etching the conductive layer and the dielectric layer.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: March 29, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu Wen Chen, Fu-Hsin Chen, Ming-Ren Tsai, William Wei-Yuan Tien
  • Patent number: 7811891
    Abstract: A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack (30, 32) formed over a substrate (36), thereby forming an etched gate (33) having a vertical sidewall profile (35). By constructing the gate stack (30, 32) with a graded material composition of silicon-based layers, the composition of which is selected to counteract the etching tendencies of the predetermined sequence of patterning and etching steps, a more idealized vertical gate sidewall profile (35) may be obtained.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: October 12, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Marius K. Orlowski, Olubunmi O. Adetutu, Phillip J. Stout
  • Patent number: 7632744
    Abstract: Formation of an WNx film 24 constituting a barrier layer of a gate electrode 7A having a polymetal structure is effected in an atmosphere containing a high concentration nitrogen gas, whereby release of N (nitrogen) from the WNx film 24 is suppressed in the heat treatment step after the formation of the gate electrode 7A.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: December 15, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Naoki Yamamoto, Yoshikazu Tanabe, Hiroshige Kogayu, Takehiko Yoshida
  • Patent number: 7611973
    Abstract: In methods of selectively forming an epitaxial semiconductor layer on a single crystalline semiconductor and semiconductor devices fabricated using the same, a single crystalline epitaxial semiconductor layer and a non-single crystalline epitaxial semiconductor layer are formed on a single crystalline semiconductor and a non-single crystalline semiconductor pattern respectively, using a main semiconductor source gas and a main etching gas. The non-single crystalline epitaxial semiconductor layer is removed using a selective etching gas. The main gases and the selective etching gas are alternately and repeatedly supplied at least two times to selectively form an elevated single crystalline epitaxial semiconductor layer having a desired thickness only on the single crystalline semiconductor. The selective etching gas suppresses formation of an epitaxial semiconductor layer on the non-single crystalline semiconductor pattern.
    Type: Grant
    Filed: June 16, 2005
    Date of Patent: November 3, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Suk Shin, Hwa-Sung Rhee, Tetsuji Ueno, Ho Lee, Seung-Hwan Lee
  • Patent number: 7566655
    Abstract: A process flow integration scheme employs one or more techniques to control stress in a semiconductor device formed thereby. In accordance with one embodiment, cumulative stress contributed by RTP of a nitride spacer and polysilicon gate, and subsequent deposition of a high stress etch stop layer, enhance strain and improve device performance. Germanium may be deposited or implanted into the gate structure in order to facilitate stress control.
    Type: Grant
    Filed: April 5, 2006
    Date of Patent: July 28, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Mihaela Balseanu, Jia Lee, Mei-Yee Shek, Amir Al-Bayati, Li-Qun Xia, Hichem M'Saad
  • Patent number: 7541269
    Abstract: A tungsten polymetal gate is made by forming a gate insulation layer and a polysilicon layer on a semiconductor substrate; depositing a barrier layer on the polysilicon layer; depositing a tungsten nucleation layer on the barrier layer through an ALD process; depositing a tungsten layer on the tungsten nucleation layer through a CVD process; depositing a hard mask layer on the tungsten layer; and etching the hard mask layer, the tungsten layer, the tungsten nucleation layer, the barrier layer, the polysilicon layer, and the gate insulation layer.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: June 2, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Soo Hyun Kim, Noh Jung Kwak, Baek Mann Kim, Young Jin Lee, Sun Woo Hwang, Kwan Yong Lim
  • Patent number: 7538030
    Abstract: An electrode on a semiconductor substrate includes a polysilicon layer, a silicon implanted layer on the polysilicon layer, a tungsten nitride layer on the silicon implanted layer, a tungsten nitride layer on the silicon implanted layer, and a tungsten layer on the tungsten nitride layer. The layer between the polysilicon layer and the tungsten nitride layer may be either a tungsten silicon nitride layer or a silicon-germanium layer.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: May 26, 2009
    Assignee: Renesas Technology Corp.
    Inventor: Kazuyoshi Maekawa
  • Patent number: 7479446
    Abstract: An electrode on a semiconductor substrate includes a polysilicon layer, a silicon-implanted layer on the polysilicon layer, a tungsten nitride layer on the silicon-implanted layer, a tungsten nitride layer on the silicon-implanted layer, and a tungsten layer on the tungsten nitride layer. The layer between the polysilicon layer and the tungsten nitride layer may be either a tungsten silicon nitride layer or a silicon-germanium layer.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: January 20, 2009
    Assignee: Renesas Technology Corp.
    Inventor: Kazuyoshi Maekawa
  • Publication number: 20080290415
    Abstract: A semiconductor device includes: an isolation region formed in a semiconductor substrate; a first active region and a second active region surrounded by the isolation region; an n-type gate electrode and a p-type gate electrode formed on gate insulating films; an insulating film and a silicon region formed on the isolation region and isolating the n-type gate electrode and the p-type gate electrode from each other; and a metal silicide film formed on the upper surfaces of the n-type gate electrode, the silicon region, the p-type gate electrode, and part of the insulating film formed therebetween. The n-type gate electrode is electrically connected to the p-type gate electrode through the metal silicide film.
    Type: Application
    Filed: January 4, 2008
    Publication date: November 27, 2008
    Inventors: Gen OKAZAKI, Akio SEBE
  • Patent number: 7446026
    Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate having a first doped region and a second doped region, providing a dielectric over the first doped region and the second doped region, and forming a first gate stack over the dielectric over at least a portion of the first doped region. The first gate stack includes a metal portion over the dielectric, a first in situ doped semiconductor portion over the metal portion, and a first blocking cap over the in situ doped semiconductor portion. The method further includes performing implantations to form source/drain regions adjacent the first and second gate stack, where the first blocking cap has a thickness sufficient to substantially block implant dopants from entering the first in situ doped semiconductor portion. Source/drain embedded stressors are also formed.
    Type: Grant
    Filed: February 8, 2006
    Date of Patent: November 4, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Da Zhang, Bich-Yen Nguyen
  • Patent number: 7375017
    Abstract: A method for fabricating a semiconductor a semiconductor device having a stacked-gate structure. A polysilicon layer is formed overlying a substrate, which is insulated from the substrate by a dielectric layer. A metal-flash layer is formed overlying the polysilicon layer, and then a tungsten nitride layer is formed overlying the titanium layer. The tungsten nitride layer is annealed using nitrogen and hydrogen gases. A tungsten layer and a cap layer are successively formed overlying the tungsten nitride layer.
    Type: Grant
    Filed: January 23, 2006
    Date of Patent: May 20, 2008
    Assignee: Nanya Technology Corporation
    Inventors: Tzu-En Ho, Chih-Hao Chang, Chang-Rong Wu, Kuo-Hui Su
  • Patent number: 7371681
    Abstract: An electrode on a semiconductor substrate includes a polysilicon layer, a silicon-implanted layer on the polysilicon layer, a tungsten nitride layer on the silicon-implanted layer, a tungsten nitride layer on the silicon-implanted layer, and a tungsten layer on the tungsten nitride layer. The layer between the polysilicon layer and the tungsten nitride layer may be either a tungsten silicon nitride layer or a silicon-germanium layer.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: May 13, 2008
    Assignee: Renesas Technology Corp.
    Inventor: Kazuyoshi Maekawa
  • Patent number: 7229919
    Abstract: A semiconductor device having a random grained polysilicon layer and a method for its manufacture are provided. In one example, the device includes a semiconductor substrate and an insulator layer on the substrate. A first polysilicon layer having a random grained structure is positioned above the insulator layer, a semiconductor alloy layer is positioned above the first polysilicon layer, and a second polysilicon layer is positioned above the semiconductor alloy layer.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: June 12, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Lin Chen, Liang-Gi Yao, Shih-Chang Chen
  • Patent number: 7129564
    Abstract: The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g.
    Type: Grant
    Filed: February 17, 2005
    Date of Patent: October 31, 2006
    Assignee: International Business Machines Corporation
    Inventors: Jochen Beintner, Yujun Li, Naim Moumen, Porshia Shane Wrschka