Abstract: A method of forming a tungsten film on a surface of an object to be processed in a vessel capable of being vacuumized, includes the steps of forming a tungsten film by alternately repeating a reduction gas supplying process for supplying a reduction gas and a tungsten gas supplying process for supplying a tungsten-containing gas with an intervening purge process therebetween for supplying an inert gas while vacuumizing the vessel. A reduction gas supplying period of a reduction gas supplying process among the repeated reduction gas supplying processes is set to be longer than that of the remaining reduction gas supplying processes.

Abstract: Method for manufacturing a semiconductor device, includes: forming a layer of dicobalt monosilicide (Co2Si) or of cobalt (Co) on a device-forming surface of a silicon substrate in a sputter apparatus, by utilizing a predetermined temperature profile; elevating a temperature of the silicon substrate to a predetermined temperature T2, which is equal to or higher than 600° C., conducted after forming the layer of Co or Co2Si; and forming a layer of monocobalt monosilicide (CoSi) on the device-forming surface of the silicon substrate at a temperature equal to or higher than T2, conducted after heating the silicon substrate to T2, wherein, the silicon substrate is elevated to a temperature between a highest reachable temperature T1 of the silicon substrate during forming the layer of Co or Co2Si and the temperature T2 at a temperature ramp rate of equal to or higher than 50° C./sec.

Abstract: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

Abstract: A method of manufacturing a non-volatile memory device includes the steps of forming gates respectively having a structure in which a gate insulating layer, a first conductive layer, a dielectric layer, a second conductive layer and a metal-silicide layer are laminated over a semiconductor substrate, annealing the metal-silicide layer at a temperature, which is the same as or lower than an annealing temperature of the dielectric layer, forming a buffer oxide layer on the entire surface, and forming a nitride layer on the buffer oxide layer.

Abstract: A memory structure including a semiconductor substrate, an insulator layer formed on the semiconductor substrate and a gate layer formed on the insulator layer is disclosed. The insulator layer includes a first nanocrystal implanted region proximate to the gate layer and a second nanocrystal implanted region proximate to the semiconductor substrate, wherein the first nanocrystal implanted region has an average nanocrystal concentration which is higher than an average nanocrystal concentration of the second nanocrystal implanted region.

Abstract: A gate structure includes a substrate, a gate dielectric layer, a first conductive layer, a second conductive layer, a cap layer and a first insulating spacer. The gate dielectric layer is disposed on the substrate. The first conductive layer is disposed on the gate dielectric layer and has an opening. A part of the second conductive layer is disposed in the opening. The second conductive layer has an extrusion that protrudes above the opening of the first conductive layer. The extrusion has a cross-sectional width less than the width of the second conductive layer inside the opening. The cap layer is disposed on the extrusion. The first insulating spacer is disposed on a part of the first conductive layer and covers the sidewalls of the extrusion. The inclusion of the extrusion in the second conductive layer decreases the resistance of the gate structure and promotes the efficiency of the device.

Abstract: A semiconductor device includes a structure of a gate electrode/a high-k dielectric insulating film containing aluminum and having a dielectric constant greater than that of a silicon oxide film/the silicon oxide film/a silicon substrate, and is provided with a diffusion layer formed by diffusing an aluminum atom or an aluminum ion to the silicon oxide film or an interface between the silicon oxide film and the silicon substrate by a heat treatment. A laminated film or a mixed film of hafnium oxide and aluminum oxide having a ratio of hafnium and aluminum ranging from about 2:8 to 8:2 is used as the high-k dielectric film. The heat treatment is performed at any temperature from about 500 to 1000° C. for any period of time from about 1 to 100 seconds.

Abstract: The technique capable of reducing the power consumption in the MISFET by suppressing the scattering of the carriers due to the fixed charges is provided. A silicon oxynitride film with a physical thickness of 1.5 nm or more and the relative dielectric constant of 4.1 or higher is formed at the interface between a semiconductor substrate and an alumina film. By so doing, a gate insulator composed of the silicon oxynitride film and the alumina film is constituted. The silicon oxynitride film is formed by performing a thermal treatment of a silicon oxide film formed on the semiconductor substrate in a NO or N2O atmosphere. In this manner, the fixed charges in the silicon oxynitride film are set to 5×1012 cm?2 or less, and the fixed charges in the interface between the silicon oxynitride film and the alumina film are set to 5×1012 cm?2 or more.

Abstract: A method of making a semiconductor structure includes etching an isolation oxide. The isolation oxide is in a substrate, a gate layer is on the substrate, a patterned metallic layer is on the gate layer, and a first patterned etch-stop layer is on the metallic layer.

Abstract: A method of forming transistor gate structures in an integrated circuit device can include forming a high-k gate insulating layer on a substrate including a first region to include PMOS transistors and a second region to include NMOS transistors. A polysilicon gate layer can be formed on the high-k gate insulating layer in the first and second regions. A metal silicide gate layer can be formed directly on the high-k gate insulating layer in the first region and avoiding forming the metal-silicide in the second region. Related gate structures are also disclosed.

Abstract: Thin film transistors for a display device each include a semiconductor layer made of polysilicon having a channel region, drain and source regions at both sides of the channel region and doped with impurity of high concentration, and an LDD region arranged either between the drain region and the channel region or between the source region and the channel region and doped with impurity of low concentration. An insulation film is formed over an upper surface of the semiconductor layer and has a film thickness which decreases in a step-like manner as it extends to the channel region, the LDD region, the drain and the source regions; and a gate electrode is formed over the channel region through the insulation film. Such a constitution can enhance the numerical aperture and can suppress the magnitude of stepped portions in a periphery of the thin film transistor.

Abstract: A biased pulse DC reactor for sputtering of oxide films is presented. The biased pulse DC reactor couples pulsed DC at a particular frequency to the target through a filter which filters out the effects of a bias power applied to the substrate, protecting the pulsed DC power supply. Films deposited utilizing the reactor have controllable material properties such as the index of refraction. Optical components such as waveguide amplifiers and multiplexers can be fabricated using processes performed on a reactor according to the present inention.

Abstract: A method of fabricating a recess channel array transistor. Using a mask layer pattern having a high etch selectivity with respect to a silicon substrate, the silicon substrate and an isolation insulating layer are etched to form a recess channel trench. After forming a gate insulating layer and a recess gate stack on the recess channel trench, a source and a drain are formed in the silicon substrate adjacent to both sidewalls of the recess gate stack, thereby completing the recess channel array transistor. Because the mask layer pattern having the high etch selectivity with respect to the silicon substrate is used, a depth of the recess channel trench is easily controlled while good etching uniformity of the silicon substrate is obtained.

Abstract: A semiconductor device and method of manufacturing the same. The semiconductor device includes a semiconductor substrate having a first conductive layer, a second conductive layer on the first conductive layer, a first high density impurity area on the second conductive layer, and a second high density impurity area on the first impurity area; a trench exposing the first conductive layer; a gate insulating layer on an inner wall of the trench; a polysilicon layer on the gate insulating layer; and a metal layer on the polysilicon layer in the trench, in which the metal layer fills the trench.

Abstract: A method is provided for forming a metal/semiconductor/metal (MSM) current limiter and resistance memory cell with an MSM current limiter. The method includes the steps of: providing a substrate; forming an MSM bottom electrode overlying the substrate; forming a ZnOx semiconductor layer overlying the MSM bottom electrode, where x is in the range between about 1 and about 2, inclusive; and, forming an MSM top electrode overlying the semiconductor layer, The ZnOx semiconductor can be formed through a number of different processes such as spin-coating, direct current (DC) sputtering, radio frequency (RF) sputtering, metalorganic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD).

Abstract: For improving the reliability of a semiconductor device having a stacked structure of a polycrystalline silicon film and a tungsten silicide film, the device is manufactured by forming a polycrystalline silicon film, a tungsten silicide film and an insulating film successively over a gate insulating film disposed over the main surface of a semiconductor substrate, and patterning them to form a gate electrode having a stacked structure consisting of the polycrystalline silicon film and tungsten silicide film. The polycrystalline silicon film has two regions, one region formed by an impurity-doped polycrystalline silicon and the other one formed by non-doped polycrystalline silicon. The tungsten silicide film is deposited so that the resistivity of it upon film formation would exceed 1000 ??cm.

Abstract: According to the manufacturing method of the semiconductor device of the present invention, an oxide film is formed on a metal film formed on a main surface of a semiconductor substrate by exposing the metal film to the oxidizing gas. The oxide film is then reduced in a reducing atmosphere, and a protection film is formed on the surface of the metal film reduced in the reducing step. In this manner, the damage to the surface of the metal film can be prevented.

Abstract: The present disclosure relates to a rapid thermal processing system that may be useful for processing semiconductor devices. A flash lamp may be utilized to provide pulse heating of a semiconductor for annealing or other purposes. A sensor may be provided to sense a characteristic of a semiconductor when a pre-pulse is applied to the semiconductor. Subsequent pulses may then be adjusted based on the characteristic sensed by the sensor.