Abstract: In accordance with the present invention, accurate and easily controlled sloped walls may be formed using. AlN and preferably a heated TMAH for such purpose as the fabrication of MEMS devices, wafer level packaging and fabrication of fluidic devices. Various embodiments are disclosed.

Abstract: A method for forming a semiconductor device is disclosed. A substrate comprising a structural layer thereon is provided. A hard mask layer is formed on the structural layer. A photoresist layer is formed on the hard mask layer. The photoresist layer is patterned to from a plurality of main photoresist patterns and at least one dummy photoresist pattern between the main photoresist patterns or adjacent to one of the main photoresist patterns, wherein width of the dummy photoresist pattern is less than that of the main photoresist patterns. Two main photoresist patterns are separated with each other by a first opening, and two dummy photoresist patterns are separated with each other by a second opening. Width of the second opening is less than that of the first opening. The hard mask layer is patterned using the patterned photoresist layer as a mask. The structural layer is patterned using the patterned hard mask layer as a mask.

Abstract: A process for manufacturing a semiconductor device, comprising: preparing a substrate in which a silicon-containing resist pattern is formed on a processed-material layer, dry-etching the processed-material layer using the silicon-containing resist pattern as a mask to form a processed-material layer pattern, ashing the silicon-containing resist pattern to leave a silicon-containing residual resist, immersing the substrate on which the silicon-containing residual resist remains into pure water to swell and deform the silicon-containing residual resist, and immersing the substrate on which the swelled and deformed silicon-containing residual resist remains into diluted hydrofluoric acid to remove the silicon-containing residual resist.

Abstract: A method of forming fine patterns of semiconductor device according to an example embodiment may include forming a plurality of multi-layered mask patterns by stacking first mask patterns and buffer mask patterns on an etch film to be etched on a substrate, forming, on the etch film, second mask patterns in spaces between the plurality of multi-layered mask patterns, removing the second mask patterns to expose upper surfaces of the first mask patterns, and forming the fine patterns by etching the etch film using the first and second mask patterns as an etch mask. This example embodiment may result in the formation of diverse dimensions at diverse pitches on a single substrate.

Abstract: A simple and cost-effective possibility is proposed for producing optically transparent regions (5, 6) in a silicon substrate (1), by the use of which both optically transparent regions of any thickness and optically transparent regions over a cavity in a silicon substrate are able to be implemented. For this purpose, first at least a specified region (5, 6) of the silicon substrate (1) is etched porous. Thereafter, the specified porous region (5, 6) of the silicon substrate (1) is oxidized.

Abstract: A method for forming a self-aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material being either photo or thermally sensitive; performing a blanket exposure of the substrate; and allowing at least a portion of the masking material to preferential develop in a fashion that is replicates the existing pattern of the substrate. The existing pattern may be comprised of a first set of regions of the substrate having a first reflectivity and a second set of regions of the substrate having a second reflectivity different from the first composition. The first set of regions may include one or more metal elements and the second set of regions may include a dielectric. Structures made in accordance with the method.

Abstract: A method for forming an etch-stop layer and a resulting structure fabricated therefrom. The etch-stop layer is a silicon-germanium layer having a ratio of silicon to germanium of about 50:1 or less, a boron layer formed within the silicon-germanium layer where the boron layer has a full-width half-maximum (FWHM) thickness value of less than 50 nanometers, and a carbon layer formed within the silicon-germanium layer where the carbon layer has an FWHM thickness value of less than 50 nanometers. A ratio of boron to carbon in the etch-stop layer is in a range of about 0.5 to 1.5.

Abstract: A Method of forming microelectromechanical optical display devices is provided. A sacrificial layer is formed above a substrate. A plurality of posts penetrating the sacrificial layer is formed. A reflective layer and a flexible layer are sequentially formed above the sacrificial layer and the posts. A photoresist layer is formed on part of the flexible layer. By performing wet etching using the photoresist layer as a mask, a portion of the flexible layer is removed to form a patterned flexible layer. The wet etching is stopped on the reflective layer. The photoresist layer is removed. By performing dry etching using the patterned flexible layer as a mask, a portion of the reflective layer is removed to form a patterned reflective layer. A mechanical layer is formed with the patterned flexible and reflective layers. The sacrificial layer is removed to release the mechanical layer.

Abstract: A wafer has thereon a plurality of integrated circuit die areas, scribe line that surrounds each of the integrated circuit die areas, and a laser marking region having therein a laser marking feature. A pad layer is formed on the wafer. AA photoresist pattern is formed on the pad layer. The AA photoresist pattern includes trench openings that expose STI trench areas within the integrated circuit die areas and dummy openings that merely expose a transitioning region of the laser-marking region. The pad layer and the substrate are etched through the trench openings and dummy openings, to form STI trenches within the integrated circuit die areas and dummy trenches in the transitioning region. A trench fill dielectric is deposited over the wafer and fills the STI trenches and the dummy trenches. Using the pad nitride layer as a polish stop layer, chemical mechanical polishing the trench fill dielectric.

Abstract: A method of forming a via contact structure using a dual damascene process is disclosed. According to one embodiment a sacrificial layer is formed on an insulating interlayer during the formation of a preliminary via hole. The sacrificial layer has the same composition as a layer filling the preliminary via hole in a subsequent trench formation process. The sacrificial layer and the layer filling the preliminary via hole are simultaneously removed after the trench formation process is carried out. According to another embodiment, a thin capping oxide layer is formed on an insulating interlayer during the formation of a preliminary via hole. The thin capping oxide layer is removed together with a sacrificial layer after a trench formation process is carried out.

Abstract: In a method for manufacturing a semiconductor device wherein via holes are formed in an SiC substrate, a stacked film consisting of a Ti film and an Au film is formed on the back face of the SiC substrate, and a Pd film is formed thereon. Then, an Ni film is formed by non-electrolytic plating, using the Pd film as a catalyst. Thereafter, via holes penetrating through the SiC substrate are formed by etching, using the Ni film as a mask.

Abstract: Two pitch-shrinking technologies are invented, which allow us to further reduce the pitch size significantly smaller than the minimum feature size resolvable with any conventional lithographic technology. One technology can be used to shrink the pitch size of both line/space (straight or wiggling) and contact-hole patterns by half from the initial (minimum) pitch size resolvable with a conventional lithography, and the other technology can reduce the pitch size of a line/space pattern down to one third of the initial pitch size resolvable with a conventional lithography. These two technologies provide production worthy methods for the whole semiconductor industry to continue the functional device scaling beyond the resolution limit of the conventional lithography.

Abstract: A method of processing a substrate of a device comprises the as following steps. Form a cap layer over the substrate. Form a dummy layer over the cap layer, the cap layer having a top surface. Etch the dummy layer forming patterned dummy elements of variable widths and exposing sidewalls of the dummy elements and portions of the top surface of the cap layer aside from the dummy elements. Deposit a spacer layer over the device covering the patterned dummy elements and exposed surfaces of the cap layer. Etch back the spacer layer forming sidewall spacers aside from the sidewalls of the patterned dummy elements spaced above a minimum spacing and forming super-wide spacers between sidewalls of the patterned dummy elements spaced less than the minimum spacing. Strip the patterned dummy elements. Expose portions of the substrate aside from the sidewall spacers. Pattern exposed portions of the substrate by etching into the substrate.

Abstract: In an embodiment, a method of producing a diffraction grating comprises steps of: forming, on a man surface of a first member, a first mask having a plurality of resist patterns arranged at a Bragg diffraction period; etching the first member by use of the first mask, thereby providing the first member with a diffraction grating; removing the first mask; forming, on the diffraction grating, a second member of which an etching rate is lower than that of the first member; forming a second mask on a first region in a surface of the second member, the first region and a second region in the surface being adjacent to each other; and etching the first member and the second member by use of the second mask.

Abstract: A feature in a layer is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls, where the photoresist features have a first critical dimension. A conformal layer is deposited over the sidewalls of the photoresist features to reduce the critical dimensions of the photoresist features. Features are etched into the layer, wherein the layer features have a second critical dimension, which is less than the first critical dimension.

Abstract: A process for defining and controlling the mask height of sensor devices is disclosed. An RIE-resistant, image layer, such as Cu or NiFe, is deposited after the DLC layer. A combination of RIE and ion milling processes or reactive ion beam etching processes are used to form the mask structure. Having an RIE-resistant layer precisely defines the DLC edge and minimizes the line edge roughness that result from fast removal of duramide during RIE. This solution controls the formation of the edges of the sensors and provides good definition for DLC mask edges. The image layer may be chemical mechanical polished to eliminate ion milling before the final RIE step.

Abstract: A process for defining and controlling the track width for sensor devices is disclosed. An RIE-resistant, image layer, such as Cu or NiFe, is deposited after the DLC layer. A combination of RIE and ion milling processes or reactive ion beam etching processes are used to form the mask structure. Having an RIE-resistant layer precisely defines the DLC edge and minimizes the line edge roughness that result from fast removal of duramide during RIE. This solution controls the formation of the edges of the sensors and provides good definition for DLC mask edges. The image layer may be chemical mechanical polished to eliminate ion milling before the final RIE step.

Abstract: By providing an etch stop layer selectively at the bevel, at least one additional wet chemical bevel etch process may be performed prior to or during the formation of a metallization layer without affecting the substrate material. Hence, the dielectric material, especially the low-k dielectric material, may be reliably removed from the bevel prior to the formation of any barrier and metal layers. The etch stop layer may be formed at an early manufacturing stage so that a bevel etch process may be performed at any desired stage of the formation of circuit elements.

Abstract: Disclosed herein is a method for manufacturing a semiconductor device that includes performing an O2 plasma treatment step after forming a Si-containing photoresist film.

Abstract: A method providing features in a dielectric layer is provided. A sacrificial layer is formed over the dielectric layer. A set of sacrificial layer features is etched into the sacrificial layer. A first set of dielectric layer features is etched into the dielectric layer through the sacrificial layer. The first set of dielectric layer features and the set of sacrificial layer features are filled with a filler material. The sacrificial layer is removed. The widths of the spaces between the parts of the filler material are shrunk with a shrink sidewall deposition. A second set of dielectric layer features is etched into the dielectric layer through the shrink sidewall deposition. The filler material and shrink sidewall deposition are removed.

Abstract: A process for defining and controlling the track width for sensor devices is disclosed. An RIE-resistant, image layer, such as Cu or NiFe, is deposited after the DLC layer. A combination of RIE and ion milling processes or reactive ion beam etching processes are used to form the mask structure. Having an RIE-resistant layer precisely defines the DLC edge and minimizes the line edge roughness that result from fast removal of duramide during RIE. This solution controls the formation of the edges of the sensors and provides good definition for DLC mask edges. The image layer may be chemical mechanical polished to eliminate ion milling before the final RIE step.

Abstract: A process for defining and controlling the mask height of sensor devices is disclosed. An RIE-resistant, image layer, such as Cu or NiFe, is deposited after the DLC layer. A combination of RIE and ion milling processes or reactive ion beam etching processes are used to form the mask structure. Having an RIE-resistant layer precisely defines the DLC edge and minimizes the line edge roughness that result from fast removal of duramide during RIE. This solution controls the formation of the edges of the sensors and provides good definition for DLC mask edges. The image layer may be chemical mechanical polished to eliminate ion milling before the final RIE step.

Abstract: A semiconductor device includes a semiconductor substrate, a film stack formed on the semiconductor substrate and having a film to be processed. A dual hard mask included in the film stack has an amorphous carbon layer and an underlying hard mask layer interposed between the amorphous carbon layer and the film to be processed, the hard mask layer does not include an amorphous carbon layer. A damascene structure for a metal interconnect is formed in the film stack. The amorphous carbon film can, for example, be incorporated within a single damascene structure, or a dual damascene structure. The amorphous carbon film can serve as part of a lithographic mask for forming the interconnect structure, or it may serve as a top layer of a dual hard mask, a chemical mechanical polishing (CMP) stop layer, or a sacrificial layer during CMP.