Abstract: A semiconductor package includes a semiconductor chip provided with a first surface having a bonding pad, a second surface opposing to the first surface and side surfaces; a first redistribution pattern connected with the bonding pad and extending along the first surface from the bonding pad to an end portion of the side surface which meets with the second surface; and a second redistribution pattern disposed over the first redistribution pattern and extending from the side surfaces to the first surface. In an embodiment of the present invention, in which the first redistribution pattern connected with the bonding pad is formed over the semiconductor chip and the second redistribution pattern is formed over the first redistribution pattern, it is capable of reducing a length for signal transfer since the second redistribution pattern is used as an external connection terminal.

Abstract: An embedded semiconductor die package is made by mounting a frame carrier to a temporary carrier with an adhesive. The frame carrier includes die mounting sites each having a leadframe interconnect structure around a cavity. A semiconductor die is disposed in each cavity. An encapsulant is deposited in the cavity over the die. A package interconnect structure is formed over the leadframe interconnect structure and encapsulant. The package interconnect structure and leadframe interconnect structure are electrically connected to the die. The frame carrier is singulated into individual embedded die packages. The semiconductor die can be vertically stacked or placed side-by-side within the cavity. The embedded die packages can be stacked and electrically interconnected through the leadframe interconnect structure. A semiconductor device can be mounted to the embedded die package and electrically connected to the die through the leadframe interconnect structure.

Abstract: A backgrinding machine 10 of a semiconductor wafer W includes: a table 13 set on the working plane of a mount 11; a multiple number of holding jigs 20 arranged via check tables 15 on table 13; a grinding machine 30 for performing a grinding process of the rear side of semiconductor wafer W held by holding jig 20; and a washing device 40 for ground semiconductor wafers W. Each holding jig 20 is constructed of a concave 22 depressed on the surface of a base plate 21, a multiple number of supporting projections 23 projectively arrayed on the bottom surface of concave 22, a deformable contact film 24, covering the concave 22, being supported by the multiple supporting projections 23, for detachably holding semiconductor wafer W in close contact with it; and an exhaust path 25 for conducting air from the concave 22 covered by contact film 24 to the outside.

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a conductive feature extending through a semiconductor substrate such that the conductive feature has a first end and a second end opposite the first end, and wherein the second end projects outwardly from a surface of the substrate. The method can further include forming a dielectric layer over the surface of the substrate and the second end of the conductive feature such that the dielectric layer has an original thickness. The method can also include removing a portion of the dielectric layer to an intermediate depth less than the original thickness such that at least a portion of the second end of the conductive feature is exposed.

Abstract: A laser release and glass chip removal process for a integrated circuit module avoiding carrier edge cracking is provided.

Abstract: A method of manufacturing a solar cell by providing a first substrate; depositing on the first substrate a sequence of layers of semiconductor material forming a solar cell including a top subcell and a bottom subcell; forming a metal back contact over the bottom subcell; forming a group of discrete, spaced-apart first bonding elements over the surface of the back metal contact; attaching a surrogate substrate on top of the back metal contact using the bonding elements; and removing the first substrate to expose the surface of the top subcell.

Abstract: The compositions and methods for the removal of residues and contaminants from metal or dielectric surfaces comprises at least one alkyl diphosphonic acid, at least one second acidic substance at amble ratio of about 1:1 to about 10:1 in water, arid pH is adjusted to from about 6 to about 10 with a metal ion free base, and a surfactant. Particularly, a composition and method of cleaning residues after chemical mechanical polishing of a copper or aluminum surface of the semiconductor substrates.

Abstract: A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide granules, grinding and polishing a top surface of the wafer, etching the top surface for eliminating a top process-induced degradation layer and maintaining a 0.5 ?m-10 ?m thick edge process-induced degradation layer.

Abstract: A method of manufacturing an electronic device that comprises a microelectromechanical (MEMS) element, the method comprising the steps of: providing a material layer (34) on a first side of a substrate (32); providing a trench (40) in the material later (34); etching material from the trench (40) such as to also etch the substrate (32) from the first side of the substrate (32); grinding the substrate (32) from a second side of the substrate to expose the trench (40); and using the exposed trench (40) as an etch hole. The exposed trench (40) is used as an etch hole for releasing a portion of the material layer (34), for example a beam resonator (12), from the substrate (32). An input electrode (6), an output electrode (8), and a top electrode (10) are provided.

Abstract: An optical device wafer processing method for dividing an optical device wafer into a plurality of individual optical devices. The optical device wafer is composed of a substrate and a semiconductor layer formed on the front side of the substrate. The optical devices are partitioned by a plurality of crossing division lines formed on the semiconductor layer.

Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a device substrate having a front side, a back side, and a first edge portion, forming a material layer over a portion of the front side of the device substrate, trimming the first edge portion, removing the material layer, bonding the front side of the device substrate to a carrier substrate, thinning the device substrate from the back side, and trimming a second edge portion of the thinned device substrate.

Abstract: To provide a thin semiconductor device having flexibility. A groove is formed in one surface of a substrate; an element layer including an element is formed, the element being disposed within the groove; the substrate is thinned from the other surface of the substrate until one surface of the element layer is exposed, to form a layer which is to be transposed, having the element; and the layer to be transposed is transposed onto the film.

Abstract: A method for fabricating an image sensor is provided. In the image sensor fabrication method, an interconnection and a dielectric interlayer are formed on a semiconductor substrate including a readout circuit. An image sensing unit is formed on a carrier substrate of one side of a dielectric layer. The carrier substrate and the dielectric interlayer are bonded to each other. The dielectric layer and the carrier substrate are removed to leave the image sensing unit on the dielectric interlayer.

Abstract: A multi-station polish system and process for polishing thin, flat (planar) and rigid workpieces. Workpieces are conveyed through multiple polishing stations that include a bulk material removal belt polishing station and finishing rotary polishing station. The bulk of the material is relatively quickly removed at the bulk removal station using a conformable abrasive belt and the workpiece surface is then polished to the desired finish at the finishing station using a conformable annular rotary polishing pad.

Abstract: An optical device wafer processing method for dividing an optical device wafer into a plurality of individual optical devices. The optical device wafer is composed of a substrate and a semiconductor layer formed on the front side of the substrate. The optical devices are partitioned by a plurality of crossing division lines formed on the semiconductor layer.

Abstract: A micro-fluid ejection head has multiple ejection chips joined adjacently to create a lengthy array across a media to-be-imaged. The chips have fluid firing elements arranged to seamlessly stitch together fluid ejections from adjacent chips. Each chip aligns with other chips at peripheral regions having edge tolerances closer than elsewhere along the periphery. The tolerances result from both etching and dicing during chip singulation. Etching occurs at the areas of alignment. Dicing occurs elsewhere. Etching techniques include deep reactive ion etching or wet etching. It cuts a planar periphery through an entire thickness of the wafer. The etching may also occur simultaneously with etching a fluid via. Dicing techniques include blade, laser or ion beam. It cuts an entire remainder of the periphery connecting the portions already etched to free single chips from the wafer. Edge tolerances, planar shapes, dicing lines, etch patterns, and wafer layout provide still further embodiments.

Abstract: A manufacturing method of a thin film semiconductor substrate includes implanting ions at a specified depth into a semiconductor substrate, forming a bubble layer in the semiconductor substrate by vaporizing the ions through heating, bonding an insulating substrate onto the semiconductor substrate, and cleaving the semiconductor substrate along the bubble layer to form a semiconductor thin film on a side of the insulating substrate. At the forming, the semiconductor substrate is heated at a temperature in a temperature range of approximately 1000° C. to 1200° C. for a duration in a range of approximately 10 ?s to 100 ms. The heating of the semiconductor substrate is performed by using, for example, a light beam.

Abstract: A method for manufacturing a semiconductor device comprises performing a CMP process using an oxide film as an etching barrier film to maintain a polysilicon layer having a large open area. A word line pattern, a DSL pattern, and a SSL pattern that are formed by a first patterning process are not additionally blocked, and the oxide film is used as an etching barrier to obtain an accurate overlay between patterns and improve CD uniformity, thereby improving a characteristic of the device.

Abstract: A method for producing a silicon film-transferred insulator wafer is disclosed. The method includes a surface activation step of performing a surface activation treatment on at least one of a surface of an insulator wafer and a hydrogen ion-implanted surface of a single crystal silicon wafer into which a hydrogen ion has been implanted to form a hydrogen ion-implanted layer; a bonding step that bonds the hydrogen ion-implanted surface to the surface of the insulator wafer to obtain bonded wafers; a first heating step that heats the bonded wafers; a grinding and/or etching step of grinding and/or etching a surface of a single crystal silicon wafer side of the bonded wafers; a second heating step that heats the bonded wafers; and a detachment step to detach the hydrogen ion-implanted layer by applying a mechanical impact to the hydrogen ion-implanted layer of the bonded wafers thus heated at the second temperature.

Abstract: Bypass diodes for solar cells are described. In one embodiment, a bypass diode for a solar cell includes a substrate of the solar cell. A first conductive region is disposed above the substrate, the first conductive region of a first conductivity type. A second conductive region is disposed on the first conductive region, the second conductive region of a second conductivity type opposite the first conductivity type.

Abstract: A method of machining a wafer in which, at the time of grinding the back-side surface of the wafer, only a back-side surface region corresponding to a device formation region where semiconductor chips are formed is thinned by grinding, to form a recessed part on the back side of the wafer. An annular projected part surrounding the recessed part is utilized to secure rigidity of the wafer. Next, the recessed part is etched to cause metallic electrodes to project from the bottom surface of the recessed part, thereby forming a back-side electrode parts, then an insulating film is formed in the recessed part, and the insulating film and end surfaces of the back-side electrode parts are cut.

Abstract: A method for providing a stacked wafer configuration is provided. The method includes bonding a first wafer to a second wafer. A filler material is applied in a gap formed along edges of the first wafer and the second wafer. The filler material provides support along the edges during a thinning and transportation process to help reduce cracking or chipping. The filler material may be cured to reduce any bubbling that may have occurred while applying the filler material. Thereafter, the second wafer may be thinned by grinding, plasma etching, wet etching, or the like. In some embodiments of the present invention, this process may be repeated multiple times to create a stacked wafer configuration having three or more stacked wafers.

Abstract: The present invention relates to a method for manufacturing a light emitting diode (LED) chip for a chip on board and a method for manufacturing an LED light source module in a chip on board fashion. The method of the present invention includes forming a plurality of LED chips on a wafer, molding a region of each LED chip, cutting the wafer into each LED chip, and testing each LED chip for operating characteristics.

Abstract: Starting point regions for cutting 8a, 8b extending along lines to cut 5a, 5b are initially formed in an object to be processed 1. The starting point regions for cutting 8b have modified regions 7b formed by irradiating the object 1 with laser light while locating a converging point within the object 1 and are formed in parts extending along the lines to cut 5b excluding portions 34b intersecting the lines to cut 5a. This makes the starting point regions for cutting 8b much less influential when cutting the object 1 from the starting point regions for cutting 8a acting as a start point, whereby bars with precise cleavage surfaces can reliably be obtained. Therefore, it is unnecessary to form a starting point region for cutting along the lines to cut 5b in each of a plurality of bars, whereby the productivity of semiconductor laser elements can be improved.

Abstract: A method for manufacturing a silicon-on-insulator structure including a substrate wafer, an active wafer, and an oxide layer between the substrate wafer and the active wafer. The method includes the steps of heat treating the structure, trapezoid grinding edges of the wafer, and grinding a surface of the wafer.

Abstract: At least one single crystal substrate, each having a backside surface and made of silicon carbide, and a supporting portion having a main surface and made of silicon carbide, are prepared. In this preparing step, at least one of the backside surface and main surface is formed by machining. By this forming step, a surface layer having distortion in the crystal structure is formed on at least one of the backside surface and main surface. The surface layer is removed at least partially. Following this removing step, the backside surface and main surface are connected to each other.

Abstract: In the fabrication of an integrated circuit, a trench with a sidewall is formed along the periphery of the integrated circuit and the substrate is back-lapped to a thickness smaller than the trench depth to separate the integrated circuit from other integrated circuits on the same substrate. Increased protection against contaminant diffusion into the integrated circuit through the sidewall at the periphery is obtained with one or more protective layers. The substrate area useful for integrated circuit fabrication is also increased.

Abstract: A method of fabricating a semiconductor substrate includes providing a first semiconductor substrate, which includes a detaching layer spaced from an upper surface of the first semiconductor substrate; forming an ion-implanted layer proximate to an edge of the detaching layer; bonding a second semiconductor substrate to the first semiconductor substrate; forming a crack in the ion-implanted layer in response to applying stress to the ion-implanted layer; and detaching a portion of the first semiconductor substrate in response to cleaving through the crack.

Abstract: Objects are to reduce the number of steps in a process for separating a substrate and a semiconductor element, to provide a separation apparatus capable of reducing the number of steps, to suppress manufacturing cost by reducing the number of steps in a separation process, and to improve productivity in manufacturing semiconductor elements. A separation apparatus including a frame body, a porous body having a chamfered, rounded corner portion, a suction unit configured to create suction in the porous body and the frame body, and a jig which includes a unit adopted to press down part of an object to be separated and a unit adopted to lift another part of the object to be separated, and also a separation method and a method for manufacturing a semiconductor element by using the separation apparatus, are provided.

Abstract: The present invention relates to a method of semiconductor wafer back processing, which includes applying a radiation-curable pressure-sensitive adhesive sheet comprising a base film and a pressure-sensitive adhesive layer disposed on one side of the base film to a front side of a semiconductor wafer, the front side of the semiconductor wafer having recesses and protrusions; grinding the back side of the semiconductor wafer in such a state that the radiation-curable pressure-sensitive adhesive sheet is adherent to the front side of the semiconductor; and irradiating the pressure-sensitive adhesive sheet with a radiation to thereby cure the pressure-sensitive adhesive layer, followed by subjecting said ground back side of the semiconductor wafer to a surface treatment; and a radiation-curable pressure-sensitive adhesive sheet for use in the method of semiconductor wafer back processing.

Abstract: The present invention provides a method of manufacturing a semiconductor device in which a thinned substrate of a semiconductor or semiconductor device is handled without cracks in the substrate and treated with heat to improve a contact between semiconductor back surface and metal in a high yield and a semiconductor device may be manufactured in a high yield. In the method of manufacturing a semiconductor device according to the present invention, a notched part is formed from a surface to a middle in a semiconductor substrate by dicing and the surface of the substrate is fixed to a support base. Next, a back surface of the substrate is ground to thin the semiconductor substrate and then a metal electrode and a carbon film that is a heat receiving layer are sequentially formed on the back surface of the substrate. Next, the carbon film is irradiated with light at a power density of 1 kW/cm2 to 1 MW/cm2 for a short time of 0.

Abstract: Methods of forming microelectronic device wafers include fabricating a plurality of semiconductor dies at an active side of a semiconductor wafer, depositing a mask on the semiconductor wafer, removing a central portion of the mask and the semiconductor wafer, and etching. The semiconductor wafer has an outer perimeter edge and a backside that is spaced from the active side by a first thickness. The mask is deposited on the backside of the semiconductor wafer and has a face that is spaced from the backside by a mask thickness. The thinned portion has a thinned surface that is spaced from the active side by a second thickness that is less than the first thickness, and the thinned surface is etched.

Abstract: The present invention provides a method of manufacturing a compound semiconductor device capable of improving yield when a wafer is divided into device regions. The method of manufacturing a compound semiconductor device includes a division step. The division step includes: a first division step of dividing a wafer 30 in a first direction ? to obtain first strip wafers each having at least two rows of device portions 10 arranged in the first direction ?; a second division step of dividing the first strip wafer in a second direction ? to obtain second strip wafers each having a row of the device portions 10 arranged in the second direction ?; and a third division step of dividing the second strip wafer into the device portions 10, thereby forming compound semiconductor devices including the device portions 10.

Abstract: One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined contour is formed in one of a semiconductor membrane and a substrate wafer. The semiconductor membrane is bonded to the substrate wafer and the predetermined contour is straightened to induce a predetermined strain in the semiconductor membrane. In various embodiments, a substrate wafer is flexed into a flexed position, a portion of the substrate wafer is bonded to a semiconductor layer when the substrate wafer is in the flexed position, and the substrate wafer is relaxed to induce a predetermined strain in the semiconductor layer. Other aspects and embodiments are provided herein.

Abstract: A partly finished product of a semiconductor device includes a resin body encapsulating a semiconductor chip, first and second leads extended outwardly from the resin body, a dam bar connected between said first and second leads, and an excess resin portion protruding from the resin body between the first and second leads and the dam bar. The excess resin portion is cut off at two limited portions, and thereby two groove portions are formed in the excess resin portion. An apparatus for cutting the dam bar includes a punch having a cutting edge for cutting connection portions between the first and second leads and the dam bar and for cutting off the two limited portions of the excess resin portion. Since the cut region of the excess resin portion becomes smaller, a stress imparted to the resin body and/or the semiconductor chip through the excess resin portion can be smaller.

Abstract: An object is to suppress discharge due to static electricity generated by peeling, when an element formation layer including a semiconductor element is peeled from a substrate. Over the substrate, the release layer and the element formation layer are formed. The support base material which can be peeled later is fixed to the upper surface of the element formation layer. The element formation layer is transformed through the support base material, and peeling is generated at an interface between the element formation layer and the release layer. Peeling is performed while the liquid is being supplied so that the element formation layer and the release layer which appear sequentially by peeling are wetted with the liquid such as pure water. Electric charge generated on the surfaces of the element formation layer and the release layer can be diffused by the liquid, and discharge by peeling electrification can be eliminated.

Abstract: An object to be processed can be cut highly accurately along a line to cut. An object to be processed 1 is irradiated with laser light while locating a converging point within a silicon wafer 11, and the converging point is relatively moved along a line to cut 5, so as to form modified regions M1, M2 positioned within the object 1 along the line to cut 5, and then a modified region M3 positioned between the modified regions M1, M2 within the object 1.

Abstract: An object is to suppress discharge due to static electricity generated by peeling, when an element formation layer including a semiconductor element is peeled from a substrate. Over the substrate, the release layer and the element formation layer are formed. The support base material which can be peeled later is fixed to the upper surface of the element formation layer. The element formation layer is transformed through the support base material, and peeling is generated at an interface between the element formation layer and the release layer. Peeling is performed while the liquid is being supplied so that the element formation layer and the release layer which appear sequentially by peeling are wetted with the liquid such as pure water. Electric charge generated on the surfaces of the element formation layer and the release layer can be diffused by the liquid, and discharge by peeling electrification can be eliminated.

Abstract: An adhesive layer of which thickness is over 25 ?m and a dicing tape are laminated on a rear surface of a semiconductor wafer. The semiconductor wafer is cut together with a part of the adhesive layer by using a first blade of which cutting depth reaches the adhesive layer. The adhesive layer is cut together with a part of the dicing tape by using a second blade of which cutting depth reaches the dicing tape and of which width is narrower than the first blade. A semiconductor element sectioned by cutting the semiconductor wafer with the adhesive layer is picked up from the dicing tape, and is adhered on another semiconductor element or a circuit board.

Abstract: A frame includes heat slug pads coupled together in a N×M matrix such that singulation of the heat slug pads consists of one or more passes across the frame, wherein the one or more passes are parallel. A method of attaching heat slug pads to packages includes gathering a plurality of packages, preparing a heat slug frame including a N×M matrix of heat slug pads, dispensing thermally conductive material onto surfaces of the heat slug pads, attaching the plurality of packages onto the heat slug pads, and singulating the heat slug pads, wherein the singulating step consists of one or more parallel passes across the N×M matrix. A method of attaching heat slug foil to packages includes preparing a plurality of packages, laminating the heat slug foil to one side of the plurality of packages using thermally conductive material, and singulating the plurality of packages.

Abstract: In a wafer processing method, rough grinding using a first grinding stone is divided into first and second steps. In the first step, a wafer is processed into a concave shape at a first transfer rate with a reinforcing rib area slightly left. Thereafter, as primary rough grinding in the second step, the grinding stone is positioned slightly on the inner circumferential side and the wafer is further processed into the concave portion at a second transfer rate faster than the first transfer rate. Since the first transfer rate is suppressed to a rate not to cause a burst chipping, a burst chipping resulting from the second step fast in the processing rate to ensure productivity will occur at the stepped edge portion on the inside of the reinforcing rib area surface. Thus, the flatness of the reinforcing rib area can be ensured.

Abstract: A process of forming ultra thin wafers having an edge support ring is disclosed. The process provides an edge support ring having an angled inner wall compatible with spin etch processes.

Abstract: A method of fabricating a semiconductor device according to one embodiment includes preparing a wafer having a plurality of chip areas, each chip area to become semiconductor chip, bonding the first side of the wafer to a support substrate through a removable adhesive, dividing the wafer into individually separate semiconductor chips, applying adhesive tape to the second side of the separate semiconductor chips, the second side being opposite to the first side bonded to the support substrate, and the adhesive tape being softer than the support substrate, removing the support substrate from the semiconductor chips, and picking up the separate semiconductor chips that are on the adhesive tape.

Abstract: A technique for positioning a semiconductor chip and a mounting substrate with high precision using an alignment mark. In a semiconductor chip, a mark is formed in an alignment mark formation region over a semiconductor substrate in the same layer as an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. Pattern P1a is formed in the same layer as a second layer wiring, pattern P1b is formed in the same layer as a first layer wiring, pattern P2 is formed in the same layer as a gate electrode, and pattern P3 is formed in the same layer as an element isolation region.

Abstract: A method for thinning a wafer is provided. In one embodiment, a wafer is provided having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of through silicon vias (TSVs), each of the TSVs substantially sealed by a liner layer and a barrier layer. A wafer carrier is provided for attaching to the second side of the wafer. The first side of the wafer is thinned and thereafer recessed to partially expose portions of the liner layers, barrier layers and the TSVs protruding from the wafer. An isolation layer is deposited over the first side of the wafer and the top portions of the liner layers, barrier layers and the TSVs. Thereafter, an insulation layer is deposited over the isolation layer. The insulation layer is then planarized to expose top portions of the TSVs. A dielectric layer is deposited over the planarized first side of the wafer.

Abstract: An optical device wafer processing method for dividing an optical device wafer into a plurality of individual optical devices. The optical device wafer is composed of a substrate and a semiconductor layer formed on the front side of the substrate. The optical devices are partitioned by a plurality of division lines formed on the semiconductor layer. The optical device wafer processing method includes a division start point forming step of applying a laser beam having a transmission wavelength to the substrate along the division lines in the condition where the focal point of the laser beam is set inside the substrate in an area corresponding to the division lines, thereby forming a plurality of modified layers as division start points inside the substrate along the division lines; and a crack growing step of applying a CO2 laser beam along the division lines to grow cracks inside the substrate from the division start points.

Abstract: An optical device wafer processing method for dividing an optical device wafer into a plurality of individual optical devices. The optical device wafer is composed of a substrate and a semiconductor layer formed on the front side of the substrate. The optical devices are partitioned by a plurality of crossing division lines formed on the semiconductor layer.

Abstract: An optical device wafer processing method for dividing an optical device wafer into a plurality of individual optical devices. The optical device wafer is composed of a substrate and a semiconductor layer formed on the front side of the substrate. The optical devices are partitioned by a plurality of crossing division lines formed on the semiconductor layer.

Abstract: A nitride semiconductor substrate has a first surface forming a principal surface of the substrate. A first edge is formed by beveling at least a portion of an edge of the first surface of the substrate. A scattering region is formed in at least a portion of the first edge. The scattering region scatters more external incident light than the first surface.

Abstract: A method of manufacturing dies formed with a dielectric layer is revealed. A liquid dielectric layer is formed on the dicing tape. The liquid dielectric layer is heated to be sticky. Then, a wafer is attached to the dielectric layer on the dicing tape. The wafer is diced into a plurality of dies on the dicing tape. The dies with attached portions of the dielectric layer are picked up to be peeled and separated from the dicing tape. The implementation of the dicing tape can be expanded to resolve various issues such as wafer contaminations, wafer warpage due to multiple heating and mismatching of thermal expansion coefficients, and wafer singulation problems due to alignment difficulties. The wafer handling steps can further be reduced to increase processing yield and to enhance easy and better processing.