Making Grooves, E.g., Cutting (epo) Patents (Class 257/E21.238)
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Patent number: 12191204Abstract: A method of processing a wafer to divide the wafer into individual device chips, includes a second modified layer forming step of applying a laser beam to the wafer while positioning a focused spot of the laser beam inside the wafer along the projected dicing lines extending in a second direction intersecting with a first direction, thereby forming second modified layers in the wafer along the projected dicing lines extending in the second direction. In the second modified layer forming step, when the focused spot of the laser beam along the projected dicing lines extending in the second direction reaches first modified layers, the focused spot of the laser beam is shifted along the first modified layers to thereby undulate the laser beam in a staggered pattern to prevent the second modified layers from being formed straight in the wafer along the projected dicing lines extending in the second direction.Type: GrantFiled: March 31, 2022Date of Patent: January 7, 2025Assignee: DISCO CORPORATIONInventor: Masaru Nakamura
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Patent number: 12138709Abstract: A foreign substance collecting apparatus according to one embodiment of the present disclosure may comprise: a collection body unit formed with a suction port through which air including foreign substances flows in and a discharge port through which air removed of the foreign substances is discharged; and a mixing unit provided inside the collection body unit and disposed on a flow passage of the air, and forming a vortex in washing water contained therein by inducing a rotary flow of the air.Type: GrantFiled: September 18, 2019Date of Patent: November 12, 2024Assignee: POSCO CO., LTDInventors: Seong-Cheol Hong, Ki-Young Min, Se-Min Park, Dong-Geun Kim, Chang-Ho Kim, Jung-Moon Kang, Oho-Cheal Kwon
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Patent number: 11437579Abstract: Disclosed is a method of fabricating a stretchable electronic device, the method including a step of forming one or more semiconductor devices on a first carrier substrate; a step of forming semiconductor device array patterns by separating semiconductor device arrays each including the semiconductor devices; a step of releasing the semiconductor device array patterns from the first carrier substrate; a step of forming a stretchable substrate on a second carrier substrate; and a step of transferring the released semiconductor device array patterns onto the stretchable substrate.Type: GrantFiled: March 22, 2018Date of Patent: September 6, 2022Assignee: UNIVERSITY-INDUSTRY COOPERATION GROUP OF KYUNG HEE UNIVERSITYInventors: Jin Jang, Min Sang Park
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Patent number: 11127633Abstract: A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of cutting the wafer by using a cutting apparatus to thereby divide the wafer into individual device chips, and a pickup step of blowing out air to push up each device chip and picking up each device chip from the polyolefin sheet.Type: GrantFiled: May 22, 2019Date of Patent: September 21, 2021Assignee: DISCO CORPORATIONInventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
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Patent number: 11075117Abstract: Techniques for singulating dies from a respective workpiece and for incorporating one or more singulated die into a stacked device structure are described herein. In some examples, singulating a die from a workpiece includes chemically etching the workpiece in a scribe line. In some examples, singulating a die from a workpiece includes mechanically dicing the workpiece in a scribe line and forming a liner along a sidewall of the die. The die can be incorporated into a stacked device structure. The die can be attached to a substrate along with another die that is attached to the substrate. An encapsulant can be between each die and the substrate and laterally between the dies.Type: GrantFiled: February 26, 2018Date of Patent: July 27, 2021Assignee: Xilinx, Inc.Inventors: Ganesh Hariharan, Raghunandan Chaware, Inderjit Singh
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Patent number: 11037813Abstract: A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of cutting the wafer by using a cutting apparatus to thereby divide the wafer into individual device chips, and a pickup step of cooling the polyolefin sheet, pushing up each device chip through the polyolefin sheet, and then picking up each device chip from the polyolefin sheet.Type: GrantFiled: August 5, 2019Date of Patent: June 15, 2021Assignee: DISCO CORPORATIONInventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
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Patent number: 11018043Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of cutting the wafer by using a cutting apparatus to thereby divide the wafer into individual device chips, and a pickup step of blowing out air to push up each device chip and picking up each device chip from the polyester sheet.Type: GrantFiled: May 22, 2019Date of Patent: May 25, 2021Assignee: DISCO CORPORATIONInventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
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Patent number: 10964595Abstract: A method of packaging an integrated circuit includes forming a first integrated circuit and a second integrated circuit on a wafer, the first and second integrated circuit separated by a singulation region. The method includes covering the first and second integrated circuits with a molding compound, and sawing through the molding compound and a top portion of the wafer using a beveled saw blade, while leaving a bottom portion of the wafer remaining. The method further includes sawing through the bottom portion of the wafer using a second saw blade, the second saw blade having a thickness that is less than a thickness of the beveled saw blade. The resulting structure is within the scope of the present disclosure.Type: GrantFiled: April 22, 2019Date of Patent: March 30, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Ping Wang, Ming-Kai Liu, Kai-Chiang Wu
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Patent number: 10896850Abstract: A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of cutting the wafer by using a cutting apparatus to thereby divide the wafer into individual device chips, and a pickup step of heating the polyolefin sheet, pushing up each device chip through the polyolefin sheet, and then picking up each device chip from the polyolefin sheet.Type: GrantFiled: June 26, 2019Date of Patent: January 19, 2021Assignee: DISCO CORPORATIONInventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
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Patent number: 10847420Abstract: A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of cutting the wafer by using a cutting apparatus to thereby divide the wafer into individual device chips, and a pickup step of picking up each device chip from the polyolefin sheet.Type: GrantFiled: May 1, 2019Date of Patent: November 24, 2020Assignee: DISCO CORPORATIONInventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
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Patent number: 10811363Abstract: Embodiments of semiconductor fabrication methods are disclosed. In an example, a method for forming a mark for locating patterns in semiconductor fabrication is disclosed. A wafer is divided into a plurality of shots. Each of the plurality of shots includes a semiconductor chip die. Four quarters of a locking corner mark are subsequently patterned, respectively, at four corners of four adjacent shots of the plurality of shots. Each quarter of the locking corner mark is symmetric to adjacent quarters of the locking corner mark and is separated from the adjacent quarters of the locking corner mark by a nominally same distance. The locking corner mark is set as an origin for locating patterns in at least one of the four adjacent shots in semiconductor fabrication.Type: GrantFiled: March 15, 2019Date of Patent: October 20, 2020Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Dou Dou Zhang, Jin Yu Qiu, Zhi Yang Song, Jun He, Zhi Hu Gao, Yaobin Feng
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Patent number: 10720360Abstract: An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the first integrated circuit die and the second integrated circuit die. The method further includes forming a kerf in the scribe line region and after forming the kerf, using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die. The kerf extends through a plurality of dielectric layers into a semiconductor substrate.Type: GrantFiled: December 9, 2016Date of Patent: July 21, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fu-Chen Chang, Cheng-Lin Huang, Wen-Ming Chen
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Patent number: 10497621Abstract: The present invention provides a method for dicing a substrate with back metal, the method comprising the following steps. The substrate is provided with a first surface and a second surface wherein the second surface is opposed to the first surface. A mask layer is provided on the first surface of the substrate and a thin film layer is provided on the second surface of the substrate. The first surface of the substrate is diced through the mask layer to expose the thin film layer on the second surface of the substrate. A fluid from a fluid jet is applied to the thin film layer on the second surface of the substrate after the thin film layer has been exposed by the dicing step.Type: GrantFiled: May 6, 2016Date of Patent: December 3, 2019Assignee: Plasma-Therm LLCInventors: Peter Falvo, Linnell Martinez, David Pays-Volard, Rich Gauldin, Russell Westerman
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Patent number: 10424548Abstract: According to one aspect of the present invention, a method of manufacturing a semiconductor device is provided, which includes a bonding step bonding a semiconductor substrate having a semiconductor element disposed on a first surface, to a support substrate, at least through an adhesive layer between the semiconductor substrate and the support substrate, and a groove forming step forming a groove in a scribe area of the semiconductor substrate, from a side of a second surface of the semiconductor substrate, the second surface being opposite to the first surface, and in the groove forming step, a conductive layer between the semiconductor substrate and the support substrate is exposed at a bottom of the groove, without the adhesive layer being exposed in the groove.Type: GrantFiled: September 21, 2017Date of Patent: September 24, 2019Assignee: CANON KABUSHIKI KAISHAInventors: Yuichi Kazue, Takahiro Hachisu, Hidemasa Oshige
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Patent number: 10364510Abstract: There is provided a substrate for crystal growth used for a vapor phase growth of a crystal, wherein a plurality of seed crystal substrates made of a group III nitride crystal are arranged in a disc shape, so that their main surfaces are parallel to each other and adjacent lateral surfaces are in contact with each other; and the plurality of seed crystal substrates constituting at least a portion other than a peripheral portion of the substrate for crystal growth respectively has a main surface whose planar shape is a regular hexagon, and a honeycomb pattern obtained by matching the seed crystal substrates has two or more symmetries, when the substrate for crystal growth is rotated once, with an axis passing through a center of a main surface of the substrate for crystal growth and orthogonal to the main surface as a central axis.Type: GrantFiled: November 25, 2016Date of Patent: July 30, 2019Assignees: SCIOCS COMPANY LIMITED, SUMITOMO CHEMICAL COMPANY, LIMITEDInventor: Tekehiro Yoshida
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Patent number: 10082455Abstract: The present invention related to an apparatus for separating micro-nano scale particles based on microfluidic chromatography using surface acoustic waves, comprising: a piezoelectric substrate; a pair of transducers, which are patterned on the piezoelectric substrate and generate surface acoustic waves when electric energy is applied to the piezoelectric substrate; a microfluidic chip, which is mounted on the piezoelectric substrate and include a microfluidic channel disposed between the pair of transducers, wherein a fluid including micro-nano scale particles flows in the microfluidic channel; and a detection unit, which detects micro-nano scale particles separated by the surface acoustic waves while the micro-nano scale particles pass through the microfluidic channel, wherein forces of the surface acoustic waves generated by the pair of transducers are formed in a direction opposite to a fluid flow to generate flow resistance to the micro-nano scale particles which flows in the microfluidic channel.Type: GrantFiled: December 27, 2013Date of Patent: September 25, 2018Assignee: Korea University Research and Business FoundationInventors: Se Hyun Shin, Jeong Hoon Nam
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Patent number: 9847258Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device from a wafer substrate, the wafer substrate having a top-side surface with a plurality of active device die separated by saw lanes and an opposite under-side surface. The method comprises coating the under-side surface of the wafer substrate with a resilient coating, locating the position of the saw lanes from the underside surface, blade dicing trenches in the resilient material to expose under-side bulk material in the position of saw lanes, and plasma etching through the trenches to remove the exposed under-side bulk material.Type: GrantFiled: September 30, 2015Date of Patent: December 19, 2017Assignee: NXP B.V.Inventors: Thomas Rohleder, Hartmut Buenning, Guido Albermann, Sascha Moeller, Martin Lapke
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Patent number: 9754832Abstract: A semiconductor wafer (100) having a regular pattern of predetermined separation lanes (102) is provided, wherein the predetermined separation lanes (102) are configured in such a way that the semiconductor wafer is singularizable along the regular pattern.Type: GrantFiled: May 17, 2012Date of Patent: September 5, 2017Assignee: NXP B.V.Inventors: Florian Schmitt, Heimo Scheucher, Michael Ziesmann
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Patent number: 9704749Abstract: A method of dividing a wafer, having on one side a device area with a plurality of devices partitioned by a plurality of division lines and a peripheral marginal area with no devices formed around the device area, into dies is provided. The method comprises: attaching an adhesive tape for protecting devices on the wafer to the one side of the wafer, the adhesive tape adhering to at least some, optionally all, of the devices; connecting a carrier for supporting the adhesive tape to the side of the adhesive tape being opposite to the side in contact with the devices by connecting means; grinding that side of the wafer being opposite the one side for adjusting the wafer height; and cutting the wafer along the division lines. The method is characterized by locating the connecting means completely outward of the device area of the wafer in a top view thereon.Type: GrantFiled: December 16, 2015Date of Patent: July 11, 2017Assignee: DISCO CORPORATIONInventor: Karl Heinz Priewasser
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Patent number: 9653417Abstract: A method of packaging an integrated circuit includes forming a first integrated circuit and a second integrated circuit on a wafer, the first and second integrated circuit separated by a singulation region. The method includes covering the first and second integrated circuits with a molding compound, and sawing through the molding compound and a top portion of the wafer using a beveled saw blade, while leaving a bottom portion of the wafer remaining. The method further includes sawing through the bottom portion of the wafer using a second saw blade, the second saw blade having a thickness that is less than a thickness of the beveled saw blade. The resulting structure is within the scope of the present disclosure.Type: GrantFiled: November 7, 2013Date of Patent: May 16, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Ping Wang, Ming-Kai Liu, Kai-Chiang Wu
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Patent number: 9564366Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.Type: GrantFiled: December 18, 2015Date of Patent: February 7, 2017Assignee: Plasma-Therm LLCInventors: Linnell Martinez, David Pays-Volard, Chris Johnson, David Johnson, Russell Westerman, Gordon M. Grivna
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Patent number: 9416041Abstract: A method for cutting a substrate of irregular pattern includes: forming a cutting line on the substrate, wherein the closed region enclosed by the cutting line is the irregular pattern that is required; forming a trough line at the cutting line; and applying an external force to the substrate so as to divide the substrate at the trough line. The method can remarkably improve accuracy and efficiency of cutting a substrate of irregular pattern.Type: GrantFiled: October 15, 2013Date of Patent: August 16, 2016Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Liyuan Jiang, Yaokun Zheng, Lianjie Qu, Yajie Wang, Yanqi Jiang
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Patent number: 9040389Abstract: In one embodiment, a method of forming a semiconductor device comprises forming a groove on and/or over a first side of a substrate. A dicing layer is formed from a second side of the substrate using a laser process. The second side is opposite the first side. The dicing layer is disposed under the groove within the substrate. The substrate is singulated through the dicing layer.Type: GrantFiled: October 9, 2012Date of Patent: May 26, 2015Assignee: Infineon Technologies AGInventors: Gunther Mackh, Maria Heidenblut, Adolf Koller, Anatoly Sotnikov
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Patent number: 9034733Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and separating portions of the backmetal layer within the singulation lines using a pressurized fluid applied to the carrier tape.Type: GrantFiled: January 21, 2014Date of Patent: May 19, 2015Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: William F. Burghout, Dennis Lee Conner, Michael J. Seddon, Jay A. Yoder, Gordon M. Grivna
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Patent number: 8999818Abstract: A semiconductor element is formed on a first surface of the substrate. A resin layer is formed over a second surface of the substrate which is opposite to the first surface of the substrate and on a part of the side surface of the substrate. A step is formed on the side surface of the substrate. The width of the upper section of the substrate with a step is narrower than the lower section of the substrate with a step. Therefore, the substrate can also be a protrusion.Type: GrantFiled: December 23, 2008Date of Patent: April 7, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hidekazu Takahashi, Daiki Yamada, Yohei Monma, Hiroki Adachi, Shunpei Yamazaki
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Patent number: 8962452Abstract: In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer.Type: GrantFiled: December 2, 2013Date of Patent: February 24, 2015Assignee: Semiconductor Components Industries, LLCInventor: Gordon M. Grivna
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Patent number: 8962363Abstract: Provided is a novel method for forming a groove composed of two smooth inclined surfaces on a surface of a flat plate formed of a nitride semiconductor crystal having an A, C, M-axes. In the present invention, a disk-shaped dicing blade is moved along a direction of the A-axis to form first and second inclined surfaces on the surface of the flat plate. The following mathematical formulae (I)-(III) are satisfied: 45 degrees??b?a?60 degrees (I) 45 degrees??b+a?60 degrees (II), 0 degrees?|a|?7.5 degrees, where angle ?b represents an angle formed between a surface of the edge and a radial direction of the dicing blade in a cross-sectional view which includes the M-axis and the C-axis. The angle a represents an angle formed between the principal surface and the M-axis.Type: GrantFiled: June 6, 2014Date of Patent: February 24, 2015Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Akira Inoue, Toshiyuki Fujita, Toshiya Yokogawa
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Patent number: 8951833Abstract: A method for forming large substantially defect-free void areas on a semiconductor integrated circuit chip includes processing the chip through the passivation level processing operations then forming one or more openings in a designated blank area of the integrated circuit chip in a separate dedicated etching operation. The one or more openings may constitute 5-10% or more of the total area of the semiconductor chip. The void areas are deep trench openings that extend through the passivation layer and through all of the other material layers in the blank area exposing the substrate surface in one embodiment and through all material layers except for a field oxide layer formed directly on the substrate in another embodiment.Type: GrantFiled: June 17, 2011Date of Patent: February 10, 2015Assignee: WaferTech, LLCInventor: Kun-Yi Liu
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Patent number: 8951815Abstract: A method for producing a liquid-discharge-head substrate includes a step of preparing a silicon substrate including, at a front-surface side of the silicon substrate, an energy generating element; a step of forming a first etchant introduction hole on the front-surface side of the silicon substrate; a step of supplying a first etchant into the first etchant introduction hole formed on the front-surface side of the silicon substrate, and supplying a second etchant to a back-surface side of the silicon substrate; a step of stopping the supply of the second etchant; and a step of, after the supply of the second etchant has been stopped, forming a liquid supply port extending through front and back surfaces of the silicon substrate by the supply of the first etchant.Type: GrantFiled: June 19, 2012Date of Patent: February 10, 2015Assignee: Canon Kabushiki KaishaInventors: Ryotaro Murakami, Shuji Koyama, Keisuke Kishimoto, Kenta Furusawa
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Patent number: 8865568Abstract: Fractures (17a, 17b) are generated from modified regions (7a, 7b) to front and rear faces (12a, 12b) of a object to be processed (1), respectively, while an unmodified region (2) is interposed between the modified regions (7a, 7b). This can prevent fractures from continuously advancing in the thickness direction of a silicon substrate (12) when forming a plurality of rows of modified regions (7). By generating a stress in the object (1), the fractures (17a, 17b) are connected to each other in the unmodified region (2), so as to cut the object (1). This can prevent fractures from meandering in the rear face (12b) of the object (1) and so forth, whereby the object (1) can be cut accurately along a line to cut the object (5).Type: GrantFiled: April 18, 2014Date of Patent: October 21, 2014Assignee: Hamamatsu Photonics K.KInventors: Takeshi Sakamoto, Aiko Nakagawa
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Patent number: 8865569Abstract: A method and apparatus for dividing a thin film device having a first layer which is a lower electrode layer, a second layer which is an active layer and a third layer which is an upper electrode layer, the layers each being continuous over the device, into separate cells which are electrically interconnected in series.Type: GrantFiled: July 15, 2011Date of Patent: October 21, 2014Assignee: M-Solv Ltd.Inventor: Adam North Brunton
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Patent number: 8790995Abstract: According to one embodiment, a substrate processing method is disclosed. The above method includes: grinding an outer edge portion on a back surface of a semiconductor wafer with a semiconductor element formed on its front surface with a first grindstone or blade to thereby form an annular groove; grinding a projecting portion on an inner side of the groove with a second grindstone to thereby form a recessed portion integrally with the groove on the back surface of the semiconductor wafer; and grinding a bottom surface of the recessed portion including a ground surface made by the second grindstone with a third grindstone.Type: GrantFiled: March 16, 2012Date of Patent: July 29, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Shinya Takyu, Noriko Shimizu, Tsutomu Fujita
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Patent number: 8790996Abstract: Methods of processing a device substrate are disclosed herein. In one embodiment, a method of processing a device substrate can include bonding a first surface of a device substrate to a carrier with a polymeric material. The device substrate may have a plurality of first openings extending from the first surface towards a second surface of the device substrate opposite from the first surface. Then, material can be removed at the second surface of the device substrate, wherein at least some of the first openings communicate with the second surface at least one of before or after performing the removal of the material. Then, at least a portion of the polymeric material disposed between the first surface and the carrier substrate can be exposed to a substance through at least some first openings to debond the device substrate from the carrier substrate.Type: GrantFiled: July 16, 2012Date of Patent: July 29, 2014Assignee: Invensas CorporationInventor: Pezhman Monadgemi
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Patent number: 8778719Abstract: The linear semiconductor substrate 1 or 2 of the present invention comprises at least one desired thin film 4 formed on a linear substrate 3 having a length ten or more times greater than a width, thickness, or diameter of the linear substrate itself. Adopting semiconductor as the thin film 4 forms a linear semiconductor thin film. The linear semiconductor substrate 1 or 2 of the present invention is produced by utilizing a fiber-drawing technique which is a fabricating technique of optical fibers.Type: GrantFiled: September 6, 2011Date of Patent: July 15, 2014Assignee: Furukawa Electric Co., Ltd.Inventors: Toshihiro Nakamura, Nobuaki Orita, Hisashi Koaizawa, Kenkichi Suzuki, Hiroshi Kuraseko, Michio Kondo
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Patent number: 8772168Abstract: Gate to contact shorts are reduced by forming dielectric caps in replaced gate structures. Embodiments include forming a replaced gate structure on a substrate, the replaced gate structure including an ILD having a cavity, a first metal on a top surface of the ILD and lining the cavity, and a second metal on the first metal and filling the cavity, planarizing the first and second metals, forming an oxide on the second metal, removing the oxide, recessing the first and second metals in the cavity, forming a recess, and filling the recess with a dielectric material. Embodiments further include dielectric caps having vertical sidewalls, a trapezoidal shape, a T-shape, or a Y-shape.Type: GrantFiled: January 19, 2012Date of Patent: July 8, 2014Assignee: GlobalFoundries Singapore Pte. Ltd.Inventors: Ruilong Xie, Balasubramanian Pranatharthi Haran, David V. Horak, Su Chen Fan
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Patent number: 8728916Abstract: A method for manufacturing a semiconductor element of the present invention, has: a laser irradiation step of focusing a pulsed laser beam inside of a substrate constituting a wafer, thereby forming a plurality of isolated processed portions along an intended dividing line inside of the substrate, and creating a fissure that runs from the processed portions at least to the surface of the substrate and links adjacent processed portions; and a wafer division step of dividing the wafer along the intended dividing line.Type: GrantFiled: February 4, 2010Date of Patent: May 20, 2014Assignee: Nichia CorporationInventor: Hiroaki Tamemoto
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Patent number: 8728914Abstract: Fractures (17a, 17b) are generated from modified regions (7a, 7b) to front and rear faces (12a, 12b) of a object to be processed (1), respectively, while an unmodified region (2) is interposed between the modified regions (7a, 7b). This can prevent fractures from continuously advancing in the thickness direction of a silicon substrate (12) when forming a plurality of rows of modified regions (7). By generating a stress in the object (1), the fractures (17a, 17b) are connected to each other in the unmodified region (2), so as to cut the object (1). This can prevent fractures from meandering in the rear face (12b) of the object (1) and so forth, whereby the object (1) can be cut accurately along a line to cut the object (5).Type: GrantFiled: January 27, 2010Date of Patent: May 20, 2014Assignee: Hamamatsu Photonics K.K.Inventors: Takeshi Sakamoto, Aiko Nakagawa
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Patent number: 8709916Abstract: A laser processing method is disclosed, comprising the steps of: directing a laser beam to a workpiece; and effecting a relative motion between the laser beam and the workpiece. In particular, the step of directing the laser beam to the workpiece comprises focusing the laser beam within the workpiece until an internal damage forms within the workpiece and a crack propagates from the internal damage to at least one surface of the workpiece to form a surface crack on the workpiece. Further, the step of effecting the relative motion between the laser beam and the workpiece is such that the surface crack on the workpiece propagates along a line of separation on the workpiece. A laser processing apparatus is also disclosed.Type: GrantFiled: July 5, 2012Date of Patent: April 29, 2014Assignee: ASM Technology Singapore Pte LtdInventors: Chi Hang Kwok, Chi Wah Cheng, Lap Kei Chow
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Patent number: 8697475Abstract: A solar cell and a method for manufacturing the same are disclosed. The solar cell may include a substrate, an emitter layer positioned at a first surface of the substrate, a first anti-reflection layer that is positioned on a surface of the emitter layer and may include a plurality of first contact lines exposing a portion of the emitter layer, a first electrode that is electrically connected to the emitter layer exposed through the plurality of first contact lines and may include a plating layer directly contacting the emitter layer, and a second electrode positioned on a second surface of the substrate.Type: GrantFiled: October 28, 2010Date of Patent: April 15, 2014Assignee: LG Electronics Inc.Inventors: Goohwan Shim, Changseo Park, Philwon Yoon, Yoonsil Jin, Jinsung Kim, Youngho Choe, Jaewon Chang
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Patent number: 8698161Abstract: A semiconductor structure is bonded directly to a diamond substrate by Van der Waal forces. The diamond substrate is formed by polishing a surface of diamond to a first degree of smoothness; forming a material, such as diamond, BeO, GaN, MgO, or SiO2 or other oxides, over the polished surface to provide an intermediate structure; and re-polishing the material formed on the intermediate structure to a second degree of smoothness smoother than the first degree of smoothness. The diamond is bonded to the semiconductor structure, such as GaN, by providing a structure having bottom surfaces of a semiconductor on an underlying material; forming grooves through the semiconductor and into the underlying material; separating semiconductor along the grooves into a plurality of separate semiconductor structures; removing the separated semiconductor structures from the underlying material; and contacting the bottom surface of at least one of the separated semiconductor structures to the diamond substrate.Type: GrantFiled: December 17, 2010Date of Patent: April 15, 2014Assignee: Raytheon CompanyInventors: Ralph Korenstein, Mary K. Herndon, Chae Doek Lee
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Patent number: 8673742Abstract: A method for manufacturing a semiconductor device includes forming a starting-point crack on a cleavage line on a surface of a semiconductor substrate; forming preliminary cracks intermittently along the cleavage line on the surface of the semiconductor substrate; and cleaving the semiconductor substrate along the cleavage line passing through the preliminary cracks, from the starting-point crack, wherein each of the preliminary cracks has a crack joining the cleavage line from outside of the cleavage line, in a direction of a progress of cleaving.Type: GrantFiled: August 17, 2012Date of Patent: March 18, 2014Assignee: Mitsubishi Electric CorporationInventors: Katsumi Ono, Masato Negishi, Masato Suzuki
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Patent number: 8669190Abstract: In a method for manufacturing a semiconductor device, a process of providing a semiconductor wafer having a wiring layer having conductive patterns and a plurality of insulation films containing a first insulation film surrounding side surfaces of the conductive patterns are provided. After the process of providing the semiconductor wafer, a process of removing some regions of the plurality of insulation films to form openings is provided. Herein, the first insulation film is disposed to a position closer to the circumference of the semiconductor wafer than a position closest to the outermost circumference of the wafer among the arrangement positions of the conductive patterns.Type: GrantFiled: February 6, 2012Date of Patent: March 11, 2014Assignee: Canon Kabushiki KaishaInventors: Kenji Togo, Hiroaki Sano
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Patent number: 8664089Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and fluid machining the semiconductor wafer to remove the backmetal layer from the singulation lines.Type: GrantFiled: August 20, 2012Date of Patent: March 4, 2014Assignee: Semiconductor Components Industries, LLCInventors: William F. Burghout, Dennis Lee Conner, Michael J. Seddon, Jay A. Yoder
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Patent number: 8563343Abstract: A method of manufacturing a laser diode device includes: forming, in a semiconductor laser bar, separation trenches extending across all of a transverse dimension of the semiconductor laser bar and defining a mesa stripe, each of the separation trenches having wide portions located at longitudinal edge portions of the semiconductor laser bar and a narrow portion located in a longitudinal central portion of the semiconductor laser bar; scribing, in the semiconductor laser bar, grooves extending parallel to the separation trenches and terminating before reaching longitudinal edge portions of the semiconductor laser bar; and splitting the semiconductor laser bar along the grooves to form cleaved surfaces extending from a bottom surface of the semiconductor laser bar to bottom surfaces of the separation trenches.Type: GrantFiled: May 17, 2012Date of Patent: October 22, 2013Assignee: Mitsubishi Electric CorporationInventor: Takashi Motoda
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Patent number: 8536025Abstract: A resized wafer using a negative photoresist ring, methods of manufacture and design structures thereof are disclosed. The method includes forming a ring within a radius of a wafer. The method also includes patterning a photoresist formed on the wafer, by exposing the photoresist to energy. Additionally, the method includes forming troughs in a substrate of the wafer based on the patterning of the photoresist, wherein the ring blocks formation of the troughs underneath the ring. The method also includes filling the troughs with a metal and resizing the wafer at an area of the ring.Type: GrantFiled: December 12, 2011Date of Patent: September 17, 2013Assignee: International Business Machines CorporationInventors: Dennis P. Hogan, Gregory S. Jankowski, Robert K. Leidy
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Patent number: 8518804Abstract: A semiconductor device manufacturing method and manufacturing apparatus with which it is possible, when a wafer has a warp, to effectively peel off an ultraviolet peelable tape with ultraviolet irradiation of a short duration. Even when a wafer has a warp, by correcting the warp of the wafer with an ultraviolet transmitting plate, and uniformly irradiating an ultraviolet peelable tape attached to the wafer with ultraviolet light, it is possible to reduce a distance between an ultraviolet light source and the ultraviolet peelable tape. Also, by blocking heat from the ultraviolet light source with the ultraviolet transmitting plate, it is possible to suppress a rise in temperature of the wafer. As a result of this, it is possible to effectively peel the ultraviolet peelable tape from the wafer with ultraviolet irradiation of a short duration without any adhesive residue remaining.Type: GrantFiled: October 20, 2011Date of Patent: August 27, 2013Assignee: Fuji Electric Co., Ltd.Inventor: Yuichi Urano
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Patent number: 8492255Abstract: A Schottky diode with a small footprint and a high-current carrying ability is fabricated by forming an opening that extends into an n-type semiconductor material. The opening is then lined with a metallic material such as platinum. The metallic material is then heated to form a salicide region where the metallic material touches the n-type semiconductor material.Type: GrantFiled: January 6, 2011Date of Patent: July 23, 2013Assignee: National Semiconductor CorporationInventors: Sheldon D. Haynie, Ann Gabrys
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Patent number: 8431440Abstract: A substrate table used for manufacturing a chip is provided. The substrate table includes a substrate stage, a substrate placement surface formed on the substrate stage, and on which a substrate is placed, and a guiding member that can project and retract from the substrate placement surface. The guiding member positions the substrate when the guiding member is at a projected position abutting an edge portion of the substrate placed on the substrate placement surface, and the guiding member retracts at a time of applying a tape to the substrate.Type: GrantFiled: June 16, 2010Date of Patent: April 30, 2013Assignee: Lapis Semiconductor Co., Ltd.Inventor: Hiromi Morita
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Patent number: 8420418Abstract: A method of fabricating a light emitting device comprising: providing a substrate, wherein the substrate comprises a first major surface and a second major surface opposite to the first major surface, forming a plurality of light emitting stack layers on the first major surface, forming an etching protection layer on the plurality of light emitting stack layers, forming a plurality of discontinuous holes or continuous lines on the substrate by a laser beam with the depth of 10˜150 ?m, cleaving the substrate through the plurality of discontinuous holes or continuous lines, providing a adhesion layer on the second major surface of the substrate, and expanding the adhesion layer to form a plurality of separated light emitting device.Type: GrantFiled: June 28, 2010Date of Patent: April 16, 2013Assignee: Epistar CorporationInventor: Tzu-Chieh Hsu
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Patent number: 8404566Abstract: Provided are a light emitting diode and a method for manufacturing the same. In the method, a semiconductor layer is formed, and a mask layer is formed on the semiconductor layer. Laser is irradiated onto a scribing region of the mask layer to divide the semiconductor layer into a plurality of light emitting diodes. The scribing region is etched, and then the mask layer is removed. The plurality of light emitting diodes are then separated from each other.Type: GrantFiled: September 20, 2007Date of Patent: March 26, 2013Assignee: LG Innotek Co., Ltd.Inventor: Sang Youl Lee