Abstract: A method of dividing an optical device wafer includes: a laser beam processing step of performing laser beam processing to provide an optical device wafer with breakage starting points along streets on the face side of the optical device wafer; a protective plate bonding step of bonding the face side of the optical device wafer to a surface of a highly rigid protective plate with a bonding agent permitting peeling; a back side grinding step of grinding the back side of the optical device wafer so as to form the optical device wafer to a finished thickness of the optical devices; a wafer supporting step of adhering the back-side surface of the optical device wafer to a surface of a dicing tape, and peeling the protective plate adhered to the face side of the optical device wafer; and a wafer dividing step of exerting an external force on the optical device wafer so as to break up the optical device wafer along the streets along which the breakage starting points have been formed, thereby dividing the optical d

Abstract: A composition and associated method for the chemical mechanical planarization (CMP) of metal substrates on semiconductor wafers are described. The composition contains a nonionic fluorocarbon surfactant and a per-type oxidizer (e.g., hydrogen peroxide). The composition and associated method are effective in controlling removal rates of low-k films during copper CMP and provide for tune-ability in removal rates of low-k films in relation to removal rates of copper, tantalum, and oxide films.

Abstract: A chip structure according to the present invention is provided. A plurality of pedestals extends from the back surface of the chip structure. Each of the pedestals is located at a position away from the edge of the back surface for a non-zero distance so that the pedestals of an upper chip structure will not damage the bonding pads positioned on the edge of the active surface of a lower chip structure when the upper chip structure is stacked on the active surface of the lower chip structure with the pedestals.

Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.

Abstract: A method for obtaining individual dies from a semiconductor structure is disclosed. The semiconductor structure includes a device layer, and the device layer in turn includes active regions separated by predefined spacings. Thick metal is selectively formed on backside of the device layer such that thick metal is formed on backside of active regions but not on backside of the predefined spacings. The semiconductor structure is then cut along the predefined spacings to separate the active regions with thick metal on their backside into individual dies.

Abstract: A method and apparatus involve providing a substrate having a dielectric layer formed thereon, forming a photoresist mask over the dielectric layer, the photoresist mask defining an opening, etching the dielectric layer through the at least one opening in the photoresist mask, treating a portion of the photoresist mask with an etching species, and removing the treated photoresist mask with a supercritical fluid. The etching, treating, and removing can be performed in one chamber.

Abstract: The present invention provides a structure combining an IC integrated substrate and a carrier, which comprises a carrier and an IC integrated substrate formed on the carrier. The IC integrated substrate has a first dielectric layer attached to the carrier. The materials of the carrier and the first dielectric layer are selected to prevent the IC integrated substrate from peeling off the carrier during processing and to allow the IC integrated substrate to naturally separate from the carrier after being cut, through the adhesion between the carrier and the first dielectric layer. The present invention also provides a method of manufacturing the above structure and a method of manufacturing electrical devices using the above structure.

Abstract: A method for producing a semiconductor structure and a semiconductor component are described.

Abstract: Even for the case where a CVD oxide film is interposed at a bonding interface, as a pre-processing of bonding a first wafer and a second wafer, at least the surface roughness of the CVD oxide film of the first wafer is made small after removing organic substances. Therefore, it is possible to prevent void occurrence which is caused by the organic substances existing at and the roughness of the bonding interface of the two wafers.

Abstract: The invention provides a method of trimming a structure that includes a first wafer bonded to a second wafer, with the first wafer having a chamfered edge. The method includes a first trimming step carried out over a first depth that includes at least the thickness of the first wafer and over a first width determined from the edge of the first wafer. A second trimming step is then carried out over a second depth that includes at least the thickness of the first wafer and over a second width that is less than the first width.

Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).

Abstract: A device fabrication method for fabricating individual devices from a wafer, wherein the back side of each device is covered with an adhesive film for die bonding. The device fabrication method includes a wafer dividing step of dividing the wafer into the individual devices along a plurality of kerfs by using a dicing before grinding process, an adhesive film mounting step of mounting an adhesive film on the back side of the wafer after performing the wafer dividing step, and an adhesive film dividing step of applying a laser beam to the adhesive film along the kerfs after performing the adhesive film mounting step, thereby dividing the adhesive film along the kerfs.

Abstract: A wafer dividing method for dividing a wafer having a film on the front side thereof.

Abstract: An object to be processed can be cut highly accurately along a line to cut. An object to be processed 1 is irradiated with laser light while locating a converging point within a silicon wafer 11, and the converging point is relatively moved along a line to cut 5, so as to form modified regions M1, M2 positioned within the object 1 along the line to cut 5, and then a modified region M3 positioned between the modified regions M1, M2 within the object 1.

Abstract: A polished semiconductor wafer of high flatness is produced by the following ordered steps: slicing a semiconductor wafer from a rod composed of semiconductor material, material-removal processing of at least one side of the semiconductor wafer, and polishing of at least one side of the semiconductor wafer, wherein the semiconductor wafer has, after the material-removing processing and before the polishing on at least one side to be polished, along its margin, a ring-shaped local elevation having a maximum height of at least 0.1 ?m, wherein the local elevation reaches its maximum height within a 10 mm wide ring lying at the edge of the semiconductor wafer.

Abstract: A dividing method for a platelike workpiece having a two-layer structure such that a solder layer (metal layer) is formed on the back side of a wafer (substrate). First, a modified layer is formed in the wafer along each division line formed on the front side of the wafer. Thereafter, the workpiece is bent along each division line to thereby divide the wafer along each division line from the corresponding modified layer as a starting point and simultaneously form a weak portion in the solder layer along each division line. Thereafter, an expandion tape attached to the solder layer is expanded to apply an external force to the solder layer, thereby dividing the solder layer along each division line from the corresponding weak portion as a starting point. Thus, the workpiece is completely divided.

Abstract: A process for producing electrical contact connections for a component integrated in a substrate material is provided, the substrate material having a first surface region, and at least one terminal contact being arranged at least partially in the first surface region for each component, which is distinguished in particular by application of a covering to the first surface region and production of at least one contact passage which, in the substrate material, runs transversely with respect to the first surface region, in which process, in order to form at least one contact location in a second surface region which is to be provided, at least one electrical contact connection from the contact location to at least one of the terminal contacts is produced via the respective contact passages.

Abstract: A backgrinding machine 10 of a semiconductor wafer W includes: a table 13 set on the working plane of a mount 11; a multiple number of holding jigs 20 arranged via check tables 15 on table 13; a grinding machine 30 for performing a grinding process of the rear side of semiconductor wafer W held by holding jig 20; and a washing device 40 for ground semiconductor wafers W. Each holding jig 20 is constructed of a concave 22 depressed on the surface of a base plate 21, a multiple number of supporting projections 23 projectively arrayed on the bottom surface of concave 22, a deformable contact film 24, covering the concave 22, being supported by the multiple supporting projections 23, for detachably holding semiconductor wafer W in close contact with it; and an exhaust path 25 for conducting air from the concave 22 covered by contact film 24 to the outside.

Abstract: [PROBLEM] Provided is a method for producing an SOI wafer which the method can prevent occurrence of thermal strain, detachment, crack and the like attributed to a difference in thermal expansion coefficients between the insulating substrate and the SOI layer and also improve the uniformity of film thickness of the SOI layer.

Abstract: A rubbing system for an alignment layer of a liquid crystal display (LCD) device, comprises: a rubbing table on which a substrate having an alignment layer thereon is positioned; a rubbing roll on which a rubbing material is wound, substantially positioned on the rubbing table thus to substantially contact the alignment layer, for rubbing the alignment layer by rotation of the rubbing roll; and a controlling unit for controlling the alignment layer to be rubbed by substantially contacting the rubbing roll onto the alignment layer by simultaneously lifting and lowering a rubbing table and the rubbing roll according to an alignment controlling force to be applied to the alignment layer.

Abstract: A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide granules, grinding and polishing a top surface of the wafer, etching the top surface for eliminating a top process-induced degradation layer and maintaining a 0.5 ?m-10 ?m thick edge process-induced degradation layer.

Abstract: A method for dividing a semiconductor substrate involves providing a semiconductor substrate. At least one separating trench is produced at a front side of the semiconductor substrate. A layer is produced at least at the bottom of the at least one separating trench. The semiconductor substrate is thinned at a rear side of the semiconductor substrate at least as far as the layer at the bottom of the at least one separating trench. The layer is severed in order to divide the semiconductor substrate into individual pieces.

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor wafer including a plurality of interconnect layers, the semiconductor wafer including: a plurality of chip-composing portions; a dicing region separating the chip-composing portions from each other; and a plurality of inter-chip interconnects formed in the dicing region and electrically connecting adjacent ones of the chip-composing portions; and forming semiconductor chips by dicing the dicing region so as to divide the chip-composing portions, wherein each of the inter-chip interconnects has a width of an intermediate portion narrower than widths of connection end portions connected to the adjacent ones of the chip-composing portions.

Abstract: An embedded semiconductor die package is made by mounting a frame carrier to a temporary carrier with an adhesive. The frame carrier includes die mounting sites each having a lead frame interconnect structure around a cavity. A semiconductor die is disposed in each cavity. An encapsulant is deposited in the cavity over the die. A package interconnect structure is formed over the lead frame interconnect structure and encapsulant. The package interconnect structure and lead frame interconnect structure are electrically connected to the die. The frame carrier is singulated into individual embedded die packages. The semiconductor die can be vertically stacked or placed side-by-side within the cavity. The embedded die packages can be stacked and electrically interconnected through the lead frame interconnect structure. A semiconductor device can be mounted to the embedded die package and electrically connected to the die through the lead frame interconnect structure.

Abstract: A scribe line structure is disclosed. The scribe line structure includes a semiconductor substrate having a die region, a die seal ring region, disposed outside the die region, a scribe line region disposed outside the die seal ring region and a dicing path formed on the scribe line region. Preferably, the center line of the dicing path is shifted away from the center line of the scribe line region along a first direction.

Abstract: A method for fabricating ICs including via-first through substrate vias (TSVs) and ICs and electronic assemblies therefrom. A substrate having a substrate thickness including a top semiconductor surface and a bottom surface is provided including at least one embedded TSV including a dielectric liner and an electrically conductive filler material formed on the dielectric liner. A portion of the bottom surface of the substrate is mechanically removed to approach but not reach the embedded TSV tip. A protective substrate layer having a protective layer thickness remains over the tip of the embedded TSV after the mechanical removing. Chemical etching exclusive of mechanical etching for removing the protective substrate layer is used form an integral TSV tip that has an exposed tip portion that generally protrudes from the bottom surface of the substrate. The chemical etching is generally a three step chemical etch.

Abstract: A method for the separation of multiple dies during semiconductor fabrication is described. On an upper surface of a semiconductor wafer containing multiple dies, a seed metal layer may be used to grow hard metal layers above it for handling. Metal may be plated above these metal layers everywhere except where a block of stop electroplating (EP) material exists. The stop EP material may be obliterated, and a barrier layer may be formed above the entire remaining structure. The substrate may be removed, and the individual dies may have any desired bonding pads and/or patterned circuitry added to the semiconductor surface. The remerged hard metal after laser cutting and heating should be strong enough for handling. Tape may be added to the wafer, and a breaker may be used to break the dies apart. The resulting structure may be flipped over, and the tape may be expanded to separate the individual dies.

Abstract: A method includes a step of forming a bump 104 having a projection 104B on an electrode pad 103 provided on a semiconductor chip 101, a step of exposing a part of the projection 104B to an upper surface of an insulating layer 105 formed on the semiconductor chip 101, a step of forming a conductive layer 107A on the upper surface of the insulating layer 105 and an exposed part of a tip portion 104D, a step of removing a protruded portion of the conductive layer 107A which is opposed to the tip portion 104D by means of a grinding roll 112, thereby exposing the projection from the conductive layer 107A, and a step of forming a conductive layer 108A through electrolytic plating using the conductive layer 107A as a feeding layer and patterning the conductive layer 108A.

Abstract: A method for singulating dies from a wafer includes laser scribing a continuous line on each side of the die, and laser ablating an area adjacent the laser scribed continuous line on each side of the die. The laser ablations in the area adjacent the laser scribed continuous line on each side of the die being spaced from one another. The method also includes sawing the laser abated area adjacent the continuous line. A method for singulating dies from a wafer includes laser scribing a first continuous line, laser scribing a second continuous line spaced apart from the first continuous line, and laser scribing a third continuous line. The third continuous line positioned between the first continuous line and the second continuous line. The third continuous line overlaps the second continuous line and the third continuous line.

Abstract: Some embodiments include methods in which a front side region of a semiconductor substrate is placed against a surface. While the front side region is against the surface, the semiconductor substrate is thinned, and then cut into a plurality of dice. The surface may be a pliable material, and may be stretched after the cutting to increase separation between at least some of the dice. While the pliable surface is stretched, at least some of the dice may be picked from the surface. In some embodiments, the semiconductor substrate is retained to the surface with a radiation-curable material. The material is in an uncured and tacky form during the thinning of the substrate, and is subsequently cured into a less tacky form prior to the picking of dice from the surface.

Abstract: A donor wafer, for example of silicon, has an irregular surface following cleaving of a lamina from the surface, for example by exfoliation following implant of hydrogen and/or helium ions to define a cleave plane. Pinholes in the lamina leave column asperities at the exfoliated surface of the donor wafer, and the beveled edge may leave an edge asperity which fails to exfoliate. To prepare the surface of the donor wafer for reuse, mechanical grinding removes the column and edge asperities, and minimal additional thickness. Following cleaning, growth and removal of an oxide layer at the surface rounds remaining peaks. The smoothed surface is well adapted to bonding to a receiver element and exfoliation of a new lamina. A variety of devices may be fabricated from the lamina, for example a photovoltaic cell.

Abstract: An object is to provide a method for manufacturing a semiconductor device which suppresses an influence on a semiconductor element due to entry of an impurity element, moisture, or the like from outside even in the case of thinning or removing a substrate after forming a semiconductor element over the substrate. A feature is to form an insulating film functioning as a protective film on at least one side of the substrate by performing surface treatment on the substrate, to form a semiconductor element such as a thin film transistor over the insulating film, and to thin the substrate. As the surface treatment, addition of an impurity element or plasma treatment is performed on the substrate. As a means for thinning the substrate, the substrate can be partially removed by performing grinding treatment, polishing treatment, or the like on the other side of the substrate.

Abstract: The present invention provides a water and a method for strengthening, homogenization and construction thereof. The concave and convex portions are processed by laser or etching, and then formed at intervals on the grinding surface of the wafer. The concave and convex portions are round or polygonal shapes. With the alternated arrangement of the concave and convex portions, a mesh structure of consistent construction is formed on the grinding surface of the wafer, making it possible to cut down greatly the interference and influence generated by the texture of grinding surface, and improve substantially the structural strength of the grinding surface for a consistent quality of wafer with better applicability and industrial benefits.

Abstract: A method for forming vias in a substrate, including the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove on the substrate; (c) filling the groove with a conductive metal; (d) removing part of the substrate which surrounds the conductive metal, wherein the conductive metal is maintained so as to form an accommodating space between the conductive metal and the substrate; (e) forming an insulating material in the accommodating space; and (f) removing part of the second surface of the substrate to expose the conductive metal and the insulating material. In this way, thicker insulating material can be formed in the accommodating space, and the thickness of the insulating material in the accommodating space is even.

Abstract: A micromachine device processing method for dividing a functional wafer, which has micromachine devices formed in a plurality of regions demarcated by streets formed in a lattice pattern on a face of the functional wafer, along the streets into the individual micromachine devices, each micromachine device having a moving portion and an electrode, comprising: a cap wafer groove forming step of forming dividing grooves, which have a depth corresponding to a finished thickness of a cap wafer for protecting the face of the functional wafer, along regions in one surface of the cap wafer which correspond to areas of the electrodes of the micromachine devices; a cap wafer joining step of joining the one surface of the cap wafer subjected to the cap wafer groove forming step to the face of the functional wafer at peripheries of the moving portions; a cap wafer grinding step of grinding the other surface of the cap wafer joined to the face of the functional wafer to expose the dividing grooves to the outside; and a cu

Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.

Abstract: A method for fabricating a solar cell. The method includes providing a thin metallic substrate in roll form. The method also includes applying an abrasive grit to a surface of the thin metallic substrate. The method includes mechanical-polishing the surface with the abrasive grit such that the surface is polished to remove at least one defect from the surface. Mechanical-polishing the surface of the thin metallic substrate is by a roll-to-roll polishing process of the surface of the thin metallic substrate. Moreover, the method includes depositing an absorber layer of the solar cell on the thin metallic substrate.

Abstract: A method of manufacturing dies formed with a dielectric layer is revealed. A liquid dielectric layer is formed on the dicing tape. The liquid dielectric layer is heated to be sticky. Then, a wafer is attached to the dielectric layer on the dicing tape. The wafer is diced into a plurality of dies on the dicing tape. The dies with attached portions of the dielectric layer are picked up to be peeled and separated from the dicing tape. The implementation of the dicing tape can be expanded to resolve various issues such as wafer contaminations, wafer warpage due to multiple heating and mismatching of thermal expansion coefficients, and wafer singulating problems due to alignment difficulties. The wafer handling steps can further be reduced to increase processing yield and to enhance easy and better processing.

Abstract: Methods of forming microelectronic device wafers include fabricating a plurality of semiconductor dies at an active side of a semiconductor wafer, depositing a mask on the semiconductor wafer, removing a central portion of the mask and the semiconductor wafer, and etching. The semiconductor wafer has an outer perimeter edge and a backside that is spaced from the active side by a first thickness. The mask is deposited on the backside of the semiconductor wafer and has a face that is spaced from the backside by a mask thickness. The thinned portion has a thinned surface that is spaced from the active side by a second thickness that is less than the first thickness, and the thinned surface is etched.

Abstract: A solder bump forming method of carrying out a reflow treatment over a conductive ball mounted on a plurality of pads, thereby forming a solder bump, includes a metal film forming step of forming a metal film capable of chemically reacting to a tackifying compound on the pads, an organic sticking layer forming step of causing a solution containing the tackifying compound to chemically react to the metal film, thereby forming an organic sticking layer on the metal film, and a conductive ball mounting step of supplying the conductive ball on the pads having the organic sticking layer formed thereon, thereby mounting the conductive ball on the pads through the metal film.

Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a device substrate having a front side, a back side, and a first edge portion, forming a material layer over a portion of the front side of the device substrate, trimming the first edge portion, removing the material layer, bonding the front side of the device substrate to a carrier substrate, thinning the device substrate from the back side, and trimming a second edge portion of the thinned device substrate.

Abstract: Starting point regions for cutting 8a, 8b extending along lines to cut 5a, 5b are initially formed in an object to be processed 1. The starting point regions for cutting 8b have modified regions 7b formed by irradiating the object 1 with laser light while locating a converging point within the object 1 and are formed in parts extending along the lines to cut 5b excluding portions 34b intersecting the lines to cut 5a. This makes the starting point regions for cutting 8b much less influential when cutting the object 1 from the starting point regions for cutting 8a acting as a start point, whereby bars with precise cleavage surfaces can reliably be obtained. Therefore, it is unnecessary to form a starting point region for cutting along the lines to cut 5b in each of a plurality of bars, whereby the productivity of semiconductor laser elements can be improved.

Abstract: According to an embodiment, a method of manufacturing a solar cell includes depositing a sequence of layers of semiconductor material forming at least one solar cell on a first substrate; temporarily bonding a flexible film to a support second substrate; permanently bonding the sequence of layers of semiconductor material to the flexible film so that the flexible film is interposed between the first and second substrates; thinning the first substrate while bonded to the support substrate to expose the sequence of layers of semiconductor material; and subsequently removing the support substrate from the flexible film.

Abstract: Aimed at stably forming sheared surfaces of leads of semiconductor devices, and at raising ratio of formation of plated layers onto the sheared surfaces of the leads, a lead cutter has a die 106, and a cutting punch 110 having a cutting edge at least on the surface facing the die, wherein clearance T between the die 106 and the cutting punch 110 is set within the range from not smaller than 2.3% and smaller than 14.0% of the total thickness of the leads to be cut and plated layers formed on the upper and the lower surfaces thereof.

Abstract: Manufacturing a wafer level stack package includes the steps of back-grinding a lower surface of a wafer including a plurality of first semiconductor chips. A support member is attached to a lower surface of the back-grinded wafer. One or more second semiconductor chips are stacked on the respective first semiconductor chips of the back-grinded wafer. First through-electrodes are formed to electrically connect the stacked first semiconductor chips and second semiconductor chips. Third semiconductor chips are attached to uppermost ones of the stacked second semiconductor chips, and the third semiconductor chips have second through-electrodes which are electrically connected to the first through-electrodes and re-distribution lines which are connected to the second through-electrodes. Outside connection terminals are attached to the re-distribution lines of the third semiconductor chips.

Abstract: A wafer-cutting process includes first cutting a semiconductive wafer along a first path at a given first cutting intensity including cutting across an intersection. The process also includes second cutting the semiconductive wafer along a second path at a given second cutting intensity. The second cutting intensity is diminished during crossing the intersection and resumed to the given cutting intensity after crossing the intersection.

Abstract: The present invention relates to a method for repairing a semiconductor device. The method includes cutting a fuse without creation of residue by transforming the fuse into a nonconductor of high resistance by oxidizing the fuse by irradiating the fuse with an oxygen ion beam instead of a laser in a blowing process. The method includes transforming a fuse corresponding to a defective cell among a plurality of fuses formed in an upper portion of a semiconductor substrate into an oxide film.

Abstract: A method is provided for producing 3D structures in a semiconductor substrate using Deep Reactive Ion Etching (DRIE), comprising at least the steps of: providing a substrate, and then grinding the backside of the substrate in order to achieve a thinned substrate, wherein extrusions and native oxides are left after said grinding step, and then performing a surface treatment selected from the group consisting of a wet etching step and a dry etching step in order to remove at least said native oxides and extrusions on the surface of said backside of the substrate which are causes for the grass formation during subsequent etching, and then performing deep reactive ion etching in order to achieve 3D vias.

Abstract: A method for manufacturing a silicon wafer is characterized by performing one or both of grinding and polishing to a thin discoid silicon wafer to give bowl-shaped warpage that is concave at a central part to a wafer surface. One main surface of the thin discoid silicon wafer is adsorbed and held, and one or both of grinding and polishing are performed to the other main surface to fabricate a convex wafer whose thickness is increased from a wafer outer periphery toward a wafer center or fabricate a concave wafer whose thickness is reduced from the wafer outer periphery toward the wafer center. Then, the other main surface is adsorbed and held to protrude the center or the periphery of the one main surface side based on elastic deformation. One or both of grinding and polishing are carried out with respect to the one main surface to flatten the main surface, and adsorption and holding are released to give bowl-shaped warpage that is concave at the central part to the other main surface or the one main surface.

Abstract: A wafer level chip scale package and method of laser marking the same are disclosed. The method includes forming a plurality of semiconductor devices on a frontside surface of a wafer, metallizing device contacts on the frontside surface of the wafer, grinding the backside surface of the wafer, silicon etching the backside surface of the wafer, laser marking the backside surface of the wafer following the silicon etch step, oxide etching the backside surface of the wafer following the laser marking step, depositing a metal layer on the backside surface of the wafer following the oxide etch step, and dicing the wafer into wafer level chip scale packages.