Mechanical Treatment, E.g., Grinding, Polishing, Cutting (epo) Patents (Class 257/E21.237)
  • Patent number: 7256105
    Abstract: A semiconductor substrate having a first substrate surface which includes a device area in which semiconductor devices are formed and a substrate peripheral portion which does not overlap with the device area. A concavo-convex portion is formed in the substrate peripheral portion. Preferably, a concavo-convex portion is formed in a side portion which adjoins the peripheral portion. The concavo-convex portion formed in the substrate peripheral portion or the side portion may be formed by a method such as dry etching, wet etching, mechanical grinding, electrolytic plating, nonelectrolytic plating, or patterning using one of a resin material and a metal material. A thin processing method includes forming the device area; forming the concavo-convex portion in the substrate peripheral portion; adhering the first substrate surface to a support; and grinding a second substrate surface of the semiconductor substrate, which is opposite with the first substrate surface.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: August 14, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Koji Yamaguchi
  • Patent number: 7256107
    Abstract: In fabricating a microelectromechanical structure (MEMS), a method of forming a narrow gap in the MEMS includes a) depositing a layer of sacrificial material on the surface of a supporting substrate, b) photoresist masking and at least partially etching the sacrificial material to form at least one blade of sacrificial material, c) depositing a structural layer over the sacrificial layer, and d) removing the sacrificial layer including the blade of the sacrificial material with a narrow gap remaining in the structural layer where the blade of sacrificial material was removed.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: August 14, 2007
    Assignee: The Regents of the University of California
    Inventors: Hideki Takeuchi, Emmanuel P. Quevy, Tsu-Jae King, Roger T. Howe
  • Publication number: 20070184660
    Abstract: Provided is a method of manufacturing a semiconductor device in which, when a polyimide resin film is formed as a protective film on a front surface of a semiconductor chip, the polyimide resin film disposed on scribe lines is removed and the polyimide resin film disposed on a circumferential portion of the semiconductor wafer is also removed. Thus, when a rear surface of the semiconductor wafer is ground, the outer circumferential portion of the semiconductor wafer and the surface protective tape can be completely bonded to each other, thereby making it possible to fill a gap between the surface protective tape and each scribe line formed on the front surface of the semiconductor wafer, prevent grinding wafer from penetrating into the gap when the rear surface of the semiconductor wafer is ground, and prevent the scribe lines and the front surface of the semiconductor chip from being contaminated with grinding swarf.
    Type: Application
    Filed: January 30, 2007
    Publication date: August 9, 2007
    Inventor: Takashi Fujimura
  • Patent number: 7250365
    Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: July 31, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Toshiyuki Arai, Ryousei Kawai, Hirofumi Tsuchiyama, Fumiyuki Kanai, Shinichi Nakabayashi
  • Patent number: 7217662
    Abstract: There is disclosed a method of processing a substrate, which comprises applying a surfactant or a water soluble polymer agent onto a surface of a substrate to be processed, and sliding a circumferential portion of the substrate and a polishing member against each other to polish the circumferential portion of the substrate.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: May 15, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Gen Toyota, Atsushi Shigeta, Hiroyuki Yano
  • Publication number: 20070072338
    Abstract: The present invention provides a semiconductor device package singulation method. The method comprises printing a photo epoxy layer on the back surface of a substrate of a wafer for marking the scribe lines to be diced. Then etching is performed through the substrate along the marks in the photo epoxy layer. Dicing the panel into individual package with a typical art designing knife, the step not only avoids the roughness on the edge of each die, but also decrease the cost of singulation process.
    Type: Application
    Filed: September 26, 2005
    Publication date: March 29, 2007
    Inventors: Wen-Kun Yang, Chun Yu, Jui-Hsien Chang, Hsien-Wen Hsu
  • Patent number: 7186574
    Abstract: A method for forming metrology structures for a CMP process is described. A trench edge is formed in a base material or stack of materials which are preferably deposited as part of the process of fabricating the production structures on the wafer. A covering film of a second material with preferably with contrasting SEM properties is deposited over the trench edge in the base material. During CMP the covering film is preferentially worn away at the edge revealing the base material. The width of the base material which has been revealed is a measure of the progress of the CMP. Since the base material and the covering material are preferably selected to have contrasting images in an SEM, a CD-SEM can be used to precisely measure the CMP progress.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: March 6, 2007
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Sukhbir Singh Dulay, Thomas L. Leong, John Jaekoyun Yang
  • Patent number: 7183178
    Abstract: A method of manufacturing a semiconductor wafer wherein a film is formed on a back surface of a starting semiconductor wafer formed with circuits in a front surface thereof.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: February 27, 2007
    Assignee: Disco Corporation
    Inventor: Kazuhisa Arai
  • Publication number: 20070029684
    Abstract: A method of dividing a wafer having a plurality of areas, which are sectioned by the streets formed on the front surface in a lattice pattern and a plurality of devices, which are formed in the sectioned areas, along streets, the method comprising a first cutting step for holding the front surface of the wafer on a chuck table of a cutting machine and forming a first groove having a depth that is about half of the thickness of the wafer, along the streets from the rear surface of the wafer; a second cutting step for holding the rear surface of the wafer on a chuck table and forming a second groove which does not reach the first groove, along the streets from the front surface of the wafer; and a dividing step for breaking an uncut portion between the first groove and the second groove by exerting external force along the streets of the wafer, on which the first grooves and the second grooves have been formed.
    Type: Application
    Filed: July 21, 2006
    Publication date: February 8, 2007
    Inventors: Kazuhisa Arai, Masatoshi Nanjo
  • Patent number: 7157376
    Abstract: Cassettes for holding thin semiconductor wafers for safe handling are provided, along with an improved methodology for reducing the thickness of semiconductor wafers. Embodiments include a cassette for holding thin semiconductor wafers, having a plurality of sets of center and edge supports, the sets being spaced from each other a distance greater than a sag amount of the wafers. The thin wafers are supported in a predetermined reference plane, so that tools such as robots or automatic handlers can be programmed to pick them up without damaging them. In another embodiment, a double into single pitch wafer cassette is provided having a wafer entrance section with spacing twice as large between sets of edge supports as a conventional cassette, to accommodate the sag/warp of the thin wafers, and a “flattening section” which guides and flattens the wafers between opposing edge supports as they are pushed into the cassette, such that the wafers are held substantially planar.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: January 2, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sally Y. L. Foong, Lim See-Kee, Wong Kwet Nam
  • Patent number: 7115443
    Abstract: The invention relates to a method of manufacturing a packaged semiconductor device comprising subjecting a metal carrier provided with at least one semiconductor crystal, the semiconductor crystal being provided with an encapsulation, to a singulation step in a dicing apparatus that is provided with a dicing blade comprising diamond grains, in which singulation step the dicing blade cuts, while being cooled with a cooling fluid, through the encapsulation and the metal carrier so as to singulate the at least one semiconductor device, characterized by applying a friction force reducing cooling fluid during the singulation step.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: October 3, 2006
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Frederik Hendrik In't Veld, Johannes Hermanus Savenije