Abstract: A wafer processing method for dividing, along streets, a wafer having a device area where devices are formed in a plurality of areas sectioned by the plurality of streets arranged in a lattice pattern on the front surface of a substrate and a peripheral extra area and comprising electrodes which are embedded in the substrate of the device area, comprising a dividing groove forming step for forming dividing grooves having a depth corresponding to the final thickness of each device along the streets; an annular groove forming step for forming an annular groove having a depth corresponding to the final thickness of each device along the boundary between the device area and the peripheral extra area; a protective member affixing step for affixing a protective member to the front surface of the wafer; a rear surface grinding step for grinding a rear surface corresponding to the device area of the substrate of the wafer to expose the dividing grooves and the annular groove to the rear surface of the substrate of th

Abstract: The present invention relates to a method of cutting PCB module using a laser. The method includes steps of: providing a coverlay film, the coverlay film including at least one opening defined therein; attaching the coverlay film onto the PCB module such that the through holes of the PCB module are covered by the coverlay film and the laser cutting area thereof is exposed via the at least one opening; applying a laser beam to the exposed laser cutting area of the PCB module to cutt the PCB module; and removing the coverlay film. A high positioning precision of the PCB module and better cutting result can be obtained.

Abstract: Semiconductor material substrates are polished by a method including at least one polishing step A by means of which the substrate is polished on a polishing pad containing an abrasive material bonded in the polishing pad and a polishing agent solution is introduced between the substrate and the polishing pad during the polishing step; and at least one polishing step B by means of which the substrate is polished on a polishing pad containing an abrasive material-containing polishing pad and wherein a polishing agent slurry containing unbonded abrasive material is introduced between the substrate and the polishing pad during the polishing step.

Abstract: The present invention provides a composition for chemical-mechanical polishing which comprises at least one abrasive particle having a surface at least partially coated by a activator. The activator comprises a metal other than a metal of Group 4(b), Group 5(b) or Group 6(b). The composition further comprises at least one oxidizing agent. The composition is believed to be effective by virtue of the interaction between the activator coated on the surface of the abrasive particles and the oxidizing agent, at the activator surface, to form free radicals. The invention further provides a method that employs the composition in the polishing of a feature or layer, such as a metal film, on a substrate surface. The invention additionally provides a substrate produced this method.

Abstract: Methods are provided, and devices made by such methods. One of the methods includes procuring a semiconductor wafer, processing the wafer to form a plurality of circuits on a top side, forming trenches on the top side between the adjacent circuits, forming a trench passivation layer on side walls of the trenches, forming conductive bumps on the top side of the wafer; and removing material from the bottom side to thin the wafer, and eventually separate the wafer along the trenches into dies, where each die includes only one of the circuits.

Abstract: There is provided a method of producing a bonded wafer by bonding two silicon wafers for active layer and support layer to each other and then thinning the wafer for active layer, in which nitrogen ions are implanted from the surface of the wafer for active layer to form a nitride layer in the interior of the wafer for active layer before the bonding.

Abstract: A process of forming ultra thin wafers having an edge support ring is disclosed. The process provides an edge support ring having an angled inner wall compatible with spin etch processes.

Abstract: Semiconductor wafers are processed so as to remove material on one or both sides by means of at least one grinding tool, with coolant supplied into a contact region between the semiconductor wafer and the at least one grinding tool, characterized in that the coolant flow rate is set as a function of a grinding tooth height of the at least one grinding tool and this coolant flow rate is reduced as the grinding tooth height decreases.

Abstract: Slurry compositions for selectively polishing silicon nitride relative to silicon oxide, methods of polishing a silicon nitride layer and methods of manufacturing a semiconductor device using the same are provided. The slurry compositions include a first agent for reducing an oxide polishing rate, an abrasive particle and water, and the first agent includes poly(acrylic acid). The slurry composition may have a high polishing selectivity of silicon nitride relative to silicon oxide to be employed in selectively polishing a silicon nitride layer in a semiconductor manufacturing process.

Abstract: A method of machining a wafer in which, at the time of grinding the back-side surface of the wafer, only a back-side surface region corresponding to a device formation region where semiconductor chips are formed is thinned by grinding, to form a recessed part on the back side of the wafer. An annular projected part surrounding the recessed part is utilized to secure rigidity of the wafer. Next, the recessed part is etched to cause metallic electrodes to project from the bottom surface of the recessed part, thereby forming a back-side electrode parts, then an insulating film is formed in the recessed part, and the insulating film and end surfaces of the back-side electrode parts are cut.

Abstract: A display apparatus includes a first substrate, a second substrate facing the first substrate, a joining layer interposed between the first and second substrates, and a buffer layer interposed between the joining layer and at least one of the first and second substrates. The buffer layer has a lower heat conductivity than the joining layer to protect the first or second substrate from the heat generated in the joining layer during fabrication.

Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).

Abstract: After performing rough grinding to the back surface of a semiconductor wafer using the first grinding material (for example, particle size of polish fine powder from #320 to #360) and making the thickness of the semiconductor wafer, for example less than 140 ?m, less than 120 ?m, or less than 100 ?m, the back surface of the semiconductor wafer being performed fine finish grinding using the third grinding material (for example, particle size of polish fine powder from #3000 to #100000), the thickness of the semiconductor wafer becomes, for example less than 100 ?m, less than 80 ?m, or less than 60 ?m, and the relatively thin second crush layer, for example the second crush layer of the thickness of less than 0.5 ?m, less than 0.3 ?m, or less than 0.1 ?m is formed on the back surface of the semiconductor wafer.

Abstract: The present invention relates to a polishing composition for a semiconductor wafer which is excellent in polishing property, and a polishing method. The polishing composition for a semiconductor wafer comprises colloidal silica consisting of non-spherical silica particles having a ratio of long axis to short axis of 1.5 to 15. The polishing method for a semiconductor wafer uses the polishing composition. The polishing composition can provide a remarkably high polishing rate compared with a polishing composition using spherical colloidal silica, and can provide good mirror-polishing without causing scratches. In addition, small alkali metal content enables reduction of adverse effects on a semiconductor wafer, such as residual abrasives after polishing.

Abstract: Some embodiments include methods in which a front side region of a semiconductor substrate is placed against a surface. While the front side region is against the surface, the semiconductor substrate is thinned, and then cut into a plurality of dice. The surface may be a pliable material, and may be stretched after the cutting to increase separation between at least some of the dice. While the pliable surface is stretched, at least some of the dice may be picked from the surface. In some embodiments, the semiconductor substrate is retained to the surface with a radiation-curable material. The material is in an uncured and tacky form during the thinning of the substrate, and is subsequently cured into a less tacky form prior to the picking of dice from the surface.

Abstract: A wafer-adhering adhesive tape, which has, on a surface of a base, a radiation-curable removable adhesive layer, and if necessary a die-bonding adhesive layer in order, wherein the radiation-curable removable adhesive layer is mainly composed of an acrylic-series copolymer having, in a principal chain, at least a radiation-curable carbon-carbon double bond containing group, a hydroxyl group, and a group containing a carboxyl group, respectively, and the radiation-curable removable adhesive layer has a gel fraction of 60% or greater.

Abstract: A photoelectric device grinding process comprising the following steps is disclosed. A wafer comprising a plurality of chip units is provided. Each chip unit has at least a photoelectric device disposed on a surface layer. A dielectric substrate is attached to the wafer with glue having a plurality of spacers therein such that the photoelectric devices face the dielectric layer. The spacers maintain a gap between the dielectric substrate and the wafer. Thereafter, the dielectric substrate surface away from the wafer or the wafer surface away from the dielectric substrate or both is ground. The grinding process is particularly suitable for preventing any possible damage to the photoelectric devices on a wafer.

Abstract: A wafer stacked on a mounting layer is safely diced. The mounting layer has holes partially corresponding to chips on the wafer. Thus, chips obtained after dicing the wafer can be safely removed from the mounting tape. An amount of the mounting tape used can be reduced. And a production cost can be lowered as well.

Abstract: The invention provides a semiconductor device, a method of manufacturing the same, an electro-optic device and an electronic apparatus which are capable of addressing or solving a problem of mechanical mounting of a semiconductor element chip on a substrate. A semiconductor device includes a tile-shaped microelement bonded to a substrate, and an insulating functional film provided to cover at least a portion of the tile-shaped microelement.

Abstract: The present invention provides a chemical-mechanical polishing (CMP) composition for polishing a ruthenium-containing substrate in the presence of hydrogen peroxide without forming a toxic level of ruthenium tetroxide during the polishing process. The composition comprises (a) a catalytic oxidant comprising a water-soluble peroxometalate complex, an oxidizable precursor of a peroxometalate complex, or a combination thereof, (b) a particulate abrasive; and (c) an aqueous carrier. The peroxometalate complex and the precursor thereof each have a reduced form that is oxidizable by hydrogen peroxide to regenerate the peroxometalate complex during chemical-mechanical polishing. CMP methods for polishing ruthenium-containing surfaces with the CMP composition are also provided.

Abstract: A method of dividing a wafer whose strength is reduced along a plurality of dividing lines formed in a lattice pattern on the front surface, along the dividing lines, comprising the steps of: a tape affixing step for affixing a protective tape to one side of the wafer; a wafer holding step for holding the wafer affixed to the protective tape on both sides of each dividing line through the protective tape; and a breaking step for dividing the wafer along each dividing line by sucking, along each dividing line, the wafer held through the protective tape.

Abstract: A method of producing a semiconductor device which can reliably perform conductor filling to form a through hole electrode by a simple method is provided. A method of producing a semiconductor device of the present invention includes the steps of thinning a substrate from its back side in a state in which a first supporting body is attached to the front side of the substrate, removing the first supporting body from the substrate and attaching a second supporting body having an opening to the back side of the substrate, forming a through hole communicating with the opening of the second supporting body in the substrate before or after attaching the second supporting body, forming an insulating film within the through hole, and filling a conductor into the through hole of the substrate.

Abstract: A semiconductor device is manufactured in a silicon-on-insulator (SOI) wafer having an silicon active layer, a buried oxide layer, and a supporting substrate layer. Before the wafer is diced into chips along scribe lines, the silicon active layer is selectively etched to form trenches surrounding the scribe lines. The wafer is then diced using a dicing apparatus having a blade width smaller than the width of the trenches. The dicing blade accordingly does not make contact with the silicon active layer, which is particularly vulnerable to chipping.

Abstract: A chemically mechanically polishing method is provided, which includes slide-contacting a polishing film with a polishing pad while feeding a first chemical liquid and a second chemical liquid to the polishing pad. The first chemical liquid contains an electrolyte and bubbles having a diameter ranging from 10 nm to 1000 ?m, and the second chemical liquid contains abrasive particles.

Abstract: An apparatus for cleaving a section of a bar of brittle material is provided. The apparatus comprises a support adapted to hold the section of the bar in a position to be cleaved, a blade, an actuator coupled to the blade for driving the blade at least partially through the bar to create a cleaved portion of the bar, and a follower for engaging the end of the bar during cleaving. An method of cleaving a section of a bar of brittle material is also provided. The method comprises initiating a crack in the bar and driving a blade through the bar to remove a portion of the brittle material from the end of the bar. In one embodiment, the blades drives through the bar at a controlled speed.

Abstract: A process applied to grinding, dicing, and/or stacking semiconductors is disclosed. One of its features is that after transparent material is stuck on its active surface, a semiconductor is ground from another surface thereof to become thinner, then take advantage of transparency of the transparent material to cut the transparent material and the semiconductor, to obtain at least one smaller semiconductor unit such as die or chip. Another feature is that the transparent material remains sticking to the active surface of the die by an adhesion layer until the die is attached to a carrier or another die, and then the transparent material and the adhesion layer are removed by taking advantage of a function of the adhesion layer: receiving a ray to lose adhesion between it and the active surface. Preferably the ray reaches the adhesion layer via the transparent material stuck on the active surface of the die.

Abstract: A system for dicing substrates to singulate integrated circuit units within in them includes a dicing machine (Z) which operates with a chuck table (4). A lifting assembly (Ax,Ay) deposits substrates to be singulated onto the chuck table (4) at substantially the same time as it removes previously singulated units from the chuck table (4).

Abstract: The method for dicing a wafer including the steps of: reducing a thickness of a wafer to at least 0.1mm or less; forming a protection sheet tightly on one side of the wafer, the protection sheet having a Vickers hardness of 2 or more; and dicing the wafer by a grindstone, the wafer having the protection sheet thereon.

Abstract: To provide a polishing compound which is capable of polishing SiC at a high removal rate, or capable of suppressing polishing of silicon dioxide in an insulating layer on the other hand, while polishing SiC at a high removal rate, in production of a semiconductor integrated circuit device, whereby it is possible to obtain a semiconductor integrated circuit device having a planarized multiplayer structure. The present polishing compound comprising abrasive particles (A), an adjusting agent of removal rate (B) which is at least one selected from the group consisting of a benzotriazole, a 1H-tetrazole, a benzene sulfonic acid, phosphoric acid or organic phosphonic acid, an organic solvent (C) having a relative permittivity of from 15 to 80, a boiling point of from 60 to 250° C. and a viscosity of from 0.5 to 60 mPa·S at 25° C., and water (D).

Abstract: Cost is reduced and reliability is improved with a CSP type semiconductor device. A glass substrate which works as a supporting plate is bonded through an adhesive to a first surface of a semiconductor wafer on which first wirings are formed. Thickness of the semiconductor wafer is reduced by back-grinding the semiconductor wafer on a second surface of the semiconductor wafer which is opposite to the first surface of the semiconductor wafer. The semiconductor wafer is wet-etched to remove bumps and dips on the second surface of the semiconductor wafer caused during the back-grinding. Then the second surface of the semiconductor wafer is etched to form a tapered groove. The semiconductor wafer is wet-etched to reduce bumps and dips caused by the etching and round a corner of the groove. The wet-etching improves coverage of insulation film, wiring and protection film and enhances yield and reliability of the semiconductor device.

Abstract: Exemplary embodiments of the invention provide techniques that enable avoidance of the concentration of an electric field at the edge of a semiconductor film in a semiconductor device such as a thin film transistor, thereby enhancing the reliability. Exemplary embodiments provide a method of manufacturing a semiconductor device using a structure in which a semiconductor film, a dielectric film, and an electrode are deposited.

Abstract: The exemplary embodiments of the present invention providing new slurry compositions suitable for use in processes involving the chemical mechanical polishing (CMP) of a polysilicon layer. The slurry compositions include one or more non-ionic polymeric surfactants that will selectively form a passivation layer on an exposed polysilicon surface in order to suppress the polysilicon removal rate relative to silicon oxide and silicon nitride and improve the planarity of the polished substrate. Exemplary surfactants include alkyl and aryl alcohols of ethylene oxide (EO) and propylene oxide (PO) block copolymers and may be present in the slurry compositions in an amount of up to about 5 wt %, although much smaller concentrations may be effective. Other slurry additives may include viscosity modifiers, pH modifiers, dispersion agents, chelating agents, and amine or imine surfactants suitable for modifying the relative removal rates of silicon nitride and silicon oxide.

Abstract: A method of fabricating isolation layers of a semiconductor device is provided. The method includes depositing a pad oxide layer and a hard mask in sequence on a semiconductor substrate and patterning the pad oxide layer and the hard mask. Trenches may be formed by etching the substrate to a specific depth and a gap-fill insulating layer may be formed in the substrate in which the trenches have been formed. The method further includes forming a barrier layer on the gap-fill insulating layer in a region where a pattern density of an isolation layer is relatively low, then polishing and removing the gap-fill insulating layer and the barrier layer until a top surface of the hard mask is exposed. Consequently, isolation layers are gap-filled only in the trenches, yielding a regular surface on the semiconductor substrate.

Abstract: The present invention relates to a process for thinning a semiconductor wafer. Two surfaces of the wafer separately form a surface-bond glue (layer) and a surface protective glue (layer). The thinning process is applied to the wafer before forming the surface protective glue. Once the baking and drying process is applied to the surface-bond glue and the surface protective glue it then cuts the wafer. Finally, it dissolves the lower solubility of the surface protective glue to obtain the finished goods. The necessity of the selection of the wafer may serve to maintain quality standards. The wafer thinning process of the present invention is suitable for the extremely thin wafer. Thus, it reduces the production cost.

Abstract: A method for the removal of residual UV radiation-sensitive adhesive from the surfaces of semiconductor wafers, remaining thereon from protective UV radiation-sensitive tapes which were stripped from the semiconductor wafers. Moreover, provided is an arrangement for implementing the removal of residual sensitive adhesive, which remain from tapes employed as protective layers on semiconductor wafers, particularly wafers having surfaces including C4 connections.

Abstract: A method for fabricating a module of a semiconductor chip is provided. The method includes the steps of: forming a bump on a substrate provided with a pad; forming a protection layer over the bump; performing a grinding process on a rear surface of the substrate to reduce a thickness of the substrate; and exposing the bump by removing the protection layer.

Abstract: To provide a polishing technique with which in production of a semiconductor integrated circuit device, when a plane to be polished is polished, an appropriate polishing rate ratio of a polysilicon film to another material can be obtained, whereby high level planarization of a plane to be polished including a polysilicon film can be realized. A polishing compound for chemical mechanical polishing, containing cerium oxide particles, a water-soluble polyamine and water and having a pH within a range of from 10 to 13, is used.

Abstract: Disclosed are a semiconductor wafer (10) having a front side laser scribe (22) and the methods for manufacturing the same. The methods of the invention include the formation of a scribe foundation (12) on the front side of the semiconductor wafer (10) designed to accept laser scribing (22), and laser scribing the scribe foundation (12). Disclosed embodiments include a semiconductor wafer (10) having a scribe foundation (12) of layered dielectric (30) and metal (34) on the front side. According to disclosed embodiments of the invention, the formation of a scribe foundation (12) is performed in combination with the formation of a top level metal layer (34) on the semiconductor wafer (10) methods for manufacturing.

Abstract: Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape is overlapped and bonded onto the supporting substrate and the semiconductor substrate is ground from the backside. The BG tape is then peeled off and an impurity is introduced into the backside of the semiconductor substrate by ion implantation. Then, the supporting substrate is peeled off, followed by heat treatment of the semiconductor substrate.

Abstract: A partly finished product of a semiconductor device includes a resin body encapsulating a semiconductor chip, first and second leads extended outwardly from the resin body, a dam bar connected between said first and second leads, and an excess resin portion protruding from the resin body between the first and second leads and the dam bar. The excess resin portion is cut off at two limited portions, and thereby two groove portions are formed in the excess resin portion. An apparatus for cutting the dam bar includes a punch having a cutting edge for cutting connection portions between the first and second leads and the dam bar and for cutting off the two limited portions of the excess resin portion. Since the cut region of the excess resin portion becomes smaller, a stress imparted to the resin body and/or the semiconductor chip through the excess resin portion can be smaller.

Abstract: The semiconductor storage device comprises memory cell transistors formed on a semiconductor substrate 10; first insulation films 42 covering the top surfaces and the side surfaces of gate electrodes 20 of the memory cell transistors; through-holes 40 opened on first diffused layers 24; a second insulation film 36 with through-holes 40 opened on second diffused layers 26 formed in; capacitors formed on the inside walls and the bottoms of the through-holes 40 and including capacitor storage electrodes 46, connected to the first diffused layers 24; capacitor dielectric films 48 covering the capacitor storage electrodes 46, and capacitor-opposed electrodes 54 covering at least a part of the capacitor dielectric films 48; and, contact conducting films 44 formed on the inside walls and bottoms of the through-holes 38, and connected to the second diffused layers.

Abstract: To provide a method of processing a sapphire substrate, where reduction in luminance of light emitting devices can be suppressed if a sapphire substrate is divided into individual light emitting devices by irradiation of a laser beam, a pulsed laser beam having a small pulse energy of 0.6 ?J to 10 ?J, and an extremely small pulse width in a range of femto-second is irradiated to the sapphire substrate while a condensing point is positioned within each of regions corresponding to predetermined division lines on the sapphire substrate so that affected zones are formed, thereby the laser beam can be irradiated even at a high peak power density of 4×1013 W/cm2 to 5×1015 W/cm2, consequently each of the affected zones can be formed at only a desired condensing point within the sapphire substrate, and necessary processing can be performed while damage to nitride semiconductors or the sapphire substrate is minimized.

Abstract: The present invention provides a substrate treating method including the steps of joining a one-side surface of a substrate to be treated to a support substrate, treating the substrate to be treated in the condition where the substrate to be treated is supported by the support substrate, and removing the support substrate from the substrate to be treated. The step of joining the substrate to be treated to the support substrate includes melting a joint bump formed on the substrate to be treated so as to join the substrate to be treated to the support substrate, and the step of removing the support substrate from the substrate to be treated includes polishing the support substrate so as to remove the support substrate.

Abstract: A method for self-supported transfer of a fine layer, in which at least one species of ions is implanted in a source-substrate at a specified depth in relation to the surface of the source-substrate. A stiffener is applied in intimate contact with the source-substrate and the source-substrate undergoes a heat treatment at a specified temperature during a specified period of time in order to create an embrittled buried area substantially at the specified depth without causing a thin layer, defined between the surface and the embrittled buried layer in relation to the remainder of the source-substrate, to become thermally detached. A controlled localized energy pulse is applied to the source-substrate in order to cause the self-supported detachment of the thin layer.

Abstract: A semiconductor wafer includes a plurality of active circuit die areas, each of which being bordered by a dicing line through which the plurality of active circuit die areas are separated from each other by mechanical wafer dicing. WAT pads are disposed along the dicing line. Each of the WAT pads has thereon a slot opening. A reinforcement structure is formed within the slot opening and penetrates through the WAT pad for stopping propagation of de-lamination during wafer dicing.

Abstract: In a production method of a micromachine having a space between first and second electrodes, a first electrode is formed on a substrate, and then a stopper film is formed on its surface. Next, a second insulating film is formed as to cover the stopper film. The thickness of the second insulating film is larger than a total thickness of the first electrode and stopper film. Then, second insulating film is polished. By this polishing, the stopper film is exposed to the outside to the outside, and is planarized. After forming an opening in the stopper film, a sacrifice film is burred in the opening. Surfaces of the sacrifice film and second insulating film are planarized, and a second electrode is formed on the second insulating film as to cross the sacrifice film. A space is formed between the first and second electrodes by removing the sacrifice film.

Abstract: In a method for processing a semiconductor wafer, having a plurality of solder bumps bonded on a front surface thereof, a fluid-like layer is formed on the front surface of the semiconductor wafer. A holder sheet is prepared, and has a support layer, and an adhesive layer formed on a surface of the support layer and exhibiting a fluidness. The fluid-like layer is covered with the holder sheet such that the adhesive layer of the holder sheet is rested on a surface of the fluid-like layer, and the adhesive layer of the holder sheet is transformable so as to conform with a configuration of the surface of the fluid-like layer due to the fluidness of the adhesive layer of the holder sheet. A rear surface of the semiconductor wafer is mechanically ground so that the thickness of the semiconductor wafer is reduced to a target value. The holder sheet is peeled from the surface of the fluid-like layer.

Abstract: This silicon wafer production process comprises in the order indicated a planarization step, in which the front surface and the rear surface of a wafer are ground or lapped, a single-wafer acid etching step, in which an acid etching liquid is supplied to the surface of the wafer while spinning and the entire wafer surface is etched to control the surface roughness Ra to 0.20 ?m or less, and a double-sided simultaneous polishing step, in which the front surface and the rear surface of the acid etched wafer are polished simultaneously. The process may comprise a single-sided polishing step, in which the top and bottom of the acid etched wafer are polished in turn, instead of the double-sided simultaneously polishing step.

Abstract: A semiconductor structure and a method of fabrication there-for are provided. The semiconductor structure comprises a substrate, a dielectric layer disposed over the substrate, a hydrophilic material layer disposed over the dielectric layer, and a hardmask layer disposed over the hydrophilic material layer. It is noted that, the edge of the semiconductor structure may be polished after the hydrophilic material layer is formed over the dielectric layer and before the hardmask layer is formed over the hydrophilic material layer.

Abstract: A die attaching method of a semiconductor chip simplifies the process of fabricating a package from the chip while preventing the chip form being damaged even when the chip is very thin. Warpage prevention material is adhered to a top surface of a wafer having a plurality of chips formed thereon, and then the wafer is cut to separate the chips from one another. Each semiconductor chip is then placed on and attached to a die pad of a base frame, while the warpage prevention material is detached from the semiconductor chip. Thus, the warpage prevention material is removed without requiring a process that is extraneous to the die attaching process.