By Dry-etching (epo) Patents (Class 257/E21.256)
  • Patent number: 10465294
    Abstract: Methods are described herein for etching metal films which are difficult to volatize. The methods include exposing a metal film to a chlorine-containing precursor (e.g. Cl2). Chlorine is then removed from the substrate processing region. A carbon-and-nitrogen-containing precursor (e.g. TMEDA) is delivered to the substrate processing region to form volatile metal complexes which desorb from the surface of the metal film. The methods presented remove metal while very slowly removing the other exposed materials. A thin metal oxide layer may be present on the surface of the metal layer, in which case a local plasma from hydrogen may be used to remove the oxygen or amorphize the near surface region, which has been found to increase the overall etch rate.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: November 5, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Xikun Wang, Jie Liu, Anchuan Wang, Nitin K. Ingle, Jeffrey W. Anthis, Benjamin Schmiege
  • Patent number: 10395991
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure and a second gate structure on a substrate and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure into a first metal gate and the second gate structure into a second metal gate; removing part of the ILD layer between the first metal gate and the second metal gate to form a recess; forming a first spacer and a second spacer in the a recess; performing a first etching process to form a first contact hole; and performing a second etching process to extend the first contact hole into a second contact hole.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: August 27, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Chun-Ya Chiu, Chin-Hung Chen, Chi-Ting Wu, Yu-Hsiang Lin
  • Patent number: 10032632
    Abstract: Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: July 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John Christopher Arnold, Sean D. Burns, Yann Alain Marcel Mignot, Yongan Xu
  • Patent number: 9812501
    Abstract: A variable resistance memory device includes a plurality of first conductive layer pattern, a plurality of second conductive layer patterns over the first conductive layer patterns, and a plurality of lower cell structures including a switching element and a variable resistance element, the lower cell structures being formed at intersections at which the first conductive layer patterns and the second conductive layer patterns overlap each other. The first conductive layer patterns, the second conductive layer patterns and the lower cell structures serves as one of a memory cell, a first dummy pattern structure and a second dummy pattern structure.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: November 7, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Woo Lee, Youn-Seon Kang, Seung-Jae Jung, Hyun-Su Ju, Masayuki Terai
  • Patent number: 9779952
    Abstract: Techniques herein include methods for controllable lateral etching of dielectrics in polymerizing fluorocarbon plasmas. Methods can include dielectric stack etching that uses a mask trimming step as part of a silicon etching process. Using a fluorocarbon mixture for dielectric mask trimming provides several advantages, such as being straightforward to apply and providing additional flexibility to the process flow. Thus, techniques herein provide a method to correct or tune CDs on a hardmask. In general, this technique can include using a fluorine-based and a fluorocarbon-based, or fluorohydrocarbon-based, chemistry for creating a plasma, and controlling a ratio of the two chemistries. Without the hardmask trim method disclosed herein, if a hardmask CD is not on target, then a wafer is scrapped. With hard-mask trim capability in silicon etch as disclosed herein, a given CD can be re-targeted to eliminate wafer-scraps.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: October 3, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Alok Ranjan, Sergey Voronin
  • Patent number: 9633941
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate. The first dielectric layer has a first opening exposing the first conductive structure. The semiconductor device structure includes a seal layer covering an inner wall of the first opening and in direct contact with the first dielectric layer. The seal layer includes a dielectric material including an oxygen compound. The semiconductor device structure includes a second conductive structure filled in the first opening and surrounded by the seal layer. The second conductive structure is electrically connected to the first conductive structure.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: April 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shu-Cheng Lin, Chih-Lin Wang, Kang-Min Kuo
  • Patent number: 9627313
    Abstract: Methods of forming conductive structures and the conductive structures are disclosed. A method includes forming an opening in a dielectric layer over a substrate, performing a cleaning process on the dielectric layer with the opening, forming a nucleation layer in the opening, etching the nucleation layer in the opening, and forming a conductive material in the opening and on the nucleation layer after the etching. An upper portion of the opening is distal from the substrate, and a lower portion of the opening is proximate the substrate. After the etching, a thickness of an upper portion of the nucleation layer in the upper portion of the opening is less than a thickness of a lower portion of the nucleation layer in the lower portion of the opening.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-I Tsai, Chi-Yuan Chen, Wei-Jung Lin, Chia-Han Lai
  • Patent number: 9306185
    Abstract: There is provided a process for forming a contained second layer over a first layer, including the steps: forming the first layer having a first surface energy; treating the first layer with a priming layer; exposing the priming layer patternwise with radiation resulting in exposed areas and unexposed areas; developing the priming layer to effectively remove the priming layer from either the exposed areas or the unexposed areas resulting in a first layer having a pattern of priming layer, wherein the pattern of priming layer has a second surface energy that is higher than the first surface energy; and forming the second layer by liquid depositions on the pattern of priming layer on the first layer. There is also provided an organic electronic device made by the process.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: April 5, 2016
    Assignee: E I DU PONT DE NEMOURS AND COMPANY
    Inventors: Adam Fennimore, Jonathan M Ziebarth, Nora Sabina Radu
  • Patent number: 8765549
    Abstract: Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. In an embodiment, a capacitor is formed between a through via and a lower level metallization layer. The capacitor may be, for example, a planar capacitor formed on the substrate or on a dielectric layer formed over the substrate.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hua Chang, Shin-Puu Jeng, Der-Chyang Yeh, Shang-Yun Hou, Wen-Chih Chiou
  • Patent number: 8753930
    Abstract: A method of manufacturing a semiconductor device comprises placing a semiconductor substrate in an ashing chamber, the semiconductor substrate having a gate, a silicon nitride gate sidewall offset spacer or a silicon nitride gate sidewall pacer formed thereon, and a photo resist residue remaining on the semiconductor substrate, introducing a gas mixture including D2 or T2 into the ashing chamber, and ashing the photo resist residue using a plasma that is formed from the gas mixture. The gas mixture can include a deuterium gas or a tritium gas having a volume ratio ranging between about 1% and about 20%. Embodiments can reduce Si recess and the loss of silicon nitride thin film during ashing.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: June 17, 2014
    Assignee: Semiconductor Manufacturing (Shanghai) Corporation
    Inventors: Xiaoying Meng, Junqing Zhou, Haiyang Zhang
  • Patent number: 8647991
    Abstract: A method for forming a dual damascene opening includes the following steps. Firstly, a first hard mask layer with a trench pattern is formed over a material layer. Then, a dielectric layer is formed over the first hard mask layer and filled into an opening of the trench pattern. Then, a second hard mask layer with a via opening pattern is formed over the first hard mask layer and the dielectric layer. Then, a first etching process is performed, so that a via opening is at least formed in the dielectric layer. After the second hard mask layer is removed, a second etching process is performed. Consequently, a trench opening is formed in the material layer and the via opening is further extended into the material layer, wherein the via opening is located within the trench opening.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: February 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Heng Liu, Seng-Wah Liau
  • Patent number: 8501501
    Abstract: A sample with at least a first structure and a second structure is measured and a first model and a second model of the sample are generated. The first model models the first structure as an independent variable and models the second structure. The second model of the sample models the second structure as an independent variable. The measurement, the first model and the second model together to determine at least one desired parameter of the sample. For example, the first structure may be on a first layer and the second structure may be on a second layer that is under the first layer, and the processing of the sample may at least partially remove the first layer, wherein the second model models the first layer as having a thickness of zero.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: August 6, 2013
    Assignee: Nanometrics Incorporated
    Inventors: Ye Feng, Zhuan Liu
  • Publication number: 20130189845
    Abstract: A method of forming a nitrogen-doped amorphous carbon layer on a substrate in a processing chamber is provided. The method generally includes depositing a predetermined thickness of a sacrificial dielectric layer over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, depositing conformally a predetermined thickness of a nitrogen-doped amorphous carbon layer on the patterned features and the exposed upper surface of the substrate, selectively removing the nitrogen-doped amorphous carbon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers formed from the nitrogen-doped amorphous carbon layer, and removing the patterned features from the substrate.
    Type: Application
    Filed: January 19, 2012
    Publication date: July 25, 2013
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Sungjin Kim, Deenesh Padhi, Song Hyun Hong, Bok Hoen Kim, Derek R. Witty
  • Patent number: 8394724
    Abstract: A method for forming device features with reduced line end shortening (LES) includes trimming the device feature to achieve the desired sub-ground rule critical dimension during the etch to form the device feature.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: March 12, 2013
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Hai Cong, Wei Loong Loh, Krishan Gopal, Xin Zhang, Mei Sheng Zhou, Pradeep Ramachandramurthy Yelehanka
  • Patent number: 8361275
    Abstract: When a substrate is etched by using a processing gas including a first gas containing halogen and carbon and having a carbon number of two or less per molecule, while supplying the processing gas toward the substrate independently from a central and a peripheral portion of a gas supply unit, which face the central and the periphery part of the substrate respectively, the processing gas is supplied such that a gas flow rate is greater in the central portion than in the peripheral portion. When the substrate is etched by using a processing gas including a second gas containing halogen and carbon and having a carbon number of three or more per molecule, the processing gas is supplied such that a gas flow rate is greater in the peripheral portion than in the central portion.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: January 29, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Shigeru Tahara, Masaru Nishino
  • Publication number: 20120273924
    Abstract: Provided are an actinic-ray- or radiation-sensitive resin composition that excels in the sensitivity, roughness characteristics and exposure latitude, and a method of forming a pattern using the same. The composition includes (A) a resin that when acted on by an acid, is decomposed to thereby increase its solubility in an alkali developer, and (B) a compound that when exposed to actinic rays or radiation, is decomposed to thereby generate an acid, the compound being any of compounds of general formula (1-1) below.
    Type: Application
    Filed: December 22, 2011
    Publication date: November 1, 2012
    Applicant: FUJIFILM Corporation
    Inventors: Tomoki Matsuda, Akinori Shibuya, Yoko Tokugawa, Shuhei Yamaguchi, Mitsuhiro Fujita
  • Patent number: 8283254
    Abstract: There are provided an etching method and an etching apparatus suitable for etching an antireflection coating layer by using a resist film as a mask. The etching method includes forming the antireflection coating layer (Si-ARC layer) on an etching target layer; forming a patterned resist film (ArF resist film) on the antireflection coating layer; and forming a desired pattern on the antireflection coating layer by introducing an etching gas including a CF4 gas, a COS gas and an O2 gas into a processing chamber and etching the antireflection coating layer by the etching gas while using the resist film as a mask.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: October 9, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Takahito Mukawa
  • Publication number: 20120129353
    Abstract: Provided by the present invention is a method including: (1) forming a resist underlayer film on the upper face side of a substrate to be processed using a composition for forming a resist underlayer film, the composition containing (A) a compound having a group represented by the following formula (1); (2) forming a resist coating film by applying a resist composition on the resist underlayer film; (3) exposing the resist coating film by selectively irradiating the resist coating film with a radiation; (4) forming a resist pattern by developing the exposed resist coating film; and (5) forming a predetermined pattern on the substrate to be processed by sequentially dry etching the resist underlayer film and the substrate using the resist pattern as a mask.
    Type: Application
    Filed: September 28, 2011
    Publication date: May 24, 2012
    Applicant: JSR Corporation
    Inventors: Shin-ya MINEGISHI, Shin-ya Nakafuji, Satoru Murakami, Toru Kimura
  • Patent number: 8133779
    Abstract: A conductive film is formed to extend from a bottom and a sidewall of a recess formed in an interlayer insulating film onto a top surface of the interlayer insulating film. Dry etching of the conductive film is performed such that a portion of the conductive film remains on the bottom and sidewall of the recess. The dry etching is also performed such that a deposition film is formed on a top portion of the recess.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: March 13, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Keisuke Ohtsuka
  • Publication number: 20110294295
    Abstract: A method for making a three-dimensional nano-structure array includes following steps. First, a substrate is provided. Next, a mask is formed on the substrate. The mask is a monolayer nanosphere array or a film defining a number of holes arranged in an array. The mask is then tailored and simultaneously the substrate is etched by the mask. Lastly, the mask is removed.
    Type: Application
    Filed: December 16, 2010
    Publication date: December 1, 2011
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., Tsinghua University
    Inventors: ZHEN-DONG ZHU, QUN-QING LI, SHOU-SHAN FAN
  • Patent number: 8017517
    Abstract: A method and system for forming dual damascene structures in a semiconductor package. In one embodiment, the method includes forming an intermediate dielectric layer on a bottom stop layer; forming an ashing removable dielectric layer on the intermediate dielectric layer; forming a patterned photoresist layer above the ashing removable dielectric layer in the semiconductor structure; and defining an in-situ hard mask in the ashing removable dielectric layer having an opening with a profile selected from the group consisting of a via, a trench, or a combination thereof. The profile of the in-situ mask preferably is capable of being transferred to the intermediate dielectric layer by etching.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: September 13, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yen Chiu Kuo
  • Patent number: 7998876
    Abstract: A method of producing a semiconductor element includes the steps of forming a wiring portion layer on a substrate; forming an interlayer insulation layer over the substrate and the wiring portion layer, in which a third insulation film, a second insulation film, and a first insulation film are laminated in this order from the substrate; forming a mask pattern on the first insulation film; removing a contact hole forming area of the first insulation film through a wet etching process; removing a contact hole forming area of the second insulation film through an etching process; removing a contact hole forming area of the third insulation film through an etching process; and a contact hole forming step of forming a contact hole in the interlayer insulation layer so that a surface of the wiring portion layer is exposed.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: August 16, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Toshiyuki Orita
  • Patent number: 7981734
    Abstract: A manufacturing method of a thin film transistor includes forming a pair of source/drain electrodes on a substrate, such that the source/drain electrodes define a gap therebetween; forming low resistance conductive thin films, which define a gap therebetween, on the source/drain electrodes; and forming an oxide semiconductor thin film layer on upper surface of the low resistance conductive thin films and in the gap defined between the low resistance conductive thin films so that the oxide semiconductor thin film layer functions as a channel. The low resistance conductive thin films and the oxide semiconductor thin film layer are etched so that side surfaces of the resistance conductive thin films and corresponding side surfaces of the oxide semiconductor thin film layer coincide with each other in a channel width direction of the channel. A gate electrode is mounted over the oxide semiconductor thin film layer.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: July 19, 2011
    Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.
    Inventors: Mamoru Furuta, Takashi Hirao, Hiroshi Furuta, Tokiyoshi Matsuda, Takahiro Hiramatsu, Hiromitsu Ishii, Hitoshi Hokari, Motohiko Yoshida
  • Patent number: 7981800
    Abstract: A shallow trench isolation (STI) structure and method for forming the same is provided that reduces defects in a nitride film used as a field oxide mask and variations in pad oxide thickness. Generally, the method involves depositing a nitride over pad oxide on a substrate using plasma enhanced chemical vapor deposition (PECVD), and patterning the PECVD nitride to form a field oxide mask. In certain embodiments, patterning the PECVD nitride involves: (i) forming a patterned resist layer on the PECVD nitride; (ii) etching in a process chamber at least one opening through at least the PECVD nitride; and (iii) stripping the patterned resist layer in-situ in the same process chamber in which the at least one opening was etched through the PECVD nitride using a fluorine based plasma. Other embodiments are also disclosed.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: July 19, 2011
    Assignee: Cypress Semiconductor Corporation
    Inventors: Geethakrishnan Narasimhan, Mehran Sedigh
  • Patent number: 7977245
    Abstract: Methods for etching a dielectric barrier layer with high selectivity to a dielectric bulk insulating layer are provided. In one embodiment, the method includes providing a substrate having a portion of a dielectric barrier layer exposed through a dielectric bulk insulating layer in a reactor, flowing a gas mixture containing H2 gas, fluorine containing gas, at least an insert gas into the reactor, and etching the exposed portion of the dielectric barrier layer selectively to the dielectric bulk insulating layer.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: July 12, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Ying Xiao, Gerardo A. Delgadino, Karsten Schneider
  • Patent number: 7968401
    Abstract: A method of plasma immersion ion implantation of a workpiece having a photoresist mask on its top surface prevents photoresist failure from carbonization of the photoresist. The method includes performing successive ion implantation sub-steps, each of the ion implantation sub-steps having a time duration over which only a fractional top portion of the photoresist layer is damaged by ion implantation. After each one of the successive ion implantation sub-steps, the fractional top portion of the photoresist is removed while leaving the remaining portion of the photoresist layer in place by performing an ashing sub-step. The number of the successive ion implantation sub-steps is sufficient to reach a predetermined ion implantation dose in the workpiece.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: June 28, 2011
    Inventors: Martin A. Hilkene, Kartik Santhanam, Yen B. Ta, Peter I. Porshnev, Majeed A. Foad
  • Publication number: 20110140244
    Abstract: The invention relates to a method for routing a chamfered substrate, having applications in the field of electronics, optics, or optoelectronics, which involves depositing a layer of a protective material on a peripheral annular zone of the substrate preferably with the aid of a plasma, partially etching the protective material with the aid of a plasma, so as to preserve a protective ring of the deposited material on the front face of the substrate, this ring located at a distance from the edge of the substrate, so as to delimit an accessible peripheral annular zone, etching a thickness of the material constituting the substrate to be routed, preferably with the aid of a plasma that is level with the accessible peripheral annular zone of the substrate, and removing the ring of protective material preferably with the aid of a plasma.
    Type: Application
    Filed: December 10, 2010
    Publication date: June 16, 2011
    Inventors: Walter Schwarzenbach, Aziz Alami-Idrissi, Alexandre Chibko, Sébastien Kerdiles
  • Patent number: 7851384
    Abstract: Methods are provided for processing a substrate comprising a bilayer barrier film thereon. In one aspect, a method comprises depositing a first barrier layer, depositing a second barrier layer on the first barrier layer, depositing a dielectric layer on the bilayer barrier film formed by the first barrier layer and the second barrier layer, and ultraviolet curing the dielectric layer. In another aspect, a method comprises depositing a first barrier layer, depositing a second barrier layer on the first barrier layer, depositing a dielectric layer on the bilayer barrier film formed by the first barrier layer and the second barrier layer, and curing the dielectric layer with an electron beam treatment.
    Type: Grant
    Filed: May 21, 2007
    Date of Patent: December 14, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Yijun Liu, Huiwen Xu, Li-Qun Xia, Chad Peterson, Hichem M'Saad
  • Patent number: 7816253
    Abstract: When an interconnect structure is built on porous ultra low k (ULK) material, the bottom of the trench and/or via is usually damaged by a following metallization process which may be suitable for dense higher dielectric materials. Embodiment of the present invention may provide a method of forming an interconnect structure on an inter-layer dielectric (ILD) material. The method includes steps of treating an exposed area of said ILD material to create a densified area, and metallizing said densified area.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: October 19, 2010
    Assignee: International Business Machines Corporation
    Inventors: Shyng-Tsong Chen, Qinghuang Lin, Kelly Malone, Sanjay Mehta, Terry A. Spooner, Chih-Chao Yang
  • Patent number: 7808026
    Abstract: Provision of a process capable of preferably etching particularly PtMn used for a pin layer of an MRAM is an object: a dry etching method for performing dry etching on a layer including platinum and/or manganese by using pulse plasma and a production method of an MRAM, wherein the dry etching method is applied to processing of the pin layer. The MRAM is configured to have a memory portion comprising a magnetic memory element composed of tunnel magnetoresistive effect element formed by stacking a magnetic fixed layer having a fixed magnetization direction, a tunnel barrier layer and a magnetic layer capable of changing the magnetization direction.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: October 5, 2010
    Assignees: Sony Corporation
    Inventors: Toshiaki Shiraiwa, Tetsuya Tatsumi, Seiji Samukawa
  • Patent number: 7799693
    Abstract: Method for manufacturing a semiconductor device including a semiconductor substrate, an element formed on the substrate, and an insulating film formed on the element, includes: (a) forming a first conductive layer (b) forming a first insulating film on the upper portion of the first conductive layer; (c) forming a second insulating film with a porous structure on the first insulating film; (d) forming a third insulating film different from the second insulating film on the second insulating film; (e) forming a via hole in the second and third insulating film by dry etching of the third insulating films; (f) removing a part of the first insulating film such that the surface of the first conductive layer is exposed at the bottom of the via hole and (g) forming a second conductive material film layer so as to fill the via hole.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: September 21, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Eiichi Soda
  • Patent number: 7745337
    Abstract: A method that includes forming a gate of a semiconductor device on a substrate, and etching sidewall spacers on sides of the gate to provide a proximity value, where the proximity value is defined as a distance between the gate and an edge of a performance-enhancing region. The sidewall spacers are used to define the edge of the region during formation of the region in the substrate. The method also includes pre-cleaning the gate and the substrate in preparation for formation of the region, where the etching and the pre-cleaning are performed in a continuous vacuum.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: June 29, 2010
    Assignee: Globalfoundries Inc.
    Inventors: David G. Farber, Fred Hause, Markus Lenski, Anthony C. Mowry
  • Patent number: 7737044
    Abstract: A method of manufacturing a solid state imaging device having photoelectric conversion devices, the method including: 1) forming a plurality of color filters differing in color from each other, 2) forming a transparent resin layer on the color filters, 3) forming an etching control layer on the transparent resin layer, the etching control layer being enabled to be etched at a different etching rate from the etching rate of the transparent resin layer, 4) forming a lens master on the etching control layer by using a heat-flowable resin material, 5) transferring a pattern of the lens master to the etching control layer by dry etching to form an intermediate micro lens, and 6) transferring a pattern of the intermediate micro lens to the transparent resin layer by dry etching to form the transfer lenses.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: June 15, 2010
    Assignee: Toppan Printing Co., Ltd.
    Inventors: Kenzo Fukuyoshi, Tadashi Ishimatsu, Keisuke Ogata, Mitsuhiro Nakao, Akiko Uchibori
  • Patent number: 7737023
    Abstract: In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes an organosiloxane as a main component, the recess, such as a trench or hole, is formed by subjecting the organic insulating film to plasma dry etching in a CF-based gas/N2/Ar gas in order to suppress the formation of an abnormal shape on the bottom of the recess, upon formation of a photoresist film over the organic insulating film, followed by formation of the recess therein with the photoresist film as an etching mask.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: June 15, 2010
    Assignee: Renesas Technology Corporation
    Inventors: Shouochi Uno, Atsushi Maekawa, Takashi Yunogami, Kazutami Tago, Kazuo Nojiri, Shuntaro Machida, Takafumi Tokunaga
  • Patent number: 7737010
    Abstract: A method of forming an intermediate semiconductor device is disclosed that comprises providing a semiconductor substrate, forming a photoresist layer on the semiconductor substrate, implanting a dopant into the semiconductor substrate, and removing a dopant-containing layer from the photoresist layer. The dopant-containing layer includes dopant residuals and a carbon-rich crust and may be formed during implantation. The dopant-containing layer may be removed from the photoresist layer by exposing the dopant-containing layer to a water rinse, a chlorinated plasma or to a fluorinated plasma. The water rinse may include deionized water that is maintained at a temperature that ranges from approximately 25° C. to approximately 80° C. The fluorinated plasma may be formed from a gaseous precursor selected from the group consisting of nitrogen trifluoride, carbon tetrafluoride, trifluoromethane, hexafluoroethane, sulfur hexafluoride, and mixtures thereof.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: June 15, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Shu Qin, Allen McTeer, Robert J. Hanson
  • Patent number: 7723133
    Abstract: A method for forming a pattern, comprises: forming a bank film on a substrate; performing a lyophobic treatment on a surface of the bank film; patterning the bank film on which the lyophobic treatment has been performed to form a bank; performing a surface modification treatment in which a hydroxyl group on a surface of a pattern forming region partitioned by the bank is alkylated; disposing a functional liquid in the pattern forming region; and firing the functional liquid to form a pattern.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: May 25, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Katsuyuki Moriya, Toshimitsu Hirai
  • Patent number: 7704888
    Abstract: Methods for removing photoresist from semiconductor structures are provided. In an exemplary embodiment, a method for removing photoresist from a semiconductor structure having a high-k dielectric material layer overlying a substrate comprises depositing a photoresist overlying the high-k dielectric material layer and patterning the photoresist. The temperature of the substrate is adjusted to a temperature of no less than about 400° C. and hydrogen gas is excited to form a hydrogen plasma of excited H and H2 species. The photoresist is subjected to the excited H and H2 species from the hydrogen plasma.
    Type: Grant
    Filed: January 23, 2007
    Date of Patent: April 27, 2010
    Assignee: Globalfoundries Inc.
    Inventor: Richard J. Carter
  • Patent number: 7678588
    Abstract: An optical critical dimension measuring method, applicable in measuring a pattern, that includes a plurality of polysilicon layers, of a device, is provided. The method includes obtaining a real curve corresponding to the to-be-measured device. Then, determining whether an ion implantation process has been performed on the polysilicon layers, a different module is selected. A correlation process is performed according to the selected module to generate a theoretical curve that correlates with the real curve to obtain a plurality of parameters corresponding to the theoretical curve.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: March 16, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Chi Huang, Wen-Yi Teng
  • Patent number: 7674393
    Abstract: When a substrate is etched by using a processing gas including a first gas containing halogen and carbon and having a carbon number of two or less per molecule, while supplying the processing gas toward the substrate independently from a central and a peripheral portion of a gas supply unit, which face the central and the periphery part of the substrate respectively, the processing gas is supplied such that a gas flow rate is greater in the central portion than in the peripheral portion. When the substrate is etched by using a processing gas including a second gas containing halogen and carbon and having a carbon number of three or more per molecule, the processing gas is supplied such that a gas flow rate is greater in the peripheral portion than in the central portion.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: March 9, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Shigeru Tahara, Masaru Nishino
  • Publication number: 20100009542
    Abstract: A substrate processing method that forms an opening, which has a size that fills the need for downsizing a semiconductor device and is to be transferred to an amorphous carbon film, in a photoresist film of a substrate to be processed. Deposit is accumulated on a side wall surface of the opening in the photoresist film using plasma produced from a deposition gas having a gas attachment coefficient S of 0.1 to 1.0 so as to reduce the opening width of the opening.
    Type: Application
    Filed: June 29, 2009
    Publication date: January 14, 2010
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Masanobu Honda, Hironobu Ichikawa
  • Patent number: 7615480
    Abstract: Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In one embodiment, the method comprises forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor. The method also includes etching a hole for a through-hole via through the hard mask to the semiconductor using a patterned photoresist process, removing the patterned photoresist and using a hard mask process to etch the hole to an amount into the semiconductor. The method further includes depositing a dielectric liner to isolate the hole from the semiconductor, depositing a gapfill metal to fill the hole, and planarizing the surface of the substrate to the hard mask. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: November 10, 2009
    Assignee: Lam Research Corporation
    Inventors: John Boyd, Fritz Redeker, Yezdi Dordi, Hyungsuk Alexander Yoon, Shijian Li
  • Patent number: 7601641
    Abstract: Methods are provided for etching during fabrication of a semiconductor device. The method includes initially etching to partially remove a portion of one or more lithographic-aiding layers overlying an oxide layer while etching a first portion of the oxide layer in accordance with a mask formed by the one or more lithographic-aiding layers, and thereafter additionally etching to remove remaining portions of the one or more lithographic-aiding layers while etching a remaining portion of the oxide layer.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: October 13, 2009
    Assignee: Global Foundries, Inc.
    Inventors: Erik Geiss, Christopher Prindle, Sven Beyer
  • Patent number: 7569478
    Abstract: In a method for manufacturing a semiconductor device having a dual damascene structure, a semiconductor substrate formed by stacking a trench mask and a via hole resist mask on an insulating film is loaded into a processing chamber, and a via hole is formed by etching the insulating film through the via hole resist mask. Then, the via hole resist mask is removed by an ashing process and a protective film is formed on an underlayer of the insulating film; Thereafter, a trench is formed by etching the insulating film through the trench mask, and the semiconductor substrate is unloaded from the processing chamber after the via hole forming step, the resist mask removing step, the protective film forming step and the trench forming step are completed in the processing chamber.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: August 4, 2009
    Assignee: Tokyo Electron Limited
    Inventor: Hiroshi Tsujimoto
  • Patent number: 7566644
    Abstract: A method for forming a gate electrode of a semiconductor device is provided wherein a hard mask layer which is a nitride film is deposited and subjected to an additional surface deposition process so that a matrix structure of a nitride film surface becomes more compact to reduce an etching ratio of the hard mask layer thereby increasing a thickness of the residual hard mask layer.
    Type: Grant
    Filed: June 2, 2005
    Date of Patent: July 28, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Ki Won Nam
  • Patent number: 7541286
    Abstract: A semiconductor device manufacturing method using a KrF light source is disclosed. Embodiments relate to a method for manufacturing a semiconductor device including forming an oxide film over a semiconductor substrate. A gate conductor may be formed over the oxide film. An antireflective film may be formed over the gate conductor. A photoresist film may be formed over the antireflective film. The photoresist film may be photo-etched, thereby forming a first photoresist film pattern having a first line width. The antireflective film may be etched, using the first photoresist film pattern as a mask, thereby forming an antireflective film pattern. The first photoresist film pattern may be simultaneously laterally etched, thereby forming a second photoresist film pattern having a second line width corresponding to a final design value for the gate conductor.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: June 2, 2009
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Chang-Myung Lee
  • Patent number: 7517468
    Abstract: The present invention is a method of etching a lower layer film (64) of an organic material formed on a surface layer (61) of a substrate, using an upper layer film (63) of an Si-containing organic material as a mask. A mixed gas containing an NH3 gas and an O2 gas is supplied into the processing vessel as an etching gas, so as to perform etching by a plasma of the etching gas. When the etching gas is supplied into the processing vessel, a CD shift value of etching can be controlled by adjusting a flow ratio of O2 gas to the NH3 gas. Specifically, a satisfactory CD shift value can be obtained when the flow ratio is from 0.5 to 20%, and preferably, 5 to 10%.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: April 14, 2009
    Assignee: Tokyo Electron Limited
    Inventors: Shuhei Ogawa, Rie Inazawa, legal representative, Koichiro Inazawa
  • Patent number: 7514357
    Abstract: Electrical characteristics of a semiconductor device may be enhanced by completely removing a residue such as a polymer formed in a trench when the semiconductor device is manufactured by a method including: forming a via hole and a trench on a semiconductor substrate by an etching process; coating a photoresist on an entire surface of the semiconductor substrate such that the via hole and the trench may be filled thereby; removing a polymer defect in the trench while removing the coated photoresist by a plasma treatment under predetermined process conditions; and performing a wet cleaning process so as to remove a residue of the photoresist.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: April 7, 2009
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Bo-Yeoun Jo
  • Patent number: 7504643
    Abstract: A cleaning arrangement for a lithographic apparatus module may be provided in a collector. The cleaning arrangement includes a hydrogen radical source configured to provide a hydrogen radical containing gas to at least part of the module and a pump configured to pump gas through the module such that a flow speed of the hydrogen radical containing gas provided through at least part of the module is at least 1 m/s. The cleaning arrangement may also include a gas shutter configured to modulate a flow of the hydrogen radical containing gas to at least part of the module, a buffer volume of at least 1 m3 in communication with the module, and a pump configured to provide a gas pressure in the buffer volume between 0.001 mbar (0.1 Pa) and 1 mbar (100 Pa). The cleaning arrangement may further include a gas return system.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: March 17, 2009
    Assignee: ASML Netherlands B.V.
    Inventors: Johannes Maria Freriks, Vadim Yevgenyevich Banine, Vladimir Vitalevitch Ivanov, Derk Jan Wilfred Klunder, Maarten Marinus Johannes Wilhelmus Van Herpen
  • Patent number: 7498232
    Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece having a plurality of trenches formed therein, forming a liner over the workpiece, and forming a layer of photosensitive material over the liner. The layer of photosensitive material is removed from over the workpiece except from over at least a portion of each of the plurality of trenches. The layer of photosensitive material is partially removed from over the workpiece, leaving a portion of the layer of photosensitive material remaining within a lower portion of the plurality of trenches over the liner.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: March 3, 2009
    Assignee: Infineon Technologies AG
    Inventor: Josef Maynollo
  • Publication number: 20090053901
    Abstract: Plasma is generated using elemental hydrogen, a weak oxidizing agent, and a fluorine containing gas. An inert gas is introduced to the plasma downstream of the plasma source and upstream of a showerhead that directs gas mixture into the reaction chamber where the mixture reacts with the high-dose implant resist. The process removes both the crust and bulk resist layers at a high strip rate, and leaves the work piece surface substantially residue free with low silicon loss.
    Type: Application
    Filed: October 14, 2008
    Publication date: February 26, 2009
    Applicant: Novellus Systems Inc.
    Inventors: Haruhiro Harry Goto, David Cheung