Layer Comprising Polysiloxane Compound (epo) Patents (Class 257/E21.261)
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Patent number: 12180595Abstract: In examples, a method of forming a semiconductor package comprises forming a conversion coating solution comprising a salt of a vanadate, a salt of a zirconate, or both with a complexing agent; cleaning a copper lead frame, wherein the cleaned copper lead frame comprises copper oxide on an outer surface thereof; immersing the cleaned copper lead frame in the conversion coating solution; rinsing the copper lead frame; and forming an assembly by coupling a semiconductor die to the copper lead frame, coupling the semiconductor die to a lead of the copper lead frame, applying a mold compound onto at least a portion of the outer surface of the copper lead frame, and curing the mold compound. An adhesion strength at an interface between the mold compound and the at least the portion of the outer surface of the copper lead frame is increased relative to a same assembly formed without immersing the copper lead frame in the conversion coating solution.Type: GrantFiled: February 28, 2022Date of Patent: December 31, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Nazila Dadvand
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Patent number: 11920242Abstract: A temperature control method includes a switchover process, an ignition process, a slope calculation process, a first and a second control processes. In the switchover process, a heat medium to be supplied into a flow path is switched from a heat medium of a first temperature supplied from a first temperature controller to a heat medium of a second temperature supplied from a second temperature controller. In the slope calculation process, a slope of temperature change of the heat medium is calculated based on a temperature of the heat medium at an outlet side of the flow path. In the first control process, the second temperature controller is controlled until the temperature of the heat medium is stabilized to a temperature lower than a set value. In the second control process, the second temperature controller is controlled such that the temperature of the heat medium reaches the set value.Type: GrantFiled: March 10, 2021Date of Patent: March 5, 2024Assignee: TOKYO ELECTRON LIMITEDInventors: Yuya Minoura, Kaho Enomoto, Hayato Sakai
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Patent number: 10446495Abstract: Embodiments of the present inventive concepts provide methods of forming an ultra-low-k dielectric layer and the ultra-low-k dielectric layer formed thereby. The method may include forming a first layer by supplying a precursor including silicon, oxygen, carbon, and hydrogen, performing a first ultraviolet process on the first layer to convert the first layer into a second layer, and performing a second ultraviolet process on the second layer under a process condition different from that of the first ultraviolet process.Type: GrantFiled: March 1, 2018Date of Patent: October 15, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Yoonhee Kang, Jiyoung Kim, Taejin Yim, Jongmin Baek, Sanghoon Ahn, Hyeoksang Oh, Kyu-Hee Han
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Patent number: 10093830Abstract: A composition for forming a silica based layer includes a silicon-containing compound including polysilazane, polysiloxazane, or a combination thereof and one or more kinds of solvent, and having a turbidity increasing rate of less than or equal to about 0.13.Type: GrantFiled: September 1, 2015Date of Patent: October 9, 2018Assignee: Samsung SDI Co., Ltd.Inventors: Wan-Hee Lim, Taek-Soo Kwak, Han-Song Lee, Eun-Su Park, Sun-Hae Kang, Bo-Sun Kim, Sang-Kyun Kim, Sae-Mi Park, Jin-Hee Bae, Jin-Woo Seo, Jun-Young Jang, Youn-Jin Cho, Kwen-Woo Han, Byeong-Gyu Hwang
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Patent number: 9741966Abstract: Methods and apparatus for encapsulating organic light emitting diode (OLED) structures disposed on a substrate using a hybrid layer of material are provided. The encapsulation methods may be performed as single or multiple chamber processes. The processing parameters used during deposition of the hybrid layer of material allow control of the characteristics of the deposited hybrid layer. The hybrid layer may be deposited such that the layer has characteristics of an inorganic material in some sublayers of the hybrid layer and characteristics of an organic material in other sublayers of the hybrid layer. Use of the hybrid material allows OLED encapsulation using a single hard mask for the complete encapsulating process with low cost and without alignment issues present in conventional processes.Type: GrantFiled: June 24, 2016Date of Patent: August 22, 2017Assignee: APPLIED MATERIALS, INC.Inventors: Jrjyan Jerry Chen, Soo Young Choi
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Patent number: 9593224Abstract: Provided are porogen compositions and methods of using such porogen compositions in the manufacture of porous materials, for example, porous silicone elastomers. The porogens generally include comprising a core material and shell material different from the core material. The porogens can be used to form a scaffold for making a resulting porous elastomer when the scaffold is removed.Type: GrantFiled: October 1, 2014Date of Patent: March 14, 2017Assignee: Allergan, Inc.Inventors: Futian Liu, Nicholas J. Manesis, Xiaojie Yu, Athene Wan Chie Chan
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Patent number: 9447124Abstract: The present invention provides multi-thiol mercaptoalkoxysilane compositions and methods of making multi-thiol mercaptoalkoxysilane compositions having the formula: wherein the R3 group, and the R4 group are independently an alkoxy, a halogen, an alkyl, an aryl, a heteroaryl, a heterocycle or derivatives thereof and n is an integer between 1 and 30.Type: GrantFiled: December 17, 2015Date of Patent: September 20, 2016Assignee: Southern Methodist UniversityInventors: David Y. Son, Abby R. Jennings
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Patent number: 9355955Abstract: A semiconductor device is provided in which reliability of the semiconductor device is improved by improving an EM characteristic, a TDDB characteristic, and a withstand voltage characteristic of the semiconductor device. An average diameter of first vacancies in a lower insulating layer which configures an interlayer insulating film of a porous low-k film for embedding a wiring therein, is made smaller than an average diameter of second vacancies in an upper insulating layer, and thereby an elastic modulus is increased in the lower insulating layer. Further, a side wall insulating layer which is a dense layer including the first vacancies having an average diameter smaller than the second vacancies is formed on the surface of the interlayer insulating film exposed on a side wall of a wiring trench.Type: GrantFiled: May 1, 2015Date of Patent: May 31, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Naohito Suzumura, Yoshihiro Oka
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Patent number: 9343290Abstract: A method of manufacturing a semiconductor device includes forming an oxide film on a substrate by performing a cycle a predetermined number of times. The cycle includes supplying a precursor gas to the substrate; and supplying an ozone gas to the substrate. In the act of supplying the precursor gas, the precursor gas is supplied to the substrate in a state where a catalytic gas is not supplied to the substrate, and in the act of supplying the ozone gas, the ozone gas is supplied to the substrate in a state where an amine-based catalytic gas is supplied to the substrate.Type: GrantFiled: March 19, 2014Date of Patent: May 17, 2016Assignees: HITACHI KOKUSAI ELECTRIC, INC., L'AIR LIQUIDE, SOCIETE ANONYME POUR L'ETUDE ET L'EXPLOITATION DES PROCEDES GEORGES CLAUDEInventors: Yoshiro Hirose, Norikazu Mizuno, Kazutaka Yanagita, Shingo Okubo
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Patent number: 8790990Abstract: Provided is a silica-based film forming material for formation of air gaps, the material being capable of forming air gaps without employing a CVD method. A silica-based film forming material for formation of air gaps including (a) a certain siloxane polymer, (b) an alkanolamine, and (c) an organic solvent is used when a silica-based film is formed with a spin coating method. According to this silica-based film forming material for formation of air gaps, air gaps with a great degree of opening can be formed even when coated with a spin coating method, without filling the recessed parts.Type: GrantFiled: January 28, 2011Date of Patent: July 29, 2014Assignee: Tokyo Ohka Kogyo Co., Ltd.Inventor: Yoshihiro Sawada
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Patent number: 8736014Abstract: A semiconductor device and method for making such that provides improved mechanical strength is disclosed. The semiconductor device comprises a semiconductor substrate; an adhesion layer disposed over the semiconductor substrate; and a porous low-k film disposed over the semiconductor substrate, wherein the porous low-k film comprises a porogen and a composite bonding structure including at least one Si—O—Si bonding group and at least one bridging organic functional group.Type: GrantFiled: November 14, 2008Date of Patent: May 27, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bo-Jiun Lin, Ching-Yu Lo, Hai-Ching Chen, Tien-I Bao, Chen-Hua Yu
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Patent number: 8530360Abstract: A device including a first body (101) with terminals (102) on a surface (101a), each terminal having a metallic connector (110), which is shaped as a column substantially perpendicular to the surface. Preferably, the connectors have an aspect ratio of height to diameter of 2 to 1 or greater, and a fine pitch center-to-center. The connector end (110a) remote from the terminal is covered by a film (130) of a sintered paste including a metallic matrix embedded in a first polymeric compound. Further a second body (103) having metallic pads (140) facing the respective terminals (102). Each connector film (130) is in contact with the respective pad (140), whereby the first body (101) is spaced from the second body (103) with the connector columns (110) as standoff. A second polymeric compound (150) is filling the space of the standoff.Type: GrantFiled: January 25, 2011Date of Patent: September 10, 2013Assignee: Texas Instruments IncorporatedInventor: Abram M. Castro
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Patent number: 8445377Abstract: A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the substrate; and a low-k dielectric material located on a the treated surface layer of the substrate. The treated surface layer and the low-k dielectric material form an interface that has an adhesion strength that is greater than 60% of the cohesive strength of the weaker material on either side of the interface. The treated surface is formed by treating the surface of the substrate with at least one of actinic radiation, a plasma and e-beam radiation prior to forming of the substrate the low-k dielectric material.Type: GrantFiled: September 9, 2011Date of Patent: May 21, 2013Assignee: International Business Machines CorporationInventors: Qinghuang Lin, Terry A. Spooner, Darshan D. Gandhi, Christy S. Tyberg
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Patent number: 8319228Abstract: The present invention relates to a resin composition for optical semiconductor devices, the resin composition including the following ingredients (A) to (D): (A) an epoxy resin; (B) a curing agent; (C) a polyorganosiloxane; and (D) a white pigment.Type: GrantFiled: September 3, 2010Date of Patent: November 27, 2012Assignee: Nitto Denko CorporationInventors: Takashi Taniguchi, Kazuhiro Fuke, Hiroshi Noro, Hisataka Ito
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Patent number: 8237296Abstract: Organic anti-stiction coatings such as, for example, hydrocarbon and fluorocarbon based self-assembled organosilanes and siloxanes applied either in solvent or via chemical vapor deposition, are selectively etched using a UV-Ozone (UVO) dry etching technique in which the portions of the organic anti-stiction coating to be etched are exposed simultaneously to multiple wavelengths of ultraviolet light that excite and dissociate organic molecules from the anti-stiction coating and generate atomic oxygen from molecular oxygen and ozone so that the organic molecules react with atomic oxygen to form volatile products that are dissipated, resulting in removal of the exposed portions of the anti-stiction coating. A hybrid etching process using heat followed by UVO exposure may be used. A shadow mask (e.g., of glass or quartz), a protective material layer, or other mechanism may be used to selective expose the portions of the anti-stiction coating to be UVO etched.Type: GrantFiled: June 8, 2010Date of Patent: August 7, 2012Assignee: Analog Devices, Inc.Inventor: Mehmet Hancer
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Patent number: 8212345Abstract: A backgrinding machine 10 of a semiconductor wafer W includes: a table 13 set on the working plane of a mount 11; a multiple number of holding jigs 20 arranged via check tables 15 on table 13; a grinding machine 30 for performing a grinding process of the rear side of semiconductor wafer W held by holding jig 20; and a washing device 40 for ground semiconductor wafers W. Each holding jig 20 is constructed of a concave 22 depressed on the surface of a base plate 21, a multiple number of supporting projections 23 projectively arrayed on the bottom surface of concave 22, a deformable contact film 24, covering the concave 22, being supported by the multiple supporting projections 23, for detachably holding semiconductor wafer W in close contact with it; and an exhaust path 25 for conducting air from the concave 22 covered by contact film 24 to the outside.Type: GrantFiled: November 12, 2010Date of Patent: July 3, 2012Assignees: Shin-Etsu Polymer Co., Ltd., Lintec CorporationInventors: Kiyofumi Tanaka, Satoshi Odashima, Noriyoshi Hosono, Hironobu Fujimoto, Takeshi Segawa
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Patent number: 8101958Abstract: Embodiments relate to a semiconductor light-emitting device. The semiconductor light-emitting device comprises a plurality of compound semiconductor layers including a first 5 conductive semiconductor layer; an active layer on the first conductive semiconductor layer; and a second conductive semiconductor layer on the active layer; an electrode under the plurality of compound semiconductor layers; an electrode portion on the plurality of compound semiconductor layers; and a bending i0 prevention member comprising a pattern on the plurality of compound semiconductor layers.Type: GrantFiled: November 24, 2009Date of Patent: January 24, 2012Assignee: LG Innotek Co., Ltd.Inventor: Hwan Hee Jeong
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Patent number: 8035236Abstract: A semiconductor device comprising curable polyorganosiloxane composites is provided where the composites contain at least 0.1 wt % of the 4th and/or 13th group elements of the periodic table. The cured polyorganosiloxane composites may be catalyst-free, have increased stability, and can be used as encapsulation resin at a temperature far lower than 300° C., have excellent light transmission properties (colorless transparency) in a wavelength region of from ultraviolet light to visible light, light resistance, heat resistance, resistance to moist heat and UV resistance, and has excellent adhesiveness toward metal, ceramics, and plastic surfaces over a long period of time.Type: GrantFiled: October 16, 2009Date of Patent: October 11, 2011Assignees: The Regents of the University of California, Mitsubishi Chemical CorporationInventors: Craig J. Hawker, Hunaid Nulwala, Anika A. Odukale, Jeffrey A. Gerbec, Kenichi Takizawa
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Patent number: 8017522Abstract: A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the substrate; and a low-k dielectric material located on a the treated surface layer of the substrate. The treated surface layer and the low-k dielectric material form an interface that has an adhesion strength that is greater than 60% of the cohesive strength of the weaker material on either side of the interface. The treated surface is formed by treating the surface of the substrate with at least one of actinic radiation, a plasma and e-beam radiation prior to forming of the substrate the low-k dielectric material.Type: GrantFiled: January 24, 2007Date of Patent: September 13, 2011Assignee: International Business Machines CorporationInventors: Qinghuang Lin, Terry A. Spooner, Darshan D. Gandhi, Christy S. Tyberg
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Patent number: 7898083Abstract: A device including a first body (101) with terminals (102) on a surface (101a), each terminal having a metallic connector (110), which is shaped as a column substantially perpendicular to the surface. Preferably, the connectors have an aspect ratio of height to diameter of 2 to 1 or greater, and a fine pitch center-to-center. The connector end (110a) remote from the terminal is covered by a film (130) of a sintered paste including a metallic matrix embedded in a first polymeric compound. Further a second body (103) having metallic pads (140) facing the respective terminals (102). Each connector film (130) is in contact with the respective pad (140), whereby the first body (101) is spaced from the second body (103) with the connector columns (110) as standoff. A second polymeric compound (150) is filling the space of the standoff.Type: GrantFiled: January 29, 2009Date of Patent: March 1, 2011Assignee: Texas Instruments IncorporatedInventor: Abram M Castro
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Patent number: 7883986Abstract: This invention includes methods of forming trench isolation. In one implementation, isolation trenches are provided within a semiconductor substrate. A liquid is deposited and solidified within the isolation trenches to form a solidified dielectric within the isolation trenches. The dielectric comprises carbon and silicon, and can be considered as having an elevationally outer portion and an elevationally inner portion within the isolation trenches. At least one of carbon removal from and/or oxidation of the outer portion of the solidified dielectric occurs. After such, the dielectric outer portion is etched selective to and effective to expose the dielectric inner portion. After the etching, dielectric material is deposited over the dielectric inner portion to within the isolation trenches.Type: GrantFiled: October 1, 2009Date of Patent: February 8, 2011Assignee: Micron Technology, Inc.Inventor: Li Li
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Patent number: 7875501Abstract: A backgrinding machine 10 of a semiconductor wafer W includes: a table 13 set on the working plane of a mount 11; a multiple number of holding jigs 20 arranged via check tables 15 on table 13; a grinding machine 30 for performing a grinding process of the rear side of semiconductor wafer W held by holding jig 20; and a washing device 40 for ground semiconductor wafers W. Each holding jig 20 is constructed of a concave 22 depressed on the surface of a base plate 21, a multiple number of supporting projections 23 projectively arrayed on the bottom surface of concave 22, a deformable contact film 24, covering the concave 22, being supported by the multiple supporting projections 23, for detachably holding semiconductor wafer W in close contact with it; and an exhaust path 25 for conducting air from the concave 22 covered by contact film 24 to the outside.Type: GrantFiled: March 9, 2007Date of Patent: January 25, 2011Assignees: Shin-Etsu Polymer Co., Ltd., Lintec CorporationInventors: Kiyofumi Tanaka, Satoshi Odashima, Noriyoshi Hosono, Hironobu Fujimoto, Takeshi Segawa
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Patent number: 7691736Abstract: Embodiments of the invention provide a semiconductor device having dielectric material and its method of manufacture. A method comprises a short (?2 sec) flash activation of an ILD surface followed by flowing a precursor such as silane, DEMS, over the activated ILD surface. The precursor reacts with the activated ILD surface thereby selectively protecting the ILD surface. The protected ILD surface is resistant to plasma processing damage. The protected ILD surface eliminates the requirement of using a hard mask to protect a dielectric from plasma damage.Type: GrantFiled: February 10, 2006Date of Patent: April 6, 2010Assignee: Infineon Technologies AGInventors: Michael Beck, John A. Fitzsimmons, Karl Hornik, Darryl Restaino
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Patent number: 7687913Abstract: Often used to reduce the RC delay in integrated circuits are dielectric films of porous organosilicates which have a silica like backbone with alkyl or aryl groups (to add hydrophobicity to the materials and create free volume) attached directly to the Si atoms in the network. Si—R bonds rarely survive an exposure to plasmas or chemical treatments commonly used in processing; this is especially the case in materials with an open cell pore structure. When Si—R bonds are broken, the materials lose hydrophobicity, due to formation of hydrophilic silanols and low dielectric constant is compromised. A method by which the hydrophobicity of the materials is recovered using a novel class of silylation agents which may have the general formula (R2N)XSiR?Y where X and Y are integers from 1 to 3 and 3 to 1 respectively, and where R and R? are selected from the group of hydrogen, alkyl, aryl, allyl and a vinyl moiety. Mechanical strength of porous organosilicates is also improved as a result of the silylation treatment.Type: GrantFiled: February 19, 2007Date of Patent: March 30, 2010Assignee: International Business Machines CorporationInventors: Nirupama Chakrapani, Matthew E. Colburn, Christos D. Dimitrakopoulos, Dirk Pfeiffer, Sampath Purushothaman, Satyanarayana V. Nitta
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Patent number: 7682977Abstract: This invention includes methods of forming trench isolation. In one implementation, isolation trenches are provided within a semiconductor substrate. A liquid is deposited and solidified within the isolation trenches to form a solidified dielectric within the isolation trenches. The dielectric comprises carbon and silicon, and can be considered as having an elevationally outer portion and an elevationally inner portion within the isolation trenches. At least one of carbon removal from and/or oxidation of the outer portion of the solidified dielectric occurs. After such, the dielectric outer portion is etched selective to and effective to expose the dielectric inner portion. After the etching, dielectric material is deposited over the dielectric inner portion to within the isolation trenches.Type: GrantFiled: May 11, 2006Date of Patent: March 23, 2010Assignee: Micron Technology, Inc.Inventor: Li Li
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Patent number: 7582970Abstract: A semiconductor device includes an interlayer insulating film formed on or over a semiconductor substrate. An opening is formed in the interlayer insulating film and reaches a lower layer metal wiring conductor. A metal plug is formed by filling the opening with Cu containing metal via a barrier metal. The interlayer insulating film includes the insulating film which includes a carbon containing silicon oxide (SiOCH) film which has Si—CH2 bond in the carbon containing silicon oxide film. The proportion of Si—CH2 bond (1360 cm-1) to Si—CH3 bond (1270 cm-1) in the insulating film is in a range from 0.03 to 0.05 measured as a peak height ratio of FTIR spectrum.Type: GrantFiled: July 28, 2008Date of Patent: September 1, 2009Assignee: NEC Electronics CorporationInventors: Sadayuki Ohnishi, Kouichi Owto, Tatsuya Usami, Noboru Morita, Kouji Arita, Ryouhei Kitao, Youichi Sasaki
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Patent number: 7534717Abstract: The formation of an interlayer insulating film above a substrate, the formation of an insulating film of an organic material on the interlayer insulating film thereafter, and the irradiation of the insulating film of an organic material and the interlayer insulating film with electron beams, thereby curing at least the insulating film of an organic material, are proposed.Type: GrantFiled: March 31, 2005Date of Patent: May 19, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Hideshi Miyajima, Keiji Fujita, Hideaki Masuda, Rempei Nakata, Miyoko Shimada
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Patent number: 7517815Abstract: A spin-on glass composition includes a solvent, about 3 to about 20 percent by weight of a porogen, and about 3 to about 20 percent by weight of a silsesquioxane oligomer represented by formula (1), where, in the formula (1), Y1 and Y2 independently represent a hydrolyzable alkoxy group, R represents a lower alkyl group, and n and m independently represent an integer in a range of one to nine both inclusive.Type: GrantFiled: June 5, 2006Date of Patent: April 14, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Hyun Cho, Jung-Sik Choi, Jung-Ho Lee, Mi-Ae Kim
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Patent number: 7501353Abstract: Disclosed is a method for the formation of features in a damascene process. According to the method, vias are formed in a dielectric layer and then covered by a layer of high molecular weight polymer. The high molecular weight polymer covers the vias but does not enter the vias. A trench is then etched through the high molecular weight polymer and the dielectric layer. Any remaining high molecular weight polymer is then removed.Type: GrantFiled: December 22, 2006Date of Patent: March 10, 2009Assignee: International Business Machines CorporationInventors: Wai-Kin Li, Wu-Song Huang
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Patent number: 7482676Abstract: Low dielectric materials and films comprising same have been identified for improved performance when used as performance materials, for example, in interlevel dielectrics integrated circuits as well as methods for making same. In one aspect of the present invention, the performance of the dielectric material may be improved by controlling the weight percentage of ethylene oxide groups in the at least one porogen.Type: GrantFiled: July 11, 2006Date of Patent: January 27, 2009Assignee: Air Products and Chemicals, Inc.Inventors: Brian Keith Peterson, John Francis Kirner, Scott Jeffrey Weigel, James Edward MacDougall, Lisa Deis, Thomas Albert Braymer, Keith Douglas Campbell, Martin Devenney, C. Eric Ramberg, Konstantinos Chondroudis, Keith Cendak
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Patent number: 7468317Abstract: A method of forming a metal line, in which a nitride layer is used instead of a metal barrier layer, enabling a metal line structure with a relatively low resistance and therefore realizing a high integration of a device. In the method of forming the metal line of the semiconductor device, a first insulating layer and a second insulating layer with a different etch selectivity are sequentially formed on a semiconductor substrate. Predetermined regions of the first insulating layer and the second insulating layer are sequentially etched to form a contact hole. A metal barrier layer is formed on the entire surface including the contact hole. A first metal material is deposited on the entire surface to gap-fill the contact hole. The first metal material on the second insulating layer is stripped such that the first metal material remains only within the contact hole, thus forming a contact plug. A metal line is formed on a predetermined region of the second insulating layer including the contact plug.Type: GrantFiled: November 7, 2006Date of Patent: December 23, 2008Assignee: Hynix Semiconductor Inc.Inventors: Jik Ho Cho, Tae Kyung Kim
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Patent number: 7465682Abstract: A method for processing an organosiloxane film includes loading a target substrate (W) with a coating film formed thereon into a reaction chamber (2), and performing a heat process on the target substrate (W) within the reaction chamber (2) to bake the coating film. The coating film contains a polysiloxane base solution having an organic functional group. The heat process includes a temperature setting step of setting an interior of the reaction chamber (2) at a process temperature by heating, and a supplying step of supplying a baking gas into the reaction chamber (2) set at the process temperature, while activating the baking gas by a gas activation section (14) disposed outside the reaction chamber (2).Type: GrantFiled: April 20, 2004Date of Patent: December 16, 2008Assignee: Tokyo Electron LimitedInventor: Shingo Hishiya
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Patent number: 7445953Abstract: The invention relates to low temperature curable spin-on glass materials which are useful for electronic applications, such as optical devices. A substantially crack-free and substantially void-free silicon polymer film is produced by (a) preparing a composition comprising at least one silicon containing pre-polymer, a catalyst, and optionally water; (b) coating a substrate with the composition to form a film on the substrate, (c) crosslinking the composition by heating to produce a substantially crack-free and substantially void-free silicon polymer film, having a a transparency to light in the range of about 400 nm to about 800 nm of about 95% or more.Type: GrantFiled: July 29, 2005Date of Patent: November 4, 2008Assignee: Honeywell International Inc.Inventors: Victor Lu, Lei Jin, Arlene J. Suedmeyer, Paul G. Apen, Peter Alfred Smith, JingHong Chen
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Patent number: 7429789Abstract: A dielectric composition for forming a dielectric layer usable in circuitized substrates such as PCBs, chip carriers and the like, the composition including at least two fluoropolymers and two inorganic fillers. A circuitized substrate including at least one such dielectric layer and at least one conductive layer thereon is also provided.Type: GrantFiled: March 28, 2006Date of Patent: September 30, 2008Assignee: Endicott Interconnect Technologies, Inc.Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papathomas
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Patent number: 7420279Abstract: An insulating film used for an interlayer insulating film of a semiconductor device and having a low dielectric constant. The insulating film comprises a carbon containing silicon oxide (SiOCH) film which has Si—CH2 bond therein. The proportion of Si—CH2 bond (1360 cm?1) to Si—CH3 bond (1270 cm?1) in the insulating film is preferably in a range from 0.03 to 0.05 measured as a peak height ratio of FTIR spectrum. The insulating film according to the present invention has higher ashing tolerance and improved adhesion to SiO2 film, when compared with the conventional SiOCH film which only has CH3 group.Type: GrantFiled: June 28, 2006Date of Patent: September 2, 2008Assignee: NEC Electronics CorporationInventors: Sadayuki Ohnishi, Kouichi Ohto, Tatsuya Usami, Noboru Morita, Kouji Arita, Ryouhei Kitao, Youichi Sasaki
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Patent number: 7410914Abstract: The invention relates to processes for producing low-k dielectric films on semiconductors or electrical circuits, which comprises using incompletely condensed polyhedral oligomeric silsesquioxanes of the formula [(RaXbSiO1.Type: GrantFiled: June 2, 2004Date of Patent: August 12, 2008Assignee: Degussa AGInventors: Adolf Kuehnle, Carsten Jost, Hartwig Rauleder, Come Rentrop, Roelant Van Dam, Klaas Timmer, Hartmut Fischer
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Patent number: 7405153Abstract: A process for the formation of an interconnect in a semiconductor structure including the steps of forming a dielectric layer on a substrate, forming a first barrier layer on the dielectric layer, forming a second barrier layer on the first barrier layer, wherein the second barrier layer is selected from the group consisting of ruthenium, platinum, palladium, rhodium and iridium and wherein the formation of the second barrier layer is manipulated so that the bulk concentration of oxygen in the second barrier layer is 20 atomic percent or less, and forming a conductive layer on the second barrier layer. The process may additionally include a step of treating the second barrier to reduce the amount of oxide on the surface of the second barrier layer.Type: GrantFiled: January 17, 2006Date of Patent: July 29, 2008Assignee: International Business Machines CorporationInventors: Sandra G. Malhotra, Hariklia Deligianni, Stephen M. Rossnagel, Xiaoyan Shao, Tsong-Lin Tai, Oscar van der Straten
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Patent number: 7399715Abstract: A method of forming an organic silica-based film, including: applying a composition for forming an insulating film for a semiconductor device, which is cured by using heat and ultraviolet radiation, to a substrate to form a coating; heating the coating; and applying heat and ultraviolet radiation to the coating to effect a curing treatment, wherein the composition includes organic silica sol having a carbon content of 11.8 to 16.7 mol %, and an organic solvent, the organic silica sol being a hydrolysis-condensation product produced by hydrolysis and condensation of a silane compound selected from compounds shown by the general formulae (1): R1Si(OR2)3, (2): Si(OR3)4, (3): (R4)2Si(OR5)2, and (4): R6b(R7O)3-bSi—(R10)d—Si(OR8)3-cR9c.Type: GrantFiled: July 8, 2005Date of Patent: July 15, 2008Assignee: JSR CorporationInventors: Hajime Tsuchiya, Hiromi Egawa, Terukazu Kokubo, Atsushi Shiota
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Patent number: 7396749Abstract: The invention relates to a method for contacting parts of a component integrated into a semiconductor substrate (1). According to the inventive method, a first contact hole is produced in an insulating layer (2), said contact hole being then filled with contact material (16) and connected to a line. The aim of the invention is to minimise the processes required for contacting parts of a component integrated into a semiconductor substrate. To this end, the hard mask (3) used to produce the contact hole is also used to structure the line.Type: GrantFiled: June 24, 2003Date of Patent: July 8, 2008Assignee: Infineon Technologies AGInventors: Ludwig Dittmar, Wolfgang Gustin, Maik Stegemann
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Patent number: 7364942Abstract: This invention discloses a process for forming durable anti-stiction surfaces on micromachined structures while they are still in wafer form (i.e., before they are separated into discrete devices for assembly into packages). This process involves the vapor deposition of a material to create a low stiction surface. It also discloses chemicals which are effective in imparting an anti-stiction property to the chip. These include polyphenylsiloxanes, silanol terminated phenylsiloxanes and similar materials.Type: GrantFiled: April 12, 2007Date of Patent: April 29, 2008Assignee: Analog Devices, Inc.Inventor: John R. Martin
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Patent number: 7345351Abstract: The present invention relates to a coating composition for insulating film production, a preparation method of a low dielectric insulating film using the same, a low dielectric insulating film for a semiconductor device prepared therefrom, and a semiconductor device comprising the same, and more particularly to a coating composition for insulating film production having a low dielectric constant and that is capable of producing an insulating film with superior mechanical strength (elasticity), a preparation method of a low dielectric insulating film using the same, a low dielectric insulating film for a semiconductor device prepared therefrom, and a semiconductor device comprising the same. The coating composition of the present invention comprises an organic siloxane resin having a small molecular weight, and water, and significantly improves low dielectricity and mechanical strength of an insulating film.Type: GrantFiled: March 31, 2004Date of Patent: March 18, 2008Assignee: LG Chem, Ltd.Inventors: Myung-Sun Moon, Min-Jin Ko, Hye-Yeong Nam, Jung-Won Kang, Bum-Gyu Choi, Byung-Ro Kim, Gwi-Gwon Kang, Young-Duk Kim, Sang-Min Park
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Patent number: 7294585Abstract: Low dielectric materials and films comprising same have been identified for improved performance when used as performance materials, for example, in interlevel dielectrics integrated circuits as well as methods for making same. In one aspect of the present invention, the performance of the dielectric material may be improved by controlling the weight percentage of ethylene oxide groups in the at least one porogen.Type: GrantFiled: July 11, 2006Date of Patent: November 13, 2007Assignee: Air Products and Chemicals, Inc.Inventors: Brian Keith Peterson, John Francis Kirner, Scott Jeffrey Weigel, James Edward MacDougall, Lisa Deis, legal representative, Thomas Albert Braymer, Keith Douglas Campbell, Martin Devenney, C. Eric Ramberg, Konstantinos Chondroudis, Keith Cendak, Thomas Alan Deis, deceased
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Patent number: 7279728Abstract: A capacitance device includes a dielectric film, the first electrode and the second electrode. One of the two electrodes is divided into a plurality of electrode portions. Each of the divided electrode portions is connected with each other through switching transistors so that appropriate portions contributing to the capacitance can be selected. The device can vary its capacitance with high accuracy.Type: GrantFiled: June 14, 2005Date of Patent: October 9, 2007Assignees: DENSO CORPORATION, NIPPON SOKEN, INC.Inventors: Toshikazu Itakura, Toshiki Isogai
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Publication number: 20070181938Abstract: A field-effect transistor includes source, drain, and gate electrodes; a crystalline or polycrystalline layer of inorganic semiconductor; and a dielectric layer. The layer of inorganic semiconductor has an active channel portion physically extending from the source electrode to the drain electrode. The inorganic semiconductor has a stack of 2-dimensional layers in which intra-layer bonding forces are covalent and/or ionic. Adjacent ones of the layers are bonded together by forces substantially weaker than covalent and ionic bonding forces. The dielectric layer is interposed between the gate electrode and the layer of inorganic semiconductor material. The gate electrode is configured to control a conductivity of an active channel part of the layer of inorganic semiconductor.Type: ApplicationFiled: April 4, 2007Publication date: August 9, 2007Inventors: Ernst Bucher, Michael Gershenson, Christian Kloc, Vitaly Podzorov
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Patent number: 7238626Abstract: A method of stabilizing a poly(paraxylylene) dielectric thin film after forming the dielectric thin film via transport polymerization is disclosed, wherein the method includes annealing the dielectric thin film under at least one of a reductive atmosphere and a vacuum at a temperature above a reversible solid phase transition temperature of the dielectric film to convert the film from a lower temperature phase to a higher temperature phase, and cooling the dielectric thin film at a sufficient rate to a temperature below the solid phase transition temperature of the dielectric thin film to trap substantial portions of the film in the higher temperature phase.Type: GrantFiled: December 21, 2004Date of Patent: July 3, 2007Assignee: Dielectric Systems, Inc.Inventors: Chung J. Lee, Atul Kumar
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Patent number: 7220614Abstract: This invention discloses a process for forming durable anti-stiction surfaces on micromachined structures while they are still in wafer form (i.e., before they are separated into discrete devices for assembly into packages). This process involves the vapor deposition of a material to create a low stiction surface. It also discloses chemicals which are effective in imparting an anti-stiction property to the chip. These include polyphenylsiloxanes, silanol terminated phenylsiloxanes and similar materials.Type: GrantFiled: June 9, 2003Date of Patent: May 22, 2007Assignee: Analog Devices, Inc.Inventor: John R. Martin
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Publication number: 20070042611Abstract: A method of producing a trench in a photo-resist on a III-V wafer comprising providing a III-V wafer; providing a photo-resist on the wafer; exposing the photo-resist to UV radiation through a mask; removing one of the exposed or non-exposed portions of the photo-resist to produce a recess; applying a polymer spacer to the photo-resist; heating the wafer to initiate a polymer cross linking reaction at the interface of the photo-resist and polymer; and removing the un-reacted polymer.Type: ApplicationFiled: August 18, 2006Publication date: February 22, 2007Inventor: Jason McMonagle
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Patent number: 7135398Abstract: An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.Type: GrantFiled: July 29, 2004Date of Patent: November 14, 2006Assignee: International Business Machines CorporationInventors: John A. Fitzsimmons, Stephen E. Greco, Jia Lee, Stephen M. Gates, Terry Spooner, Matthew S. Angyal, Habib Hichri, Theordorus E. Standaert, Glenn A. Biery
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Patent number: 7122880Abstract: Low dielectric materials and films comprising same have been identified for improved performance when used as performance materials, for example, in interlevel dielectrics integrated circuits as well as methods for making same. In one aspect of the present invention, the performance of the dielectric material may be improved by controlling the weight percentage of ethylene oxide groups in the at least one porogen.Type: GrantFiled: May 20, 2003Date of Patent: October 17, 2006Assignee: Air Products and Chemicals, Inc.Inventors: Brian Keith Peterson, John Francis Kirner, Scott Jeffrey Weigel, James Edward MacDougall, Lisa Deis, Thomas Albert Braymer, Keith Douglas Campbell, Martin Devenney, C. Eric Ramberg, Konstantinos Chondroudis, Keith Cendak
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Publication number: 20060188664Abstract: A coating composition for the formation of a low refractive index layer, comprising: a fluorine-containing olefin-based polymer that has a polysiloxane segment represented by formula 1 in its main chain, has a fluorine content of 30 mass % or more, and contains a plurality of ethylenically unsaturated groups; and a hollow silica fine particle having an average particle diameter of 5 to 200 nm and a refractive index of 1.17 to 1.40: Formula 1: [wherein R1 and R2, which may be the same or different, each represents a hydrogen atom, an alkyl group, an alkyl halide group or an aryl group].Type: ApplicationFiled: February 21, 2006Publication date: August 24, 2006Applicant: FUJI PHOTO FILM CO., LTD.Inventors: Takumi Ando, Yuuichi Fukushige