Organic Layers, E.g., Photoresist (epo) Patents (Class 257/E21.259)
  • Patent number: 10829665
    Abstract: A method of forming a self-cleaning film system includes depositing a photocatalytic material onto a substrate to form a first layer. The method also includes disposing a photoresist onto the first layer and then exposing the photoresist to light so that the photoresist has a developed portion and an undeveloped portion. The method includes removing the undeveloped portion so that the developed portion protrudes from the first layer. After removing, the method includes depositing a perfluorocarbon siloxane polymer onto the first layer to surround and contact the developed portion. After depositing the perfluorocarbon siloxane polymer, the method includes removing the developed portion to thereby form the self-cleaning film system.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: November 10, 2020
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Gayatri V. Dadheech, Thomas A. Seder, James A. Carpenter
  • Patent number: 10790135
    Abstract: There is provided a method of manufacturing a semiconductor device by performing a process on a substrate, comprising: forming a sacrificial film made of a polymer having a urea bond on a surface of the substrate by supplying a precursor for polymerization onto the surface of the substrate; subsequently, performing a step of changing a sectional shape of the sacrificial film and a step of adjusting a film thickness of the sacrificial film by heating the sacrificial film; subsequently, performing the process on the surface of the substrate; and subsequently, removing the sacrificial film.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: September 29, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tatsuya Yamaguchi, Reiji Niino, Syuji Nozawa, Makoto Fujikawa
  • Patent number: 10692782
    Abstract: Provided is a control device for controlling an operation of a substrate processing apparatus that forms a predetermined film on a substrate and operations of a plurality of measurement devices that measure a characteristic of the predetermined film. The control device includes: an individual difference information storing unit that stores individual difference information representing a relationship between information allocated to each of the plurality of measurement devices to specify each measurement device and an individual difference of the measurement device; and a controller that corrects a measurement value of the characteristic of the predetermined film measured by the measurement device based on information specifying the measurement device that has measured the characteristic of the predetermined film and the individual difference information stored in the individual difference information storing unit.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: June 23, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yuichi Takenaga, Takahito Kasai, Yozo Nagata
  • Patent number: 10615036
    Abstract: A process for fabricating an integrated circuit is provided. The process includes providing a substrate, forming a hard mask upon the substrate by one of atomic-layer deposition and molecular-layer deposition, and exposing the hard mask to a charged particle from one or more charged particle beams to pattern a gap in the hard mask. In the alternative, the process includes exposing the hard mask to a charged particle from one or more charged-particle beams to pattern a structure on the hard mask.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: April 7, 2020
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Kuen-Yu Tsai, Miin-Jang Chen, Samuel C. Pan
  • Patent number: 10481711
    Abstract: An array substrate comprises the plurality of gate lines and matrix arranged touch electrodes, which each of the touch electrodes has a plurality of sub electrodes, and each of the sub electrode and the gate line extend along the first direction, the plurality of the sub electrode are arranged in spaced arrangement along the second direction. The first direction and the second direction are perpendicular each other, and the plurality of the sub electrodes electrically connected to each other by the first touch trace, and the shadow of the gate line on the touch electrode is between two of the sub electrodes. The touch electrode is separated into the plurality of sub electrode arranged in spaced arrangement. The shadow of the gate line on the touch electrode is between the two sub electrodes, and the touch electrode avoids the gate line.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: November 19, 2019
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd
    Inventors: Yao-li Huang, Hongsen Zhang, Pan Yang
  • Patent number: 10281628
    Abstract: A method of preparing a photochromic optical article is provided, which includes: (i) applying a first organic solvent to a surface of an optical substrate, thereby forming an organic solvent wetted surface on the optical substrate; and (ii) applying a curable photochromic coating composition over the organic solvent wetted surface of said optical substrate, thereby forming a curable photochromic coating layer over the surface of the optical substrate. The curable photochromic coating composition includes a second organic solvent, and the first and second organic solvents are miscible with each other. With some embodiments, the first and second organic solvents are the same.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: May 7, 2019
    Assignee: Transitions Optical, Inc.
    Inventors: Jerry L. Koenig, II, Joseph David Turpen, Glen Todd Owens, Nancyanne Gruchacz
  • Patent number: 10262951
    Abstract: A novel radiation hardened chip package technology protects microelectronic chips and systems in aviation/space or terrestrial devices against high energy radiation. The proposed technology of a radiation hardened chip package using rare earth elements and mulitlayered structure provides protection against radiation bombardment from alpha and beta particles to neutrons and high energy electromagnetic radiation.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: April 16, 2019
    Assignees: National Institute of Aerospace Associates, The United States of America as represented by the Administrator of NASA
    Inventors: Jin Ho Kang, Godfrey Sauti, Cheol Park, Luke Gibbons, Sheila Ann Thibeault, Sharon E. Lowther, Robert G. Bryant
  • Patent number: 10249545
    Abstract: A method for processing a substrate exposes a silicon-containing surface at a circumferential edge portion of a first main surface of a substrate to be processed, performs surface processing to the silicon-containing surface to increase a contact angle of the silicon-containing surface with respect to a resist material, comparing with the contact angle before the surface processing is performed, supplies the resist material onto the substrate to be processed after the surface processing, and transfers a template pattern to the resist material.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: April 2, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Nobuyoshi Sato
  • Patent number: 10068765
    Abstract: A multi-step system and method for curing a dielectric film in which the system includes a drying system configured to reduce the amount of contaminants, such as moisture, in the dielectric film. The system further includes a curing system coupled to the drying system, and configured to treat the dielectric film with ultraviolet (UV) radiation and infrared (IR) radiation in order to cure the dielectric film.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: September 4, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Junjun Liu, Eric M. Lee, Dorel I. Toma
  • Patent number: 10056363
    Abstract: The present disclosure includes systems and techniques relating to methods and systems that improve yield in multiple chips integration processes. In some implementations, a method includes providing, in a chamber, a first integrated circuit chip and a second integrated circuit chip supported on a carrier, flowing a molding compound to cover the first integrated circuit chip, the second integrated circuit chip, and the carrier; and flowing a forming gas into the chamber while curing the molding compound.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: August 21, 2018
    Assignee: Marvell World Trade Ltd.
    Inventors: Runzi Chang, Winston Lee
  • Patent number: 9997703
    Abstract: A resistive memory device includes a bottom electrode and a top electrode sandwiching a switching layer. The device also includes a field enhancement (FE) feature that extends from the bottom electrode either into the switching layer or is covered by switching layer and that is to enhance an electric field generated by the two electrodes to thereby confine a switching area of the device at the FE feature. The device further includes a planar interlayer dielectric surrounding the device, for supporting the top electrode. A method of making a resistive memory device, employing in-situ vacuum deposition of all layers, is also provided.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: June 12, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Si-Ty Lam, Xia Sheng, Richard H. Henze, Zhang-Lin Zhou
  • Patent number: 9965851
    Abstract: The inventive concepts provide a method for inspecting a pattern, a method for manufacturing a semiconductor device, and an apparatus used according to the methods. The method for inspecting a pattern includes detecting a measured image corresponding to a pattern formed on a substrate, detecting a first hot spot corresponding to a ghost image of the measured image, with the first hot spot representing a defect of the pattern, and detecting a second hot spot that has an area that is wider than that of the first hot spot.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: May 8, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kaiyuan Chi, Kiho Yang, Seunghune Yang
  • Patent number: 9949416
    Abstract: An implantable device includes an exterior gold surface and a thin film disposed on the exterior gold surface and forming a barrier between the exterior gold surface and an implanted environment, in which the thin film includes molecules with a head portion, the head portion attached to the exterior gold surface.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: April 17, 2018
    Assignee: ADVANCED BIONICS AG
    Inventor: Kurt J. Koester
  • Patent number: 9837558
    Abstract: A concentrator photovoltaic module 1M includes a vessel-shaped housing 11 composed of a metal and a flexible printed wiring board 12 provided so as to be in contact with an inner surface of the housing 11. The flexible printed wiring board 12 includes an insulating layer 124, an insulating substrate 121a, a pattern 121b, a plurality of power generation elements 122, and an insulting layer 126. The insulating layer 124 is in contact with a bottom surface 11a of the housing 11. The insulating substrate 121a is provided on the insulating layer 124 and has flexibility. The pattern 121b is composed of a conductor and is provided on the insulating substrate 121a. The plurality of power generation elements 122 are mounted on the pattern 121b. The insulating layer 126 is provided so as to cover an entire surface of the pattern 121b except for portions where the power generation elements 122 are mounted.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: December 5, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Youichi Nagai, Takashi Iwasaki, Kazumasa Toya, Kenji Saito, Kenichi Hirotsu, Hideaki Nakahata
  • Patent number: 9708507
    Abstract: A method for improving a chemical resistance of a polymerized film, which is formed on a surface of a target object and to be processed by a chemical, includes: consecutively performing a treatment for improving the chemical resistance of the polymerized film subsequent to formation of the polymerized film within a processing chamber of a film forming apparatus where the polymerized film is formed, without unloading the target object from the processing chamber.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: July 18, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kippei Sugita, Tatsuya Yamaguchi, Yoshinori Morisada, Makoto Fujikawa
  • Patent number: 9640401
    Abstract: A method of manufacturing a semiconductor device includes forming a cavity in a first semiconductor layer formed on a semiconducting base layer, the cavity extending from a process surface of the first semiconductor layer at least down to the base layer, forming a recessed mask liner on a portion of a sidewall of the cavity distant to the process surface or a mask plug in a portion of the cavity distant to the process surface, and growing a second semiconductor layer on the process surface by epitaxy, the second semiconductor layer spanning the cavity.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: May 2, 2017
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Hans-Joachim Schulze, Anton Mauder, Erich Griebl
  • Patent number: 9613880
    Abstract: A method for fabricating a semiconductor structure includes: providing a substrate with a dielectric layer and a passivation layer formed on the substrate; forming a via through the dielectric layer and exposing the substrate; forming a first conductive layer to fill the via with a top surface of the first conductive layer leveled with a top surface of the passivation layer; forming a patterned layer with an opening on the passivation layer. The opening is located above the first conductive layer with a dimension larger than the dimension of the via. The method also includes forming a trench in the dielectric layer; forming a second conductive layer to fill the trench and to electrically connect to the first conductive layer; then removing a portion of the second conductive layer, the patterned layer, and the passivation layer to make a top surface of the second conductive layer level with a top surface of the dielectric layer.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: April 4, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Chenglong Zhang, Haiyang Zhang
  • Patent number: 9613849
    Abstract: Disclosed is a composite substrate manufacturing method whereby, after bonding a semiconductor substrate (1) and a supporting substrate (3) to each other, the semiconductor substrate (1) is thinned, and a composite substrate (8) having a semiconductor layer (6) on the supporting substrate (3) is obtained. On the supporting substrate (3) surface to be bonded, a coating film (4a) containing polysilazane is formed, a silicon-containing insulating film (4) is formed by performing firing by heating the coating film (4a) to 600-1,200° C., then, the semiconductor substrate (1) and the supporting substrate (3) are bonded to each other with the insulating film (4) therebetween, thereby suppressing bonding failures due to surface roughness and defects of the supporting substrate, and easily obtaining the composite substrate.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: April 4, 2017
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Shigeru Konishi, Shozo Shirai
  • Patent number: 9606436
    Abstract: A photosensitive resin composition includes an alkali-soluble resin (A), a compound having an unsaturated vinyl group (B), a photo initiator (C), solvent (D) and a silane compound (E) having a structure shown as formula (I): in the formula (I), A individually and independently represents a single bond, an alkylene group, or an arylene group, B individually and independently represents an organic group having diphenyl phosphine, hydrogen atom, an alkyl group, an aryl group, or —OR, in which R is a C1-C6 alkyl group or a phenyl group, at least one B is the organic group having diphenyl phosphine and at least one B is —OR. When B is —OR, A connected to B is the single bond. A film formed by the photosensitive resin composition has good refractivity and adhesivity to molybdenum.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: March 28, 2017
    Assignee: CHI MEI CORPORATION
    Inventors: Yu-Jie Tsai, I-Kuang Chen
  • Patent number: 9595468
    Abstract: To provide a semiconductor device having improved reliability. After formation of a first insulating film for an interlayer insulating film by spin coating, the surface of the first insulating film is subjected to a hydrophilicity improving treatment. A second insulating film for the interlayer insulating film is then formed on the first insulating film by spin coating. The interlayer insulating film is comprised of a stacked insulating film including the first insulating film and the second insulating film thereon. The interlayer insulating film therefore can have improved surface flatness.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: March 14, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshikazu Hanawa, Kazuhide Fukaya
  • Patent number: 9558930
    Abstract: In one aspect, a method of forming a wiring layer on a wafer is provided which includes: depositing a HSQ layer onto the wafer; cross-linking a first portion(s) of the HSQ layer using e-beam lithography; depositing a hardmask material onto the HSQ layer; patterning the hardmask using optical lithography, wherein the patterned hardmask covers a second portion(s) of the HSQ layer; patterning the HSQ layer using the patterned hardmask in a manner such that i) the first portion(s) of the HSQ layer remain and ii) the second portion(s) of the HSQ layer covered by the patterned hardmask remain, wherein by way of the patterning step trenches are formed in the HSQ layer; and filling the trenches with a conductive material to form the wiring layer on the wafer.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: January 31, 2017
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Szu-Lin Cheng, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 9514932
    Abstract: Methods are described for forming flowable carbon layers on a semiconductor substrate. A local excitation (such as a hot filament in hot wire CVD, a plasma in PECVD or UV light) may be applied as described herein to a silicon-free carbon-containing precursor containing a hydrocarbon to form a flowable carbon-containing film on a substrate. A remote excitation method has also been found to produce flowable carbon-containing films by exciting a stable precursor to produce a radical precursor which is then combined with unexcited silicon-free carbon-containing precursors in the substrate processing region.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: December 6, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Abhijit Basu Mallick, Nitin K. Ingle
  • Patent number: 9360725
    Abstract: An element substrate is provided, including a substrate, a metal layer and a planarization layer. The metal layer is located on the substrate. The metal layer has a first edge in a first direction. The planarization layer is located on the metal layer. The planarization layer includes a contact hole. The contact hole has a contiguous wall and a bottom side. The metal layer is exposed in the bottom side. A contour line of the contiguous wall on a vertical plane is a curved line. The first edge corresponds vertically with a critical point on the contour line. The slope of a tangent line on the critical point of the contour line is smaller than 0.176.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: June 7, 2016
    Assignee: INNOLUX CORPORATION
    Inventors: Yueh-Ting Chung, Jyun-Yu Chen, Wei-Chen Hsu, Yung-Hsin Lu, Chao Hsiang Wang, Kuan Yu Chiu
  • Patent number: 9348219
    Abstract: Provided herein are methods for depositing a spin-on-glass composition over an imprinted resist; curing the spin-on-glass composition to form a cured spin-on-glass composition; and forming a patterned mask by etching the cured spin-on-glass composition, the resist, and an underlying mask composition, wherein the patterned mask comprises features of the cured spin-on-glass composition atop the mask composition, and wherein curing the spin-on-glass composition is configured to prevent shifting or toppling of the spin-on glass composition from atop the mask composition while forming the patterned mask.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: May 24, 2016
    Assignee: Seagate Technology LLC
    Inventors: Zhaoning Yu, Nobuo Kurataka, Gennady Gauzner
  • Patent number: 9312195
    Abstract: A first photosensitive organic insulating film (PO1) formed in contact with a passivation film (PL) covers the entire circumference of a stepped portion (TRE) at a surface of the passivation film PL formed by a topmost conductive layer (TCL) and has an outer circumferential edge (ED1) positioned, along the entire circumference, on the outer circumferential side with respect to the stepped portion (TRE). This can prevent the first photosensitive organic insulating film (PO1) from peeling off the passivation film (PL).
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: April 12, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Kazuo Tomita
  • Patent number: 9231061
    Abstract: The invention relates to a new method of texturing silicon surfaces suited for antireflection based on ion implantation of hydrogen and heavy ions or heavy elements combined with thermal annealing or thermal annealing and oxidation. The addition of the heavy ions or heavy elements allows for a more effective anti-reflective surface than is found when only hydrogen implantation is utilized. The methods used are also time- and cost-effective, as they can utilize already existing semiconductor ion implantation fabrication equipment and reduce the number of necessary steps. The antireflective surfaces are useful for silicon-based solar cells.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: January 5, 2016
    Assignee: The Research Foundation of State University of New York
    Inventors: Mengbing Huang, Nirag Kadakia, Sebastian Naczas, Hassaram Bakhru
  • Patent number: 9041181
    Abstract: A land grid array (LGA) package including a substrate having a plurality of lands formed on a first surface of the substrate, a semiconductor chip mounted on a second surface of the substrate, a connection portion connecting the semiconductor chip and the substrate, and a support layer formed on part of a surface of a first land.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: May 26, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hee-chul Lee, Myung-kee Chung, Kun-dae Yeom
  • Patent number: 8999862
    Abstract: Methods of fabricating nano-scale structures are provided. A method includes forming a first hard mask pattern corresponding to first openings in a dense region, forming first guide elements on the first hard mask pattern aligned with the first openings, and forming second hard mask patterns in a sparse region to provide isolated patterns. A blocking layer is formed in the sparse region to cover the second hard mask patterns. A first domain and second domains are formed in the dense region using a phase separation of a block co-polymer layer. Related nano-scale structures are also provided.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: April 7, 2015
    Assignee: SK Hynix Inc.
    Inventors: Keun Do Ban, Cheol Kyu Bok, Myoung Soo Kim, Jung Hyung Lee, Hyun Kyung Shim, Chang Il Oh
  • Patent number: 8994177
    Abstract: A method for far back end of the line (FBEOL) protection of a semiconductor device includes forming a patterned layer over a back end of the line (BEOL) stack, depositing a first conformal protection layer on the patterned layer which covers horizontal surfaces of a top surface and sidewalls of openings formed in the patterned layer. A resist layer is patterned over the first conformal protection layer such that openings in the resist layer correspond with the openings in the patterned layer. The first conformal protection layer is etched through the openings in the resist layer to form extended openings that reach a stop position. The resist layer is removed, and a second conformal protection layer is formed on the first conformal protection layer and on sidewalls of the extended openings to form an encapsulation boundary to protect at least the patterned layer and a portion of the BEOL stack.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Tymon Barwicz, Robert L. Bruce, Swetha Kamlapurkar
  • Patent number: 8987095
    Abstract: The disclosure relates to integrated circuit fabrication and, more particularly, to a semiconductor device with a high-k gate dielectric layer. An exemplary structure for a semiconductor device comprises a substrate and a gate structure disposed over the substrate. The gate structure comprises a dielectric portion and an electrode portion that is disposed over the dielectric portion, and the dielectric portion comprises a carbon-doped high-k dielectric layer on the substrate and a carbon-free high-k dielectric layer adjacent to the electrode portion.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kun-Yu Lee, Liang-Gi Yao, Yasutoshi Okuno, Clement Hsingjen Wann
  • Patent number: 8951917
    Abstract: The invention provides a composition for forming a silicon-containing resist underlayer film comprising: (A) a silicon-containing compound obtained by a hydrolysis-condensation reaction of a mixture containing, at least, one or more hydrolysable silicon compound shown by the following general formula (1) and one or more hydrolysable compound shown by the following general formula (2), and (B) a silicon-containing compound obtained by a hydrolysis-condensation reaction of a mixture containing, at least, one or more hydrolysable silicon compound shown by the following general formula (3) and one or more hydrolysable silicon compound shown by the following general formula (4).
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: February 10, 2015
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Tsutomu Ogihara, Takafumi Ueda, Toshiharu Yano, Fujio Yagihashi
  • Patent number: 8932956
    Abstract: A method for far back end of the line (FBEOL) protection of a semiconductor device includes forming a patterned layer over a back end of the line (BEOL) stack, depositing a first conformal protection layer on the patterned layer which covers horizontal surfaces of a top surface and sidewalls of openings formed in the patterned layer. A resist layer is patterned over the first conformal protection layer such that openings in the resist layer correspond with the openings in the patterned layer. The first conformal protection layer is etched through the openings in the resist layer to form extended openings that reach a stop position. The resist layer is removed, and a second conformal protection layer is formed on the first conformal protection layer and on sidewalls of the extended openings to form an encapsulation boundary to protect at least the patterned layer and a portion of the BEOL stack.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Tymon Barwicz, Robert L. Bruce, Swetha Kamlapurkar
  • Patent number: 8912540
    Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: December 16, 2014
    Assignee: Renesas Electronics Corporations
    Inventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
  • Patent number: 8884377
    Abstract: In one embodiment, first and second pattern structures respectively include first and second conductive line patterns and first and second hard masks sequentially stacked, and at least portions thereof extends in a first direction. The insulation layer patterns contact end portions of the first and second pattern structures. The first pattern structure and a first insulation layer pattern of the insulation layer patterns form a first closed curve shape in plan view, and the second pattern structure and a second insulation layer pattern of the insulation layer patterns form a second closed curve shape in plan view. The insulating interlayer covers upper portions of the first and second pattern structures and the insulation layer patterns, a first air gap between the first and second pattern structures, and a second air gap between the insulation layer patterns.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sok-Won Lee, Joon-Hee Lee, Jung-Dal Choi, Seong-Min Jo
  • Patent number: 8883646
    Abstract: The present disclosure is directed to a process for the fabrication of a semiconductor device. In some embodiments the semiconductor device comprises a patterned surface. The pattern can be formed from a self-assembled monolayer. The disclosed process provides self-assembled monolayers which can be deposited quickly, thereby increasing production throughput and decreasing cost, as well as providing a pattern having substantially uniform shape.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee, Chien-Hua Huang
  • Patent number: 8828886
    Abstract: Disclosed is a low dielectric constant insulating film formed of a polymer containing Si atoms, O atoms, C atoms, and H atoms, which includes straight chain molecules in which a plurality of basic molecules with an SiO structure are linked in a straight chain, binder molecules with an SiO structure linking a plurality of the straight chain molecules. The area ratio of a signal indicating a linear type SiO structure is 49% or more, and the signal amount of the signal indicating Si(CH3) is 66% or more.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: September 9, 2014
    Assignee: Tohoku University
    Inventors: Seiji Samukawa, Shigeo Yasuhara, Shingo Kadomura, Tsutomu Shimayama, Hisashi Yano, Kunitoshi Tajima, Noriaki Matsunaga, Masaki Yoshimaru
  • Patent number: 8802569
    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of circuit devices over a substrate. The method includes forming an organic layer over the substrate. The organic layer is formed over the plurality of circuit devices. The method includes polishing the organic layer to planarize a surface of the organic layer. The organic layer is free of being thermally treated prior to the polishing. The organic material is un-cross-linked during the polishing. The method includes depositing a LT-film over the planarized surface of the organic layer. The depositing is performed at a temperature less than about 150 degrees Celsius. The depositing is also performed without using a spin coating process. The method includes forming a patterned photoresist layer over the LT-film.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: August 12, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Liang Lu, Ming-Feng Shieh, Ching-Yu Chang
  • Patent number: 8759161
    Abstract: To provide a surface coating method, which contains applying a surface coating material to a layered structure so as to cover at least a surface of an insulating film of the layered structure, to form a coating on the surface of the insulating film, wherein the surface coating material contains a water-soluble resin, an organic solvent, and water, and wherein the layered structure contains the insulating film exposed to an outer surface, and a patterned metal wiring exposed to an outer surface.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: June 24, 2014
    Assignee: Fujitsu Limited
    Inventor: Junichi Kon
  • Patent number: 8741781
    Abstract: Some embodiments include a semiconductor construction having a pair of lines extending primarily along a first direction, and having a pair of contacts between the lines. The contacts are spaced from one another by a lithographic dimension, and are spaced from the lines by sub-lithographic dimensions. Some embodiments include a method of forming a semiconductor construction. Features are formed over a base. Each feature has a first type sidewall and a second type sidewall. The features are spaced from one another by gaps. Some of the gaps are first type gaps between first type sidewalls, and others of the gaps are second type gaps between second type sidewalls. Masking material is formed to selectively fill the first type gaps relative to the second type gaps. Excess masking material is removed to leave a patterned mask. A pattern is transferred from the patterned mask into the base.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: June 3, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Justin B. Dorhout, Ranjan Khurana, David Swindler, Jianming Zhou
  • Patent number: 8685865
    Abstract: A method of forming patterns of a semiconductor device may include forming a photoresist layer that includes a photo acid generator (PAG) and a photo base generator (PBG), generating an acid from the PAG in a first exposed portion of the photoresist layer by first-exposing the photoresist layer, and generating a base from the PBG in a second exposed portion of the photoresist layer by second-exposing a part of the first exposed portion and neutralizing the acid. The method may also include baking the photoresist layer after the first and second-exposing and deblocking the photoresist layer of the first exposed portion in which the acid is generated to form a deblocked photoresist layer, and forming a photoresist pattern by removing the deblocked photoresist layer by using a developer.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: April 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-ju Park, Kyoung-mi Kim, Min-jung Kim, Dong-jun Lee, Boo-deuk Kim
  • Publication number: 20140080305
    Abstract: A double patterning process is described. A substrate having a first area and a second area is provided. A target layer is formed over the substrate. A patterned first photoresist layer is formed over the target layer, wherein the patterned first photoresist layer has openings and has a first thickness in the first area, and at least a portion of the patterned first photoresist layer in the second area has a second thickness less than the first thickness. A second photoresist layer is then formed covering the patterned first photoresist layer and filling in the openings.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Jenn-Wei Lee, Hung-Jen Liu
  • Publication number: 20140042594
    Abstract: Aspects of the disclosure provide a method of inhibiting crack propagation in a silicon wafer. In one embodiment, a method of repairing an imperfection on a surface of a semiconductor device is disclosed. The method includes: screening for imperfections on a surface of a silicon wafer of a semiconductor device; and in response to at least one imperfection on the surface of the silicon wafer, depositing a material on the surface of the silicon wafer.
    Type: Application
    Filed: August 9, 2012
    Publication date: February 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen P. Ayotte, David J. Hill, Glen E. Richard, Timothy M. Sullivan, Heather M. Truax
  • Patent number: 8617653
    Abstract: It is disclosed an over-coating agent for forming fine patterns which is applied to cover a substrate having photoresist patterns thereon and allowed to shrink under heat so that the spacing between adjacent photoresist patterns is lessened, with the applied film of the over-coating agent being removed to form fine patterns, further characterized by comprising a water-soluble polymer which contains a monomeric component and a dimeric component, wherein the total content of the monomeric component and the dimeric component in the water-soluble polymer is reduced to 10 mass % or less, and a method of forming fine patterns using the same. By the present invention, even in reducing the pattern size on a substrate having thereon patterns having different pitches, the heat shrinkage of the over-coating agent can be controlled, irrespective whether the pitch is dense or isolate, thus achieving the pattern size reduction.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: December 31, 2013
    Assignee: Tokyo Ohka Okgyo Co., Ltd.
    Inventors: Tsunehiro Watanabe, Toshiki Takedutsumi, Masanori Yagishita, Kiyofumi Mitome, Takahito Imai, Masatoshi Hashimoto, Masaji Uetsuka
  • Patent number: 8592821
    Abstract: It is an object of the present invention to provide an organic transistor having a low drive voltage. It is also another object of the present invention to provide an organic transistor, in which light emission can be obtained, which can be manufactured simply and easily. According to an organic light-emitting transistor, a composite layer containing an organic compound having a hole-transporting property and a metal oxide is used as part of the electrode that injects holes among source and drain electrodes, and a composite layer containing an organic compound having an electron-transporting property and an alkaline metal or an alkaline earth metal is used as part of the electrode that injects electrons, where either composite layer has a structure of being in contact with an organic semiconductor layer.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: November 26, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinobu Furukawa, Ryota Imahayashi
  • Patent number: 8592619
    Abstract: The invention relates to compounds comprising a cycloalkyne or heterocycloalkyne group and a redox group. Said compounds are of general formula (I) wherein Z is a cycloalkyne or heterocycloalkyne with at least 8 links, optionally substituted by a halogen atom or a linear or branched C1 to C5 alkyl, A is an organic structure having oxidation-reduction properties, and B is an organic link between the cycloalkyne or heterocycloalkyne cycle and the organic structure A. The invention is especially applicable to the field of molecular electronics.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: November 26, 2013
    Assignee: Commissariat a L'Energie Atomique et aux Enerigies Alternatives
    Inventors: Guillaume Delapierre, Regis Barattin, Aude Bernardin, Isabelle Texier-Nogues
  • Patent number: 8581421
    Abstract: According to one embodiment, there is provided a semiconductor package manufacturing method utilizing a support body in which a first layer is stacked on a second layer, the method including: a first step of forming an opening in the first layer to expose the second layer therethrough; a second step of arranging a semiconductor chip on the second layer through the opening; a third step of forming a resin portion on the first layer to cover the semiconductor chip; and a fourth step of forming a wiring structure on the resin portion so as to be electrically connected to the semiconductor chip.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: November 12, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Noriyoshi Shimizu, Akio Rokugawa, Hirokazu Yoshino
  • Patent number: 8580588
    Abstract: An organic light emitting display includes a substrate, a semiconductor layer arranged on the substrate, an organic light emitting diode arranged on the semiconductor layer, an encapsulant arranged on an top surface periphery of the substrate, which is an outer periphery of the semiconductor layer and the organic light emitting diode, an encapsulation substrate bonded to the encapsulant, and a bonding agent arranged on an under surface of the substrate which is opposite to the encapsulant.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: November 12, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jongyun Kim, Byoungdeog Choi
  • Patent number: 8575039
    Abstract: A surface treating method for treating a surface of a substrate inside a process chamber includes the steps of generating an atmosphere containing no moisture in the process chamber, heating the substrate inside the atmosphere containing no moisture in the process chamber; and causing a reaction between the substrate and an adhesion accelerating agent by feeding the adhesion accelerating agent gas into the process chamber.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: November 5, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Tatsuya Yamaguchi, Hiroyuki Hashimoto
  • Patent number: 8575031
    Abstract: A method is provided for forming a fine pattern. In the method, a first fine pattern and a first metal pattern are formed by respectively patterning a first fine pattern layer on a base substrate and a first metal layer on the first fine pattern layer. A second fine pattern layer and a second metal layer are sequentially formed over the first fine pattern and the first metal pattern. The second metal layer is patterned, so that a second metal pattern between adjacent portions of the first fine pattern. The second fine pattern layer is patterned using the second metal pattern as a mask, so that a second fine pattern is formed between adjacent portions of the first fine pattern.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: November 5, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Se-Hwan Yu, Chong-Sup Chang, Sang-Ho Park, Ji-Seon Lee
  • Publication number: 20130281583
    Abstract: The present invention relates to a method for improving polyimide (PI) non-adherence to a substrate and a PI solution. The method includes the following steps: (1) providing a substrate and a PI solution, the PI solution comprising PI molecules and a solvent, the PI molecules having hydrophobic moieties; and (2) coating the PI solution on the substrate to form a PI film. The PI solution includes PI molecules and a solvent. The PI molecules have hydrophobic moieties. The solvent include N-methyl-2-pyrrolidone, ?-butyrolactone, butyl carbonate, or a mixture thereof. The PI molecules of the PI solution contain hydrophobic moieties and in coating the PI solution to a substrate, the hydrophobic moieties link with organic compounds on the substrate thereby enhancing affinity of the PI solution with surface of the substrate, improving the issue of PI non-adherence, and the heightening quality of printing the substrate.
    Type: Application
    Filed: May 4, 2012
    Publication date: October 24, 2013
    Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO. LTD.
    Inventors: Meina Zhu, Jianjun Zhao, Hsiangyin Shih