Abstract: A substrate processing apparatus according to the present disclosure includes a gripping mechanism and a base plate. The gripping mechanism grips a peripheral edge of a substrate. The base plate is located below the substrate gripped by the gripping mechanism and supports the gripping mechanism. Furthermore, the base plate includes a liquid drain hole that discharges a processing liquid flowing from the substrate to an upper surface of the base plate through the gripping mechanism.

Abstract: An electrically dynamic window structure may include first and second panes of transparent material and an electrically controllable optically active material positioned between the two panes. A driver can be electrically connected to electrode layers carried by the two panes. The driver may be configured to alternate between a drive phase in which a drive signal is applied to the electrode layers and an idle phase in which the drive signal is not applied to the electrode layers. The electrically controllable optically active material can maintain its transition state during the idle phase. As a result, the power consumption of the structure may be reduced as compared to if the driver continuously delivers the drive signal.

Abstract: The present disclosure or invention is directed to novel or improved separators for a variety of lead acid batteries and/or systems. In addition, exemplary embodiments disclosed herein are directed to novel or improved battery separators, separator profiles, separator and electrode assemblies incorporating the same, battery cells incorporating the same, batteries incorporating the same, systems incorporating the same, and/or methods of manufacturing and/or of using the same, and/or the like, and/or combinations thereof. For example, disclosed herein are exemplary embodiments of improved electrode plate and separator assemblies (400) for lead acid batteries, improved lead acid cells or batteries incorporating the improved assemblies, systems or vehicles incorporating the improved assemblies (400) and/or batteries (100), and methods related thereto. The electrode plate (200, 201) may have a grid (202) of a stamped, cast, or expanded metal manufacturing process.

Abstract: The present invention provides a hydrophobic surface coating and a preparation method therefor. The hydrophobic surface coating uses one or more fluorinated alcohol compounds as a reaction gas material, and is formed on a surface of a base body by a plasma-enhanced chemical vapor deposition method, to improve the hydrophobicity, the chemical resistance, and the weatherability of the surface of the base body.

Abstract: A composition includes a polymer and a solvent. The polymer includes: a structural unit including a ring structure; and a functional group capable of bonding to a metal atom. An atom chain constituting the ring structure constitutes a part of a main chain of the polymer. The polymer preferably includes at an end of the main chain or at an end of a side chain, a group including the functional group. The functional group is preferably a cyano group, a phosphono group, or a dihydroxyboryl group. The ring structure preferably includes an alicyclic structure.

Abstract: A method for depositing coating onto a substrate includes providing a monomer for creation of a protective coating on a substrate, energizing the monomer with a plasma generation system, and polymerizing the energized monomer onto the substrate in a plasma-enhanced chemical vapor deposition (PECVD) chamber.

Abstract: Elastic Parylene films produced via chemical vapor deposition polymerization (CVDP) on a substrate are disclosed.

Abstract: According to one or more embodiments, a method for manufacturing a semiconductor device includes alternately stacking a first film and a second film on an object to form a multilayer film, then forming a stacked body and a recess by partially removing the multilayer film. A dielectric layer is then formed by applying a composite material to the recess to fill the recess with the dielectric layer. The composite material includes an inorganic material and an organic material. The dielectric layer is then exposed to an oxidizing gas to oxidize the inorganic material and to remove at least part of the organic material from the dielectric layer.

Abstract: A wafer cleaning apparatus, a method of cleaning wafer and a method of fabricating a semiconductor device are provided. The method of fabricating the semiconductor device includes disposing a wafer on a rotatable chuck, irradiating a lower surface of the wafer with a laser to heat the wafer, and supplying a chemical to an upper surface of the wafer to clean the wafer, wherein the laser penetrates an optical system including an aspheric lens array, the laser penetrates a calibration window, which includes a first window structure including a first light projection window including first and second regions different from each other, a first coating layer covering the first region of the first light projection window, and a second coating layer covering the second region of the first light projection window, and the first coating layer and the second coating layer have different light transmissivities from each other.

Abstract: A graphite sheet having a ratio of thermal diffusivity in horizontal and vertical directions of 300 or more is disclosed. Also, a graphite sheet having a ratio of thermal diffusivity in a vertical direction of 2.0 mm2/s or less is disclosed. The graphite sheet has excellent thermal conductivity in horizontal and vertical directions and excellent flexibility at the same time and can be produced at low manufacturing cost, thereby holding an economic advantage.

Abstract: A method of forming a self-cleaning film system includes depositing a photocatalytic material onto a substrate to form a first layer. The method also includes disposing a photoresist onto the first layer and then exposing the photoresist to light so that the photoresist has a developed portion and an undeveloped portion. The method includes removing the undeveloped portion so that the developed portion protrudes from the first layer. After removing, the method includes depositing a perfluorocarbon siloxane polymer onto the first layer to surround and contact the developed portion. After depositing the perfluorocarbon siloxane polymer, the method includes removing the developed portion to thereby form the self-cleaning film system.

Abstract: There is provided a method of manufacturing a semiconductor device by performing a process on a substrate, comprising: forming a sacrificial film made of a polymer having a urea bond on a surface of the substrate by supplying a precursor for polymerization onto the surface of the substrate; subsequently, performing a step of changing a sectional shape of the sacrificial film and a step of adjusting a film thickness of the sacrificial film by heating the sacrificial film; subsequently, performing the process on the surface of the substrate; and subsequently, removing the sacrificial film.

Abstract: Provided is a control device for controlling an operation of a substrate processing apparatus that forms a predetermined film on a substrate and operations of a plurality of measurement devices that measure a characteristic of the predetermined film. The control device includes: an individual difference information storing unit that stores individual difference information representing a relationship between information allocated to each of the plurality of measurement devices to specify each measurement device and an individual difference of the measurement device; and a controller that corrects a measurement value of the characteristic of the predetermined film measured by the measurement device based on information specifying the measurement device that has measured the characteristic of the predetermined film and the individual difference information stored in the individual difference information storing unit.

Abstract: A process for fabricating an integrated circuit is provided. The process includes providing a substrate, forming a hard mask upon the substrate by one of atomic-layer deposition and molecular-layer deposition, and exposing the hard mask to a charged particle from one or more charged particle beams to pattern a gap in the hard mask. In the alternative, the process includes exposing the hard mask to a charged particle from one or more charged-particle beams to pattern a structure on the hard mask.

Abstract: An array substrate comprises the plurality of gate lines and matrix arranged touch electrodes, which each of the touch electrodes has a plurality of sub electrodes, and each of the sub electrode and the gate line extend along the first direction, the plurality of the sub electrode are arranged in spaced arrangement along the second direction. The first direction and the second direction are perpendicular each other, and the plurality of the sub electrodes electrically connected to each other by the first touch trace, and the shadow of the gate line on the touch electrode is between two of the sub electrodes. The touch electrode is separated into the plurality of sub electrode arranged in spaced arrangement. The shadow of the gate line on the touch electrode is between the two sub electrodes, and the touch electrode avoids the gate line.

Abstract: A method of preparing a photochromic optical article is provided, which includes: (i) applying a first organic solvent to a surface of an optical substrate, thereby forming an organic solvent wetted surface on the optical substrate; and (ii) applying a curable photochromic coating composition over the organic solvent wetted surface of said optical substrate, thereby forming a curable photochromic coating layer over the surface of the optical substrate. The curable photochromic coating composition includes a second organic solvent, and the first and second organic solvents are miscible with each other. With some embodiments, the first and second organic solvents are the same.

Abstract: A novel radiation hardened chip package technology protects microelectronic chips and systems in aviation/space or terrestrial devices against high energy radiation. The proposed technology of a radiation hardened chip package using rare earth elements and mulitlayered structure provides protection against radiation bombardment from alpha and beta particles to neutrons and high energy electromagnetic radiation.

Abstract: A method for processing a substrate exposes a silicon-containing surface at a circumferential edge portion of a first main surface of a substrate to be processed, performs surface processing to the silicon-containing surface to increase a contact angle of the silicon-containing surface with respect to a resist material, comparing with the contact angle before the surface processing is performed, supplies the resist material onto the substrate to be processed after the surface processing, and transfers a template pattern to the resist material.

Abstract: A multi-step system and method for curing a dielectric film in which the system includes a drying system configured to reduce the amount of contaminants, such as moisture, in the dielectric film. The system further includes a curing system coupled to the drying system, and configured to treat the dielectric film with ultraviolet (UV) radiation and infrared (IR) radiation in order to cure the dielectric film.

Abstract: The present disclosure includes systems and techniques relating to methods and systems that improve yield in multiple chips integration processes. In some implementations, a method includes providing, in a chamber, a first integrated circuit chip and a second integrated circuit chip supported on a carrier, flowing a molding compound to cover the first integrated circuit chip, the second integrated circuit chip, and the carrier; and flowing a forming gas into the chamber while curing the molding compound.

Abstract: A resistive memory device includes a bottom electrode and a top electrode sandwiching a switching layer. The device also includes a field enhancement (FE) feature that extends from the bottom electrode either into the switching layer or is covered by switching layer and that is to enhance an electric field generated by the two electrodes to thereby confine a switching area of the device at the FE feature. The device further includes a planar interlayer dielectric surrounding the device, for supporting the top electrode. A method of making a resistive memory device, employing in-situ vacuum deposition of all layers, is also provided.

Abstract: The inventive concepts provide a method for inspecting a pattern, a method for manufacturing a semiconductor device, and an apparatus used according to the methods. The method for inspecting a pattern includes detecting a measured image corresponding to a pattern formed on a substrate, detecting a first hot spot corresponding to a ghost image of the measured image, with the first hot spot representing a defect of the pattern, and detecting a second hot spot that has an area that is wider than that of the first hot spot.

Abstract: An implantable device includes an exterior gold surface and a thin film disposed on the exterior gold surface and forming a barrier between the exterior gold surface and an implanted environment, in which the thin film includes molecules with a head portion, the head portion attached to the exterior gold surface.

Abstract: A concentrator photovoltaic module 1M includes a vessel-shaped housing 11 composed of a metal and a flexible printed wiring board 12 provided so as to be in contact with an inner surface of the housing 11. The flexible printed wiring board 12 includes an insulating layer 124, an insulating substrate 121a, a pattern 121b, a plurality of power generation elements 122, and an insulting layer 126. The insulating layer 124 is in contact with a bottom surface 11a of the housing 11. The insulating substrate 121a is provided on the insulating layer 124 and has flexibility. The pattern 121b is composed of a conductor and is provided on the insulating substrate 121a. The plurality of power generation elements 122 are mounted on the pattern 121b. The insulating layer 126 is provided so as to cover an entire surface of the pattern 121b except for portions where the power generation elements 122 are mounted.

Abstract: A method for improving a chemical resistance of a polymerized film, which is formed on a surface of a target object and to be processed by a chemical, includes: consecutively performing a treatment for improving the chemical resistance of the polymerized film subsequent to formation of the polymerized film within a processing chamber of a film forming apparatus where the polymerized film is formed, without unloading the target object from the processing chamber.

Abstract: A method of manufacturing a semiconductor device includes forming a cavity in a first semiconductor layer formed on a semiconducting base layer, the cavity extending from a process surface of the first semiconductor layer at least down to the base layer, forming a recessed mask liner on a portion of a sidewall of the cavity distant to the process surface or a mask plug in a portion of the cavity distant to the process surface, and growing a second semiconductor layer on the process surface by epitaxy, the second semiconductor layer spanning the cavity.

Abstract: Disclosed is a composite substrate manufacturing method whereby, after bonding a semiconductor substrate (1) and a supporting substrate (3) to each other, the semiconductor substrate (1) is thinned, and a composite substrate (8) having a semiconductor layer (6) on the supporting substrate (3) is obtained. On the supporting substrate (3) surface to be bonded, a coating film (4a) containing polysilazane is formed, a silicon-containing insulating film (4) is formed by performing firing by heating the coating film (4a) to 600-1,200° C., then, the semiconductor substrate (1) and the supporting substrate (3) are bonded to each other with the insulating film (4) therebetween, thereby suppressing bonding failures due to surface roughness and defects of the supporting substrate, and easily obtaining the composite substrate.

Abstract: A method for fabricating a semiconductor structure includes: providing a substrate with a dielectric layer and a passivation layer formed on the substrate; forming a via through the dielectric layer and exposing the substrate; forming a first conductive layer to fill the via with a top surface of the first conductive layer leveled with a top surface of the passivation layer; forming a patterned layer with an opening on the passivation layer. The opening is located above the first conductive layer with a dimension larger than the dimension of the via. The method also includes forming a trench in the dielectric layer; forming a second conductive layer to fill the trench and to electrically connect to the first conductive layer; then removing a portion of the second conductive layer, the patterned layer, and the passivation layer to make a top surface of the second conductive layer level with a top surface of the dielectric layer.

Abstract: A photosensitive resin composition includes an alkali-soluble resin (A), a compound having an unsaturated vinyl group (B), a photo initiator (C), solvent (D) and a silane compound (E) having a structure shown as formula (I): in the formula (I), A individually and independently represents a single bond, an alkylene group, or an arylene group, B individually and independently represents an organic group having diphenyl phosphine, hydrogen atom, an alkyl group, an aryl group, or —OR, in which R is a C1-C6 alkyl group or a phenyl group, at least one B is the organic group having diphenyl phosphine and at least one B is —OR. When B is —OR, A connected to B is the single bond. A film formed by the photosensitive resin composition has good refractivity and adhesivity to molybdenum.

Abstract: To provide a semiconductor device having improved reliability. After formation of a first insulating film for an interlayer insulating film by spin coating, the surface of the first insulating film is subjected to a hydrophilicity improving treatment. A second insulating film for the interlayer insulating film is then formed on the first insulating film by spin coating. The interlayer insulating film is comprised of a stacked insulating film including the first insulating film and the second insulating film thereon. The interlayer insulating film therefore can have improved surface flatness.

Abstract: In one aspect, a method of forming a wiring layer on a wafer is provided which includes: depositing a HSQ layer onto the wafer; cross-linking a first portion(s) of the HSQ layer using e-beam lithography; depositing a hardmask material onto the HSQ layer; patterning the hardmask using optical lithography, wherein the patterned hardmask covers a second portion(s) of the HSQ layer; patterning the HSQ layer using the patterned hardmask in a manner such that i) the first portion(s) of the HSQ layer remain and ii) the second portion(s) of the HSQ layer covered by the patterned hardmask remain, wherein by way of the patterning step trenches are formed in the HSQ layer; and filling the trenches with a conductive material to form the wiring layer on the wafer.

Abstract: Methods are described for forming flowable carbon layers on a semiconductor substrate. A local excitation (such as a hot filament in hot wire CVD, a plasma in PECVD or UV light) may be applied as described herein to a silicon-free carbon-containing precursor containing a hydrocarbon to form a flowable carbon-containing film on a substrate. A remote excitation method has also been found to produce flowable carbon-containing films by exciting a stable precursor to produce a radical precursor which is then combined with unexcited silicon-free carbon-containing precursors in the substrate processing region.

Abstract: An element substrate is provided, including a substrate, a metal layer and a planarization layer. The metal layer is located on the substrate. The metal layer has a first edge in a first direction. The planarization layer is located on the metal layer. The planarization layer includes a contact hole. The contact hole has a contiguous wall and a bottom side. The metal layer is exposed in the bottom side. A contour line of the contiguous wall on a vertical plane is a curved line. The first edge corresponds vertically with a critical point on the contour line. The slope of a tangent line on the critical point of the contour line is smaller than 0.176.

Abstract: Provided herein are methods for depositing a spin-on-glass composition over an imprinted resist; curing the spin-on-glass composition to form a cured spin-on-glass composition; and forming a patterned mask by etching the cured spin-on-glass composition, the resist, and an underlying mask composition, wherein the patterned mask comprises features of the cured spin-on-glass composition atop the mask composition, and wherein curing the spin-on-glass composition is configured to prevent shifting or toppling of the spin-on glass composition from atop the mask composition while forming the patterned mask.

Abstract: A first photosensitive organic insulating film (PO1) formed in contact with a passivation film (PL) covers the entire circumference of a stepped portion (TRE) at a surface of the passivation film PL formed by a topmost conductive layer (TCL) and has an outer circumferential edge (ED1) positioned, along the entire circumference, on the outer circumferential side with respect to the stepped portion (TRE). This can prevent the first photosensitive organic insulating film (PO1) from peeling off the passivation film (PL).

Abstract: The invention relates to a new method of texturing silicon surfaces suited for antireflection based on ion implantation of hydrogen and heavy ions or heavy elements combined with thermal annealing or thermal annealing and oxidation. The addition of the heavy ions or heavy elements allows for a more effective anti-reflective surface than is found when only hydrogen implantation is utilized. The methods used are also time- and cost-effective, as they can utilize already existing semiconductor ion implantation fabrication equipment and reduce the number of necessary steps. The antireflective surfaces are useful for silicon-based solar cells.

Abstract: A land grid array (LGA) package including a substrate having a plurality of lands formed on a first surface of the substrate, a semiconductor chip mounted on a second surface of the substrate, a connection portion connecting the semiconductor chip and the substrate, and a support layer formed on part of a surface of a first land.

Abstract: Methods of fabricating nano-scale structures are provided. A method includes forming a first hard mask pattern corresponding to first openings in a dense region, forming first guide elements on the first hard mask pattern aligned with the first openings, and forming second hard mask patterns in a sparse region to provide isolated patterns. A blocking layer is formed in the sparse region to cover the second hard mask patterns. A first domain and second domains are formed in the dense region using a phase separation of a block co-polymer layer. Related nano-scale structures are also provided.

Abstract: A method for far back end of the line (FBEOL) protection of a semiconductor device includes forming a patterned layer over a back end of the line (BEOL) stack, depositing a first conformal protection layer on the patterned layer which covers horizontal surfaces of a top surface and sidewalls of openings formed in the patterned layer. A resist layer is patterned over the first conformal protection layer such that openings in the resist layer correspond with the openings in the patterned layer. The first conformal protection layer is etched through the openings in the resist layer to form extended openings that reach a stop position. The resist layer is removed, and a second conformal protection layer is formed on the first conformal protection layer and on sidewalls of the extended openings to form an encapsulation boundary to protect at least the patterned layer and a portion of the BEOL stack.

Abstract: The disclosure relates to integrated circuit fabrication and, more particularly, to a semiconductor device with a high-k gate dielectric layer. An exemplary structure for a semiconductor device comprises a substrate and a gate structure disposed over the substrate. The gate structure comprises a dielectric portion and an electrode portion that is disposed over the dielectric portion, and the dielectric portion comprises a carbon-doped high-k dielectric layer on the substrate and a carbon-free high-k dielectric layer adjacent to the electrode portion.

Abstract: The invention provides a composition for forming a silicon-containing resist underlayer film comprising: (A) a silicon-containing compound obtained by a hydrolysis-condensation reaction of a mixture containing, at least, one or more hydrolysable silicon compound shown by the following general formula (1) and one or more hydrolysable compound shown by the following general formula (2), and (B) a silicon-containing compound obtained by a hydrolysis-condensation reaction of a mixture containing, at least, one or more hydrolysable silicon compound shown by the following general formula (3) and one or more hydrolysable silicon compound shown by the following general formula (4).

Abstract: A method for far back end of the line (FBEOL) protection of a semiconductor device includes forming a patterned layer over a back end of the line (BEOL) stack, depositing a first conformal protection layer on the patterned layer which covers horizontal surfaces of a top surface and sidewalls of openings formed in the patterned layer. A resist layer is patterned over the first conformal protection layer such that openings in the resist layer correspond with the openings in the patterned layer. The first conformal protection layer is etched through the openings in the resist layer to form extended openings that reach a stop position. The resist layer is removed, and a second conformal protection layer is formed on the first conformal protection layer and on sidewalls of the extended openings to form an encapsulation boundary to protect at least the patterned layer and a portion of the BEOL stack.

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract: The present disclosure is directed to a process for the fabrication of a semiconductor device. In some embodiments the semiconductor device comprises a patterned surface. The pattern can be formed from a self-assembled monolayer. The disclosed process provides self-assembled monolayers which can be deposited quickly, thereby increasing production throughput and decreasing cost, as well as providing a pattern having substantially uniform shape.

Abstract: In one embodiment, first and second pattern structures respectively include first and second conductive line patterns and first and second hard masks sequentially stacked, and at least portions thereof extends in a first direction. The insulation layer patterns contact end portions of the first and second pattern structures. The first pattern structure and a first insulation layer pattern of the insulation layer patterns form a first closed curve shape in plan view, and the second pattern structure and a second insulation layer pattern of the insulation layer patterns form a second closed curve shape in plan view. The insulating interlayer covers upper portions of the first and second pattern structures and the insulation layer patterns, a first air gap between the first and second pattern structures, and a second air gap between the insulation layer patterns.

Abstract: Disclosed is a low dielectric constant insulating film formed of a polymer containing Si atoms, O atoms, C atoms, and H atoms, which includes straight chain molecules in which a plurality of basic molecules with an SiO structure are linked in a straight chain, binder molecules with an SiO structure linking a plurality of the straight chain molecules. The area ratio of a signal indicating a linear type SiO structure is 49% or more, and the signal amount of the signal indicating Si(CH3) is 66% or more.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of circuit devices over a substrate. The method includes forming an organic layer over the substrate. The organic layer is formed over the plurality of circuit devices. The method includes polishing the organic layer to planarize a surface of the organic layer. The organic layer is free of being thermally treated prior to the polishing. The organic material is un-cross-linked during the polishing. The method includes depositing a LT-film over the planarized surface of the organic layer. The depositing is performed at a temperature less than about 150 degrees Celsius. The depositing is also performed without using a spin coating process. The method includes forming a patterned photoresist layer over the LT-film.

Abstract: To provide a surface coating method, which contains applying a surface coating material to a layered structure so as to cover at least a surface of an insulating film of the layered structure, to form a coating on the surface of the insulating film, wherein the surface coating material contains a water-soluble resin, an organic solvent, and water, and wherein the layered structure contains the insulating film exposed to an outer surface, and a patterned metal wiring exposed to an outer surface.

Abstract: Some embodiments include a semiconductor construction having a pair of lines extending primarily along a first direction, and having a pair of contacts between the lines. The contacts are spaced from one another by a lithographic dimension, and are spaced from the lines by sub-lithographic dimensions. Some embodiments include a method of forming a semiconductor construction. Features are formed over a base. Each feature has a first type sidewall and a second type sidewall. The features are spaced from one another by gaps. Some of the gaps are first type gaps between first type sidewalls, and others of the gaps are second type gaps between second type sidewalls. Masking material is formed to selectively fill the first type gaps relative to the second type gaps. Excess masking material is removed to leave a patterned mask. A pattern is transferred from the patterned mask into the base.

Abstract: A method of forming patterns of a semiconductor device may include forming a photoresist layer that includes a photo acid generator (PAG) and a photo base generator (PBG), generating an acid from the PAG in a first exposed portion of the photoresist layer by first-exposing the photoresist layer, and generating a base from the PBG in a second exposed portion of the photoresist layer by second-exposing a part of the first exposed portion and neutralizing the acid. The method may also include baking the photoresist layer after the first and second-exposing and deblocking the photoresist layer of the first exposed portion in which the acid is generated to form a deblocked photoresist layer, and forming a photoresist pattern by removing the deblocked photoresist layer by using a developer.