Composed Of Alternated Layers Or Of Mixtures Of Nitrides And Oxides Or Of Oxynitrides, E.g., Formation Of Oxynitride By Oxidation Of Nitride Layer (epo) Patents (Class 257/E21.267)
-
Patent number: 8390135Abstract: The reliability of a porous Low-k film is improved. The mean diameter of first pores and second pores in an interlayer insulation film of a second fine layer including a porous Low-k film is set at 1.0 nm or more and less than 1.45 nm. This prevents the formation of a modified layer over the surface of the interlayer insulation film by process damages. Further, the formation of the moisture-containing modified layer is inhibited to prevent oxidation of a barrier film and a main conductor film forming respective wirings. This prevents deterioration of breakdown voltage between respective wirings. This prevents deterioration of the EM lifetime of wirings formed adjacent to the interlayer insulation film and the inter-wiring TDDB lifetime of the wirings.Type: GrantFiled: May 18, 2011Date of Patent: March 5, 2013Assignee: Renesas Electronics CorporationInventors: Yoshihiro Oka, Kinya Goto
-
Patent number: 8384135Abstract: A phase-change random access memory device includes a semiconductor substrate, a bottom electrode structure formed on the semiconductor substrate, a cylindrical bottom electrode contact that includes a conductive material layer, which is in contact with the bottom electrode, and a cylindrical phase-change material layer that is in contact with the bottom electrode contact. Therefore, the contact area between the bottom electrode contact and the phase-change material layer can be minimized.Type: GrantFiled: June 20, 2011Date of Patent: February 26, 2013Assignee: SK hynix Inc.Inventors: Cheol Hwi Ryu, Hyung Soon Park, Jong Han Shin, Jum Yong Park, Sung Jun Kim
-
Patent number: 8383522Abstract: There is provided a micro pattern forming method including forming a thin film on a substrate; forming a film serving as a mask when processing the thin film; processing the film serving as a mask into a pattern including lines having a preset pitch; trimming the pattern including the lines; and forming an oxide film on the pattern including the lines and on the thin film by alternately supplying a source gas and an activated oxygen species. Here, the process of trimming the pattern and the process of forming an oxide film are consecutively performed in a film forming apparatus configured to form the oxide film.Type: GrantFiled: June 7, 2011Date of Patent: February 26, 2013Assignee: Tokyo Electron LimitedInventors: Shigeru Nakajima, Kazuhide Hasebe, Pao-Hwa Chou, Mitsuaki Iwashita, Reiji Niino
-
Patent number: 8357562Abstract: A structure to diminish high voltage instability in a high voltage device when under stress includes an amorphous silicon layer over a field oxide on the high voltage device.Type: GrantFiled: January 28, 2011Date of Patent: January 22, 2013Assignee: Fairchild Semiconductor CorporationInventor: Jifa Hao
-
Patent number: 8357608Abstract: An in-situ process is described incorporating plasma enhanced chemical vapor deposition comprising flowing at least one of a Si, Si+C, B, Si+B, Si+B+C, and B+C containing precursor, and a N containing precursors at first times and removing the N precursor at second times and starting the flow of an oxidant gas and a porogen gas into the chamber. A dielectric layer is described comprising a network having inorganic random three dimensional covalent bonding throughout the network which contains at least one SiCN, SiCNH, SiN, SiNH, BN, BNH, CBN, CBNH, BSiN, BSiNH, SiCBN and SiCBNH as a first component and a low k dielectric as a second component adjacent thereto.Type: GrantFiled: August 9, 2010Date of Patent: January 22, 2013Assignee: International Business Machines CorporationInventors: Stephen M Gates, Alfred Grill, Son Van Nguyen, Satyanarayana Venkata Nitta
-
Publication number: 20130017690Abstract: In a plasma nitriding method, a processing gas containing nitrogen gas and rare gas is introduced into a processing chamber of a plasma processing apparatus by setting a flow rate thereof as a total flow rate [mL/min(sccm)] of the processing gas per 1 L volume of the processing chamber within a range from 1.5 (mL/min)/L to 13 (mL/min)/L. Further, a nitriding process is performed on oxygen-containing films of target objects to be processed by generating a nitrogen-containing plasma in the processing chamber and while exchanging the target objects.Type: ApplicationFiled: March 30, 2011Publication date: January 17, 2013Applicant: TOKYO ELECTRON LIMITEDInventors: Koichi Takatsuki, Kazuyoshi Yamazaki, Hideyuki Noguchi, Daisuke Tamura, Tomohiro Saito
-
Publication number: 20130015494Abstract: A termination structure for a semiconductor device includes an array of termination cells formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In other embodiments, semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches.Type: ApplicationFiled: September 21, 2012Publication date: January 17, 2013Applicant: ALPHA & OMEGA SEMICONDUCTOR, INC.Inventor: ALPHA & OMEGA SEMICONDUCTOR, INC.
-
Patent number: 8354702Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.Type: GrantFiled: February 19, 2010Date of Patent: January 15, 2013Assignee: Elpida Memory, Inc.Inventors: Sunil Shanker, Xiangxin Rui, Pragati Kumar, Hanhong Chen, Toshiyuki Hirota
-
Patent number: 8354349Abstract: A semiconductor device includes a plurality of wiring lines which are provided on an upper side of a semiconductor substrate and which have connection pad portions, and columnar electrodes are provided on the connection pad portions of the wiring lines. A first sealing film is provided around the columnar electrodes on the upper side of the semiconductor substrate and on the wiring lines. A second sealing film is provided on the first sealing film. The first sealing film is made of a resin in which fillers are not mixed, and the second sealing film is made of a material in which fillers are mixed in a resin.Type: GrantFiled: March 19, 2010Date of Patent: January 15, 2013Assignee: Casio Computer Co., Ltd.Inventor: Junji Shiota
-
Publication number: 20130005155Abstract: Methods of improving charge trapping are disclosed. One such method includes forming an oxide-nitride-oxide tunnel stack and a silicon nitride layer on the oxide-nitride-oxide tunnel stack. This silicon nitride layer is implanted with ions. These ions may function as electron traps or as fields. The silicon nitride layer may be part of a flash memory device.Type: ApplicationFiled: September 11, 2012Publication date: January 3, 2013Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATE, INC.Inventors: Deepak RAMAPPA, Kyu-Ha SHIM
-
Patent number: 8343842Abstract: A semiconductor process and apparatus to provide a way to reduce plasma-induced damage by applying a patterned layer of photoresist which includes resist openings formed over the active circuit areas as well as additional resist openings formed over inactive areas in order to maintain the threshold coverage level to control the amount of resist coverage over a semiconductor structure so that the total amount of resist coverage is at or below a threshold coverage level. Where additional resist openings are required in order to maintain the threshold coverage level, these openings may be used to create additional charge dissipation structures for use in manufacturing the final structure.Type: GrantFiled: March 31, 2011Date of Patent: January 1, 2013Assignee: Freescale Semiconductor, Inc.Inventors: David M. Schraub, Terry A. Breeden, James D. Legg, Mehul D. Shroff, Ruiqi Tian
-
Publication number: 20120306058Abstract: A method of forming a surface passivation layer on a surface of a crystalline silicon substrate is disclosed. In one aspect, the method includes depositing an Al2O3 layer on the surface, the Al2O3 layer having a thickness not exceeding about 15 nm; performing an outgassing process at a temperature in the range between about 500° C. and 900° C., after the deposition of the Al2O3 layer on the surface; and after the outgassing process, depositing at least one additional dielectric layer such as a silicon nitride layer and/or a silicon oxide layer on the Al2O3 layer.Type: ApplicationFiled: June 5, 2012Publication date: December 6, 2012Applicants: Katholieke Universiteit Leuven, IMECInventor: Bart Vermang
-
Patent number: 8319261Abstract: A semiconductor component having a semiconductor body having a first and a second side, an edge and an edge region adjacent to the edge in a lateral direction is described.Type: GrantFiled: January 5, 2011Date of Patent: November 27, 2012Assignee: Infineon Technologies Austria AGInventors: Anton Mauder, Stefan Sedlmaier, Ralf Erichsen, Hans Weber, Oliver Haeberlen, Franz Hirler
-
Patent number: 8304327Abstract: At present, a forming process of a base film through an amorphous silicon film is conducted in respective film forming chambers in order to obtain satisfactory films. When continuous formation of the base film through the amorphous silicon film is performed in a single film forming chamber with the above film formation condition, crystallization is not sufficiently attained in a crystallization process. By forming the amorphous silicon film using silane gas diluted with hydrogen, crystallization is sufficiently attained in the crystallization process even with the continuous formation of the base film through the amorphous silicon film in the single film forming chamber.Type: GrantFiled: February 25, 2010Date of Patent: November 6, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi
-
Patent number: 8294182Abstract: A light emitting device according to the embodiment includes a first electrode; a light emitting structure including a first semiconductor layer over the first electrode, an active layer over the first semiconductor layer, and a second semiconductor layer over the second semiconductor layer; a second electrode over the second semiconductor layer; and a connection member having one end making contact with the first semiconductor layer and the other end making contact with the second semiconductor layer to form a schottky contact with respect to one of the first and second semiconductor layers.Type: GrantFiled: November 12, 2010Date of Patent: October 23, 2012Assignee: LG Innotek Co., Ltd.Inventor: Hwan Hee Jeong
-
Publication number: 20120261767Abstract: Systems and methods for reducing gate leakage current and positive bias temperature instability drift are provided. In one embodiment, a system comprises a p-channel field effect transistor (PFET) device on a semiconductor substrate, and a high voltage transistor on the substrate. The system also comprises a plurality of silicides formed in the substrate, the plurality of silicides formed proximate to the PFET device and the high voltage transistor. Further, the system comprises a buffer oxide layer formed over the substrate, the PFET device, and the high voltage transistor and a moisture barrier formed over the buffer layer, the moisture barrier comprised of silicon oxynitride. Additionally, the system comprises an interlayer dielectric device formed over the moisture barrier and a plurality of electrical contacts extending through the interlayer dielectric, the moisture barrier, and the buffer oxide layer, wherein the plurality of electrical contacts are electrically connected to the plurality of silicides.Type: ApplicationFiled: March 19, 2012Publication date: October 18, 2012Applicant: INTERSIL AMERICAS INC.Inventor: Michael D. Church
-
Patent number: 8288234Abstract: To provide a method of manufacturing a dielectric film having a high dielectric constant. In an embodiment of the present invention, an HfN/Hf laminated film is formed on a substrate on which a thin silicon oxide film is formed and a dielectric film of a metal nitride made of a mixture of Hf, Si, O and N is manufactured by annealing treatment. According to the present invention, it is possible to (1) reduce an EOT, (2) reduce a leak current to Jg=1.0×10?1 A/cm2 or less, (3) suppress hysteresis caused by the generation of fixed charges, and (4) prevent an increase in EOT even if heat treatment at 700° C. or more is performed and obtain excellent heat resistance.Type: GrantFiled: July 21, 2010Date of Patent: October 16, 2012Assignee: Canon Anelva CorporationInventors: Takuya Seino, Takashi Nakagawa, Naomu Kitano, Toru Tatsumi
-
Patent number: 8288184Abstract: A production method for producing a semiconductor device capable of improving surface flatness and suppressing a variation in electrical characteristics of the semiconductor chip, and improving production yield. The production method includes the steps of: forming a first insulating film on a semiconductor substrate and on a conductive pattern film formed on the semiconductor substrate and reducing a thickness of the first insulating film in a region where the conductive pattern film is arranged by patterning; forming a second insulating film and polishing the second insulating film, thereby forming a flattening film; implanting a substance for cleavage into the semiconductor substrate through the flattening film, thereby forming a cleavage layer; transferring the semiconductor chip onto a substrate with an insulating surface so that the chip surface on the side opposite to the semiconductor substrate is attached thereto; and separating the semiconductor substrate from the cleavage layer.Type: GrantFiled: October 14, 2008Date of Patent: October 16, 2012Assignee: Sharp Kabushiki KaishaInventors: Michiko Takei, Yutaka Takafuji, Yasumori Fukushima, Kazuhide Tomiyasu, Steven Roy Droes
-
Patent number: 8288217Abstract: A field effect transistor device includes a gate stack portion disposed on a substrate, and a channel region in the substrate having a depth partially defined by the gate stack portion and a silicon region of the substrate, the silicon region having a sloped profile such that a distal regions of the channel region have greater depth than a medial region of the channel region.Type: GrantFiled: November 12, 2010Date of Patent: October 16, 2012Assignee: International Business Machines CorporationInventors: Dechao Guo, Pranita Kulkarni, Philip J. Oldiges, Alexander Reznicek, Keith Kwong Hon Wong
-
Patent number: 8283263Abstract: An integrated circuit method for manufacturing an integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas.Type: GrantFiled: July 5, 2006Date of Patent: October 9, 2012Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Sripad Sheshagiri Nagarad, Hwa Weng Koh, Dong Kyun Sohn, Xiaoyu Chen, Louis Lim, Sung Mun Jung, Chiew Wah Yap, Pradeep Ramachandramurthy Yelehanka, Nitin Kamat
-
Patent number: 8273617Abstract: A suite of novel structures and methods is provided to reduce power consumption in a wide array of electronic devices and systems. Some of these structures and methods can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. As will be discussed, some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors.Type: GrantFiled: February 18, 2010Date of Patent: September 25, 2012Assignee: SuVolta, Inc.Inventors: Scott E. Thompson, Damodar R. Thummalapally
-
Patent number: 8269318Abstract: A method for forming an offset spacer of a MOS device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; forming a dielectric stack on the substrate and the gate structure, wherein the dielectric stack includes a first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer; and performing an etching process on the dielectric stack to form an offset spacer around the gate structure.Type: GrantFiled: May 3, 2010Date of Patent: September 18, 2012Assignee: United Microelectronics Corp.Inventor: Chun Rong
-
Patent number: 8263421Abstract: An object is to provide a manufacturing method of a microcrystalline semiconductor film with favorable quality over a large-area substrate. After forming a gate insulating film over a gate electrode, in order to improve quality of a microcrystalline semiconductor film formed in an initial stage, glow discharge plasma is generated by supplying high-frequency powers with different frequencies, and a lower part of the film near an interface with the gate insulating film is formed under a first film formation condition, which is low in film formation rate but results in a good quality film. Thereafter, an upper part of the film is deposited under a second film formation condition with higher film formation rate, and further, a buffer layer is stacked on the microcrystalline semiconductor film.Type: GrantFiled: November 12, 2010Date of Patent: September 11, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Sachiaki Teduka, Satoshi Toriumi, Makoto Furuno, Yasuhiro Jinbo, Koji Dairiki, Hideaki Kuwabara
-
Patent number: 8263458Abstract: Embodiments of the present technology are directed toward charge trapping region process margin engineering for charge trapping field effect transistor. The techniques include forming a plurality of shallow trench isolation regions on a substrate, wherein the tops of the shallow trench isolation regions extend above the substrate by a given amount. A portion of the substrate is oxidized to form a tunneling dielectric region. A first set of one or more nitride layers are deposited on the tunneling dielectric region and shallow trench isolation regions, wherein a thickness of the first set of nitride layers is approximately half of the given amount that the tops of the shallow trench isolation regions extend above the substrate. A portion of the first set of nitride layers is etched back to the tops of the trench isolation regions. A second set of one or more nitride layers is deposited on the etched back first set of nitride layers.Type: GrantFiled: December 20, 2010Date of Patent: September 11, 2012Assignee: Spansion LLCInventors: Tung-Sheng Chen, Shenqing Fang
-
Patent number: 8247329Abstract: A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.Type: GrantFiled: February 9, 2011Date of Patent: August 21, 2012Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
-
Patent number: 8241993Abstract: Methods for rounding the bottom corners of a shallow trench isolation structure are described herein. Embodiments of the present invention provide a method comprising forming a first masking layer on a sidewall of an opening in a substrate, removing, to a first depth, a first portion of the substrate at a bottom surface of the opening having the first masking layer therein, forming a second masking layer on the first masking layer in the opening, and removing, to a second depth, a second portion of the substrate at the bottom surface of the opening having the first and second masking layers therein. Other embodiments also are described.Type: GrantFiled: July 10, 2008Date of Patent: August 14, 2012Assignee: Marvell World Trade Ltd.Inventors: Albert Wu, Runzi Chang
-
Patent number: 8237264Abstract: A method of manufacturing a semiconductor device has forming a ferroelectric film over a substrate, placing the substrate having the ferroelectric film in a chamber substantially held in vacuum, introducing oxygen and an inert gas into the chamber, annealing the ferroelectric film in the chamber, and containing oxygen and the inert gas while the chamber is maintained sealed.Type: GrantFiled: January 20, 2011Date of Patent: August 7, 2012Assignee: Fujitsu Semiconductor LimitedInventor: Kouichi Nagai
-
Publication number: 20120196450Abstract: Stress of a silicon nitride layer may be enhanced by deposition at higher temperatures. Employing an apparatus that allows heating of a substrate to substantially greater than 400° C. (for example a heater made from ceramic rather than aluminum), the silicon nitride film as-deposited may exhibit enhanced stress allowing for improved performance of the underlying MOS transistor device. In accordance with some embodiments, a deposited silicon nitride film is exposed to curing with plasma and ultraviolet (UV) radiation, thereby helping remove hydrogen from the film and increasing film stress. In accordance with other embodiments, a silicon nitride film is formed utilizing an integrated process employing a number of deposition/curing cycles to preserve integrity of the film at the sharp corner of the underlying raised feature. Adhesion between successive layers may be promoted by inclusion of a post-UV cure plasma treatment in each cycle.Type: ApplicationFiled: February 2, 2012Publication date: August 2, 2012Applicant: Applied Materials, Inc.Inventors: Mihaela Balseanu, Victor Nguyen, Li-Qun Xia, Derek R. Witty, Hichem M'Saad, Mei-Yee Shek, Isabelita Roflox
-
Patent number: 8227356Abstract: The present invention provides a semiconductor device having an improved silicon oxide film as a gate insulation film of a Metal Insulator Semiconductor structure and a method of making the same.Type: GrantFiled: August 26, 2011Date of Patent: July 24, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Kouichi Muraoka
-
Publication number: 20120184110Abstract: An insulating film including characteristics such as low permittivity, a low etching rate and a high insulation property is formed. Supplying a gas containing an element, a carbon-containing gas and a nitrogen-containing gas to a heated substrate in a processing vessel to form a carbonitride layer including the element, and supplying the gas containing the element and an oxygen-containing gas to the heated substrate in the processing vessel to form an oxide layer including the element are alternately repeated to form on the substrate an oxycarbonitride film having the carbonitride layer and the oxide layer alternately stacked therein.Type: ApplicationFiled: January 9, 2012Publication date: July 19, 2012Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Yoshiro Hirose, Yushin Takasawa, Tsukasa Kamakura, Yoshinobu Nakamura, Ryota Sasajima
-
Patent number: 8222705Abstract: Disclosed herein is a solid-state image pickup device including: a trench formed in an insulating film above a light-receiving portion; a first waveguide core portion provided on an inner wall side of the trench; a second waveguide core portion filled in the trench via the first waveguide core portion; and a rectangular lens formed of the same material as that of the second waveguide core portion and provided integrally with the second waveguide core portion.Type: GrantFiled: May 7, 2010Date of Patent: July 17, 2012Assignee: Sony CorporationInventors: Akiko Ogino, Yukihiro Sayama, Takayuki Shoya, Masaya Shimoji
-
Publication number: 20120178267Abstract: Silicon precursors for forming silicon-containing films in the manufacture of semiconductor devices, such as low dielectric constant (k) thin films, high k gate silicates, low temperature silicon epitaxial films, and films containing silicon nitride (Si3N4), siliconoxynitride (SiOxNy) and/or silicon dioxide (SiO2). The precursors of the invention are amenable to use in low temperature (e.g., <500° C.) chemical vapor deposition processes, for fabrication of ULSI devices and device structures.Type: ApplicationFiled: March 19, 2012Publication date: July 12, 2012Applicant: ADVANCED TECHNOLOGY MATERIALS, INC.Inventors: Ziyun Wang, Chongying Xu, Ravi K. Laxman, Thomas H. Baum, Bryan Hendrix, Jeffrey Roeder
-
Patent number: 8217513Abstract: Embodiments related to the cleaning of interface surfaces in a semiconductor wafer fabrication process via remote plasma processing are disclosed herein. For example, in one disclosed embodiment, a semiconductor processing apparatus includes a processing chamber, a load lock coupled to the processing chamber via a transfer port, a wafer pedestal disposed in the load lock and configured to support a wafer in the load lock, a remote plasma source configured to provide a remote plasma to the load lock, and an ion filter disposed between the remote plasma source and the wafer pedestal.Type: GrantFiled: February 2, 2011Date of Patent: July 10, 2012Assignee: Novellus Systems, Inc.Inventors: George Andrew Antonelli, Jennifer O'Loughlin, Tony Xavier, Mandyam Sriram, Bart van Schravendijk, Vishwanathan Rangarajan, Seshasayee Varadarajan, Bryan L. Buckalew
-
Patent number: 8212345Abstract: A backgrinding machine 10 of a semiconductor wafer W includes: a table 13 set on the working plane of a mount 11; a multiple number of holding jigs 20 arranged via check tables 15 on table 13; a grinding machine 30 for performing a grinding process of the rear side of semiconductor wafer W held by holding jig 20; and a washing device 40 for ground semiconductor wafers W. Each holding jig 20 is constructed of a concave 22 depressed on the surface of a base plate 21, a multiple number of supporting projections 23 projectively arrayed on the bottom surface of concave 22, a deformable contact film 24, covering the concave 22, being supported by the multiple supporting projections 23, for detachably holding semiconductor wafer W in close contact with it; and an exhaust path 25 for conducting air from the concave 22 covered by contact film 24 to the outside.Type: GrantFiled: November 12, 2010Date of Patent: July 3, 2012Assignees: Shin-Etsu Polymer Co., Ltd., Lintec CorporationInventors: Kiyofumi Tanaka, Satoshi Odashima, Noriyoshi Hosono, Hironobu Fujimoto, Takeshi Segawa
-
Publication number: 20120156894Abstract: This invention relates to silicon precursor compositions for forming silicon-containing films by low temperature (e.g., <550° C.) chemical vapor deposition processes for fabrication of ULSI devices and device structures. Such silicon precursor compositions comprise at least a silane or disilane derivative that is substituted with at least one alkylhydrazine functional groups and is free of halogen substitutes.Type: ApplicationFiled: February 9, 2012Publication date: June 21, 2012Applicant: Advanced Technology Materials, Inc.Inventors: Ziyun Wang, Chongying Xu, Thomas H. Baum
-
Patent number: 8198192Abstract: Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. Moreover, a single metal-containing electrode material may be deposited for both types of transistors.Type: GrantFiled: May 7, 2010Date of Patent: June 12, 2012Assignee: GlobalFoundries Inc.Inventors: Richard Carter, Martin Trentzsch, Sven Beyer, Rohit Pal
-
Patent number: 8198184Abstract: An integrated circuit having a gate dielectric layer (414, 614, 814) having an improved nitrogen profile and a method of fabrication. The gate dielectric layer is a graded layer with a significantly higher nitrogen concentration at the electrode surface than near the substrate surface. An amorphous silicon layer (406) may be deposited prior to nitridation to retain the nitrogen concentration at the top surface (416). Alternatively, a thin silicon nitride layer (610) may be deposited after anneal or a wet nitridation process may be performed.Type: GrantFiled: September 30, 2009Date of Patent: June 12, 2012Assignee: Texas Instruments IncorporatedInventors: James Joseph Chambers, Hiroaki Niimi, Luigi Colombo
-
Patent number: 8188490Abstract: The present invention discloses an organic light emitting diode and a manufacturing method thereof. The OLED comprises a first electrode, a first hole-transporting layer disposed on the first electrode, a second hole-transporting layer disposed on the first hole-transporting layer, a first light-emitting layer disposed on the second hole-transporting layer, an electron-transporting layer disposed on the first light-emitting layer, an electron injection layer disposed on the electron-transporting layer and a second electrode disposed on the electron injection layer. The energy level of the first light-emitting layer in the lowest unoccupied molecular orbital is lower than that of the second hole-transporting layer, and the thickness of the first hole-transporting layer is larger than that of the second hole-transporting layer.Type: GrantFiled: November 12, 2010Date of Patent: May 29, 2012Assignee: National Tsing Hua UniversityInventors: Jwo-Huei Jou, Kuo-Yen Tsend
-
Patent number: 8187973Abstract: A method for manufacturing a semiconductor device which includes: alternately supplying a silicon source and an oxidant to deposit a silicon oxide film on a surface of a semiconductor substrate, wherein the silicon source is supplied under a supply condition where an adsorption amount of molecules of the silicon source on the semiconductor substrate is increased without causing an adsorption saturation of the molecules of the silicon source on the semiconductor substrate, and wherein the oxidant is supplied under a supply condition where impurities remain in the molecules of the silicon source adsorbed on the semiconductor substrate.Type: GrantFiled: March 16, 2009Date of Patent: May 29, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Katsuyuki Sekine, Kazuhei Yoshinaga
-
Patent number: 8187982Abstract: The invention permits a plurality of strips of resin adhesive film having a desired width and unwound from a single feeding reel to be simultaneously pasted on a solar cell. For this purpose, the invention comprises the steps of: unwinding a resin adhesive film sheet from a reel on which the resin adhesive film sheet is wound; splitting the unwound resin adhesive film into two or more film strips in correspondence to lengths of wiring material to bond; pasting the strips of resin adhesive film on an electrode of the solar cell; and placing the individual lengths of wiring material on the electrode of the solar cell having the plural strips of resin adhesive film pasted thereon and thermally setting the resin adhesive film by heating so as to fix together the electrode of the solar cell and the wiring material.Type: GrantFiled: March 22, 2010Date of Patent: May 29, 2012Assignee: Sanyo Electric Co., Ltd.Inventors: Yousuke Ishii, Shingo Okamoto
-
Patent number: 8178400Abstract: A semiconductor fabrication method includes depositing a dummy gate layer onto a substrate, patterning the dummy gate layer, depositing a hardmask layer over the dummy gate layer, patterning the hardmask layer, etching a recess into the substrate, adjacent the dummy gate layer, depositing a semiconductor material into the recess, removing the hardmask layer, depositing replacement spacers onto the dummy gate layer, performing an oxide deposition over the dummy gate layer and replacement spacers, removing the dummy gate and replacement spacers, thereby forming a gate recess in the oxide and depositing a gate stack into the recess.Type: GrantFiled: September 28, 2009Date of Patent: May 15, 2012Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Amlan Majumdar
-
Patent number: 8174078Abstract: An embodiment is a method and apparatus to fabricate a flat panel display. A poly-last structure is formed for a display panel using an amorphous silicon or amorphous silicon compatible process. The poly-last structure has a channel silicon precursor. The display panel is formed from the poly-last structure using a polysilicon specific or polysilicon compatible process.Type: GrantFiled: November 15, 2010Date of Patent: May 8, 2012Assignee: Palo Alto Research Center IncorporatedInventors: Jackson H. Ho, Jeng Ping Lu
-
Patent number: 8163626Abstract: Embodiments described herein generally relate to flash memory devices and methods for manufacturing flash memory devices. In one embodiment, a method for selective removal of nitrogen from the nitrided areas of a substrate is provided. The method comprises positioning a substrate comprising a material layer disposed adjacent to an oxide containing layer in a processing chamber, exposing the substrate to a nitridation process to incorporate nitrogen onto the material layer and the exposed areas of the oxide containing layer, and exposing the nitrided material layer and the nitrided areas of the oxide containing layer to a gas mixture comprising a quantity of a hydrogen containing gas and a quantity of an oxygen containing gas to selectively remove nitrogen from the nitrided areas of the oxide containing layer relative to the nitrided material layer using a radical oxidation process.Type: GrantFiled: June 15, 2010Date of Patent: April 24, 2012Assignee: Applied Materials, Inc.Inventors: Johanes Swenburg, David Chu, Theresa Kramer Guarini, Yonah Cho, Udayan Ganguly, Lucien Date
-
Patent number: 8158535Abstract: A method for forming an insulating film includes a step of preparing a substrate, which is to be processed and has silicon exposed on the surface, a step of performing oxidizing to the silicon on the surface, and forming a silicon oxide thin film on the surface of the silicon, a step of performing first nitriding to the silicon oxide film and the base silicon thereof, and forming a silicon oxynitride film, and a step of performing first heat treatment to the silicon oxynitride film in N2O atmosphere. In such method, a step of performing second nitriding to the silicon oxynitride film may be further included after the first heat treatment, and furthermore, a step of performing second heat treatment to the silicon oxynitride film after the second nitriding may be included.Type: GrantFiled: December 20, 2007Date of Patent: April 17, 2012Assignee: Tokyo Electron LimitedInventors: Minoru Honda, Yoshihiro Sato, Toshio Nakanishi
-
Patent number: 8143134Abstract: The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after separation by favorably separating a single crystal semiconductor substrate even in the case where a non-mass-separation type ion irradiation method is used, and to improve planarity of a surface of a single crystal semiconductor layer after separation as well as to improve throughput.Type: GrantFiled: September 28, 2009Date of Patent: March 27, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takeshi Shichi, Junichi Koezuka, Hideto Ohnuma, Shunpei Yamazaki
-
Publication number: 20120071005Abstract: A heat treating apparatus, which performs a specified heat treatment on a target object, includes a processing chamber accommodating therein the target object; a mounting table for mounting thereon the target object; a vacuum exhaust system for vacuum evacuating the processing chamber; an electromagnetic wave supply unit for irradiating an electromagnetic wave onto the target object to heat the target object; and a controller for controlling the heat treating apparatus such that the electromagnetic wave is irradiated onto the target object at a high vacuum level at which plasma is not generated. Further, a heat treating method performs a specified heat treatment on a target object, wherein the target object is accommodated in a processing chamber capable of being vacuum evacuated, and the target object is heated by irradiating an electromagnetic wave thereon at a high vacuum level at which plasma is not generated in the processing chamber.Type: ApplicationFiled: November 28, 2011Publication date: March 22, 2012Applicant: TOKYO ELECTRON LIMITEDInventor: Masahiro SHIMIZU
-
Patent number: 8138070Abstract: A method of forming a multi-doped junction is disclosed. The method includes providing a first substrate and a second substrate. The method also includes depositing a first ink on a first surface of each of the first substrate and the second substrate, the first ink containing a first set of nanoparticles and a first set of solvents, the first set of nanoparticles containing a first concentration of a first dopant. The method further includes depositing a second ink on a second surface of each of the first substrate and the second substrate, the second ink containing a second set of nanoparticles and a second set of solvents, the second set of nanoparticles containing a second concentration of a second dopant. The method also includes placing the first substrate and the second substrate in a back to back configuration; and heating the first substrate and the second substrate in a first drive-in ambient to a first temperature and for a first time period.Type: GrantFiled: November 25, 2009Date of Patent: March 20, 2012Assignee: Innovalight, Inc.Inventors: Maxim Kelman, Michael Burrows, Dmitry Poplavskyy, Giuseppe Scardera, Daniel Kray, Elena Rogojina
-
Patent number: 8134194Abstract: Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material between the first conductive material and the second conductive material. A resistance of the memory component is configurable via a current conducted from the first conductive material through the oxide material to the second conductive material. Other embodiments include a diode including metal and a dielectric material and a memory component connected in series with the diode. The memory component includes a magnetoresistive material and has a resistance that is changeable via a current conducted through the diode and the magnetoresistive material.Type: GrantFiled: May 22, 2008Date of Patent: March 13, 2012Assignee: Micron Technology, Inc.Inventor: Chandra Mouli
-
Patent number: 8133768Abstract: The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.Type: GrantFiled: September 15, 2009Date of Patent: March 13, 2012Assignees: NthDegree Technologies Worldwide Inc, The United States of America as represented by the Unites States National Aeronautics and Space AdministrationInventors: William Johnstone Ray, Mark D. Lowenthal, Neil O. Shotton, Richard A. Blanchard, Mark Allan Lewandowski, Kirk A. Fuller, Donald Odell Frazier
-
Publication number: 20120045904Abstract: Embodiments of the disclosure generally provide methods of forming a hydrogen free silicon containing layer in TFT devices. The hydrogen free silicon containing layer may be used as a passivation layer, a gate dielectric layer, an etch stop layer, or other suitable layers in TFT devices, photodiodes, semiconductor diode, light-emitting diode (LED), or organic light-emitting diode (OLED), or other suitable display applications. In one embodiment, a method for forming a hydrogen free silicon containing layer in a thin film transistor includes supplying a gas mixture comprising a hydrogen free silicon containing gas and a reacting gas into a plasma enhanced chemical vapor deposition chamber, wherein the hydrogen free silicon containing gas is selected from a group consisting of SiF4, SiCl4, Si2Cl6, and forming a hydrogen free silicon containing layer on the substrate in the presence of the gas mixture.Type: ApplicationFiled: August 20, 2011Publication date: February 23, 2012Applicant: APPLIED MATERIALS, INC.Inventor: Soo Young Choi