Abstract: A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.

Abstract: In an embodiment, an interposer includes multiple integrated circuits coupled thereto. The integrated circuits may include processors and non-processor functionality that may have previously been integrated with the processors on an SOC. By separating the functionality into multiple integrated circuits, the integrated circuits may be arranged on the interposer to spread out the potentially high power ICs and lower power ICs, interleaving them. In other embodiments, instances of the integrated circuits (e.g. processors) from different manufacturing process conditions may be selected to allow a mix of high performance, high power density integrated circuits and lower performance, low power density integrated circuits. In an embodiment, a phase change material may be in contact with the integrated circuits, providing a local reservoir to absorb heat. In an embodiment, a battery or display components may increase thermal mass and allow longer optimal performance state operation.

Abstract: Thin AlN films are oxidatively treated in a plasma to form AlO and AlON films without causing damage to underlying layers of a partially fabricated semiconductor device (e.g., to underlying metal and/or dielectric layers). The resulting AlO and AlON films are characterized by improved leakage current compared to the AlN film and are suitable for use as etch stop layers. The oxidative treatment involves contacting the substrate having an exposed AlN layer with a plasma formed in a process gas comprising an oxygen-containing gas and a hydrogen-containing gas. In some implementations oxidative treatment is performed with a plasma formed in a process gas including CO2 as an oxygen-containing gas, H2 as a hydrogen-containing gas, and further including a diluent gas. The use of a hydrogen-containing gas in the plasma eliminates the oxidative damage to the underlying layers.

Abstract: A manufacturing method of a semiconductor device including the following steps is provided. A substrate having a device structure and a first interconnection structure on a front side is provided. A first annealing process is performed in an atmosphere of pure hydrogen at a first temperature. A second interconnection structure is formed on a back side of the substrate. A second annealing process is performed in an atmosphere of gas mixture including hydrogen at a second temperature.

Abstract: A method for processing a workpiece is provided. The method can include placing a workpiece on a susceptor disposed within a processing chamber. The method can include performing a multi-cycle thermal treatment process on the workpiece in the processing chamber. The multi-cycle thermal treatment process can include at least two thermal cycles. Each thermal cycle of the at least two thermal cycles can include performing a first treatment on the workpiece at a first temperature; heating a device side surface of the workpiece to a second temperature in less than one second; performing a second treatment on the workpiece at approximately the second temperature; and cooling the workpiece subsequent to performing the second treatment.

Abstract: A method of manufacturing a magnetoresistive random access memory device, the method including forming a memory structure on a substrate, the memory structure including a lower electrode, a magnetic tunnel junction structure, and an upper electrode sequentially stacked; forming a first capping layer to cover a surface of the memory structure by a deposition process using a plasma under first conditions; and forming a second capping layer on the first capping layer by a deposition process using a plasma under second conditions different from the first conditions.

Abstract: A middle-of-line interconnect structure including copper interconnects and integral copper alloy caps provides effective electromigration resistance. A metal cap layer is deposited on the top surfaces of the interconnects. A post-deposition anneal causes formation of the copper alloy caps from the interconnects and the metal cap layer. Selective removal of unalloyed metal cap layer material provides an interconnect structure free of metal residue on the dielectric material layer separating the interconnects.

Abstract: A method of manufacturing a semiconductor device includes forming a film on a substrate by overlapping the following during at least a certain period: (a) supplying a first source to the substrate, the first source including at least one of an inorganic source containing a specific element and a halogen element and an organic source containing the specific element and the halogen element; (b) supplying a second source to the substrate, the second source including at least one of amine, organic hydrazine, and hydrogen nitride; and (c) supplying a third source to the substrate, the third source including at least one of amine, organic hydrazine, hydrogen nitride, and organic borane.

Abstract: A method of processing a substrate according to a PECVD process is described. Temperature profile of the substrate is adjusted to change deposition rate profile across the substrate. Plasma density profile is adjusted to change deposition rate profile across the substrate. Chamber surfaces exposed to the plasma are heated to improve plasma density uniformity and reduce formation of low quality deposits on chamber surfaces. In situ metrology may be used to monitor progress of a deposition process and trigger control actions involving substrate temperature profile, plasma density profile, pressure, temperature, and flow of reactants.

Abstract: A method of manufacturing a magnetoresistive random access memory device, the method including forming a memory structure on a substrate, the memory structure including a lower electrode, a magnetic tunnel junction structure, and an upper electrode sequentially stacked; forming a first capping layer to cover a surface of the memory structure by a deposition process using a plasma under first conditions; and forming a second capping layer on the first capping layer by a deposition process using a plasma under second conditions different from the first conditions.

Abstract: A method of depositing ALD films on semiconductor substrates processed in a micro-volume of a plasma enhanced atomic layer deposition (PEALD) reaction chamber wherein a single semiconductor substrate is supported on a ceramic surface of a pedestal and process gas is introduced through gas outlets in a ceramic surface of a showerhead into a reaction zone above the semiconductor substrate, includes (a) cleaning the ceramic surfaces of the pedestal and showerhead with a fluorine plasma such that aluminum-rich byproducts are formed on the ceramic surfaces, (b) depositing a conformal halide-free atomic layer deposition (ALD) oxide undercoating on the ceramic surfaces so as to cover the aluminum-rich byproducts, (c) depositing a pre-coating on the halide-free ALD oxide undercoating, and (d) processing a batch of semiconductor substrates by transferring each semiconductor substrate into the reaction chamber and depositing a film on the semiconductor substrate supported on the ceramic surface of the pedestal.

Abstract: A semiconductor device (100A) includes a substrate (11); a TFT (10A) supported on the substrate, the TFT including an oxide semiconductor layer (16); an organic insulating layer (24) covering the TFT; a lower layer electrode (32) on the organic insulating layer; a dielectric layer (34) on the lower layer electrode; an upper layer electrode on the dielectric layer; and an upper layer electrode (36) including a portion opposing the lower layer electrode via the dielectric layer. The dielectric layer is a silicon nitride film having a hydrogen content of 5.33×1021 atoms/cm3 or less.

Abstract: In a transistor having a top-gate structure in which a gate electrode layer overlaps with an oxide semiconductor layer which faints a channel region with a gate insulating layer interposed therebetween, when a large amount of hydrogen is contained in the insulating layer, hydrogen is diffused into the oxide semiconductor layer because the insulating layer is in contact with the oxide semiconductor layer; thus, electric characteristics of the transistor are degraded. An object is to provide a semiconductor device having favorable electric characteristics. An insulating layer in which the concentration of hydrogen is less than 6×1020 atoms/cm3 is used for the insulating layer being in contact with oxide semiconductor layer which forms the channel region. Using the insulating layer, diffusion of hydrogen can be prevented and a semiconductor device having favorable electric characteristics can be provided.

Abstract: A nitride semiconductor device includes a substrate; a nitride semiconductor multilayer structure which is formed on the substrate, includes a first nitride semiconductor layer and a second nitride semiconductor layer having a different composition from that of the first nitride semiconductor layer, and generates two dimensional electron gas on a hetero interface between the first nitride semiconductor layer and the second nitride semiconductor layer; and an insulating film which covers at least a portion of a surface of the nitride semiconductor multilayer structure, has a concentration of Si—H bonds equal to or less than 6.0×1021 cm?3, and is formed of silicon nitride.

Abstract: A method of forming a gate dielectric layer for a MOS transistor includes the following steps. A gate dielectric layer is formed on a substrate. A nitridation process is performed on the gate dielectric layer. A multi-step post nitridation annealing process including two oxygen-containing annealing steps with different respective annealing temperatures is performed on the gate dielectric layer.

Abstract: A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.

Abstract: One object is to provide a semiconductor device including an oxide semiconductor, which has stable electric characteristics and high reliability. Another object is to manufacture a highly reliable semiconductor device in a high yield. In a top-gate staggered transistor including an oxide semiconductor film, as a first gate insulating film in contact with the oxide semiconductor film, a silicon oxide film is formed by a plasma CVD method with use of a deposition gas containing silicon fluoride and oxygen; and as a second gate insulating film stacked over the first gate insulating film, a silicon oxide film is formed by a plasma CVD method with use of a deposition gas containing silicon hydride and oxygen.

Abstract: Disclosed embodiments include a capacitor structure and a method for forming a capacitor structure. An embodiment is a structure comprising a conductor-insulator-conductor capacitor on a substrate. The conductor-insulator-conductor capacitor comprises a first conductor on the substrate, a dielectric stack over the first conductor, and a second conductor over the dielectric stack. The dielectric stack comprises a first nitride layer, a first oxide layer over the first nitride layer, and a second nitride layer over the first oxide layer. A further embodiment is a method comprising forming a first conductor on a substrate; forming a first nitride layer over the first conductor; treating the first nitride layer with a first nitrous oxide (N2O) treatment to form an oxide layer on the first nitride layer; forming a second nitride layer over the oxide layer; and forming a second conductor over the second nitride layer.

Abstract: There is provided a method for manufacturing a semiconductor device, including forming a film on a substrate by performing a cycle one or more times. The cycle includes forming a first layer containing silicon, nitrogen, and carbon by supplying a first silane-based source having a halogen-based ligand to the substrate and supplying a second silane-based source having amino groups to the substrate. The cycle also includes forming a second layer by modifying the first layer by performing supplying a reactive gas different from each of the sources, to the substrate.

Abstract: There is provided a substrate processing apparatus, including a processing chamber configured to house a substrate, a first source supply system configured to supply a chlorosilane-based source to the substrate in the processing chamber, a second source supply system configured to supply an aminosilane-based source to the substrate in the processing chamber and a reactive gas supply system configured to supply a reactive gas different from each of the sources, to the substrate in the processing chamber. The substrate processing apparatus further includes a controller configured to control the first source supply system, the second source supply system, and the reactive gas supply system, so that a process of forming an insulating film on the substrate is performed by an alternating process.

Abstract: Disclosed are metal-containing precursors having the formula Compound (I) wherein: —M is a metal selected from Ni, Co, Mn, Pd; and —each of R-1, R2, R3, R4, R5, R6, R7, R8, R9, and R10 are independently selected from H; a C1-C4 linear, branched, or cyclic alkyl group; a C1-C4 linear, branched, or cyclic alkylsilyl group (mono, bis, or tris alkyl); a C1-C4 linear, branched, or cyclic alkylamino group; or a C1-C4 linear, branched, or cyclic fluoroalkyl group. Also disclosed are methods of synthesizing and using the disclosed metal-containing precursors to deposit metal-containing films on a substrate via a vapor deposition process.

Abstract: A device includes a tube extending in a longitudinal direction and a hollow channel arranged in the tube. An end part of the tube is formed such that first electromagnetic radiation paths extending in the tube and outside of the hollow channel in the longitudinal direction are focused in a first focus.

Abstract: A method of manufacturing a semiconductor device includes: accommodating a substrate in a processing chamber; and supplying an organosilicon-based gas into the processing chamber that is heated to form a film including silicon and carbon on the substrate. In the forming of the film including silicon and carbon, a cycle is performed a predetermined number of times. The cycle includes supplying the organosilicon-based gas into the processing chamber and confining the organosilicon-based gas in the processing chamber, maintaining a state in which the organosilicon-based gas is confined in the processing chamber, and exhausting an inside of the processing chamber.

Abstract: Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about ?600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of SixByCz, SixByNz, SixByCzNw, BxCy, and BxNy. In some embodiments, a hardmask film includes a germanium-rich GeNx material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.

Abstract: A method of processing a substrate includes performing a first exposure that comprises generating a plasma containing reactive gas ions in a plasma chamber and generating a bias voltage between the substrate and the plasma chamber. The method also includes providing a plasma sheath modifier having an aperture disposed between the plasma and substrate and operable to direct the reactive gas ions toward the substrate, and establishing a pressure differential between the plasma chamber and substrate region while the reactive gas ions are directed onto the substrate.

Abstract: Electronic devices can be prepared by forming a patterned thin film on a suitable receiver substrate. A cyanoacrylate polymer is used as a deposition inhibitor material and applied first as a deposition inhibitor material. The deposition inhibitor material can be patterned to provide selected areas on the receiver substrate where the deposition inhibitor is absent. An inorganic thin film is then deposited on the receiver substrate using a chemical vapor deposition technique only in those areas where the deposition inhibitor material is absent. The cyanoacrylate polymer deposition inhibitor material can be applied by thermal transfer from a donor element to a receiver substrate before a patterned thin film is formed.

Abstract: A process is described for integrating, on an inert substrate, a device having at least one passive component and one active component. The process comprises: deposition of a protection dielectric layer on the inert substrate; formation of a polysilicon island on the protection dielectric layer; integration of the active component on the polysilicon island; deposition of the covering dielectric layer on the protection dielectric layer and on the active component; integration of the passive component on the covering dielectric layer; formation of first contact structures in openings realised in the covering dielectric layer in correspondence with active regions of the active component; and formation of second contact structures in correspondence with the passive component. An integrated device obtained through this process is also described.

Abstract: A method of forming a dielectric film having at least Si—N, Si—C, or Si—B bonds on a semiconductor substrate by atomic layer deposition (ALD), includes: supplying a precursor in a pulse to adsorb the precursor on a surface of a substrate; supplying a reactant gas in a pulse over the surface without overlapping the supply of the precursor; reacting the precursor and the reactant gas on the surface; and repeating the above steps to form a dielectric film having at least Si—N, Si—C, or Si—B bonds on the substrate. The precursor has at least one Si—C or Si—N bond, at least one hydrocarbon, and at least two halogens attached to silicon in its molecule.

Abstract: A silicon oxide film (2) comprising an amorphous phase is deposited on a substrate (1) (see a step (b)) by a plasma CVD method using an SiH4 gas and an N2O gas. Subsequently, a sample comprising the silicon oxide film (2)/the substrate (1) is set on an RTA apparatus. The sample (=the silicon oxide film (2)/the substrate (1)) is heat-treated (rapid heating and rapid cooling) (see a step (c)). In this case, a temperature raising rate is 200° C./s, and a temperature in heat treatment is 1000° C.

Abstract: In a method of manufacturing a semiconductor device, a plurality of sacrificial layers and a plurality of insulating interlayers are repeatedly and alternately on a substrate. The insulating interlayers include a different material from a material of the sacrificial layers. At least one opening through the insulating interlayers and the sacrificial layers are formed. The at least one opening exposes the substrate. The seed layer is formed on an inner wall of the at least one opening using a first silicon source gas. A polysilicon channel is formed in the at least one opening by growing the seed layer. The sacrificial layers are removed to form a plurality of grooves between the insulating interlayers. A plurality of gate structures is formed in the grooves, respectively.

Abstract: A method for amorphizing a layer on a substrate is described. In one embodiment, the method includes treating the substrate with a first gas cluster ion beam (GCIB) using a first beam energy selected to yield an amorphous sub-layer within the substrate of a desired thickness, which produces a first interfacial roughness of an amorphous-crystal interface between the amorphous sub-layer and a crystalline sub-layer of the substrate. The method further includes treating the substrate with a second GCIB using a second beam energy, less than the first beam energy, to reduce the first interfacial roughness of the amorphous-crystal interface to a second interfacial roughness.

Abstract: A method of manufacturing a semiconductor device includes forming a film on a substrate in a process chamber, and removing a deposit from at least a portion of an inside of the process chamber after forming the film, wherein removing the deposit includes performing a cycle a predetermined number of times, the cycle including a first process of supplying a first gas for etching the deposit into the process chamber and a second process of supplying a second gas into the process chamber so as to increase a pressure in the process chamber, the second gas being incapable of etching a member constituting the process chamber or having an etchability against the member lower than that of the first gas.

Abstract: A plasma processing apparatus generates plasma by introducing microwaves into a processing chamber by using a planar antenna having a plurality of slots. By using the plasma processing apparatus, a nitrogen containing gas and a silicon containing gas introduced into the processing chamber are brought into the plasma state, and at the time of depositing by using the plasma a silicon nitride film on the surface of the a substrate to be processed, stress to the silicon nitride film to be formed is controlled by the combination of the type and the processing pressure of the nitrogen containing gas.

Abstract: Strontium ruthenium oxide provides an effective interface between a ruthenium conductor and a strontium titanium oxide dielectric. Formation of the strontium ruthenium oxide includes the use of atomic layer deposition to form strontium oxide and subsequent annealing of the strontium oxide to form the strontium ruthenium oxide. A first atomic layer deposition of strontium oxide is preformed using water as an oxygen source, followed by a subsequent atomic layer deposition of strontium oxide using ozone as an oxygen source.

Abstract: A substrate processing apparatus, including: a reaction container in which a substrate is processed; a seal cap, brought into contact with one end in an opening side of the reaction container via a first sealing member and a second sealing member so as to seal the opening of the reaction container air-tightly; a first gas channel, formed in a region between the first sealing member and the second sealing member in a state where the seal cap is in contact with the reaction container; a second gas channel, provided to the seal cap and through which the first gas channel is in communication with an inside of the reaction container; a first gas supply port that is provided to the reaction container and supplies a first gas to the first gas channel; and a second gas supply port that is provided to the reaction container and supplies a second gas into the reaction container, wherein a front end opening of the first gas supply port opening to the first gas channel, and a base opening of the second gas channel openin

Abstract: When a layered structure of a transparent electrode layer and a metal layer is formed as a back side electrode layer over a surface on a side opposite to a side of incidence of light of a thin film solar battery, a time when formation of the transparent electrode layer is completed and a time when formation of the metal layer is started are made to coincide for one substrate.

Abstract: Disclosed is a substrate processing apparatus and method. The substrate processing apparatus includes a chamber (10) providing an internal space, in which a process is carried out onto a substrate; a gas supply unit (40) supplying a source gas to the internal space; a coil (16) generating an electric field in the internal space to generate plasma from the source gas; and an adjustment ring (50) disposed on a flow path of the plasma toward a support member to adjust the flow of the plasma. The chamber (10) includes a process chamber (12), in which the support member is provided and the process is carried out by the plasma; and a generation chamber (14), in which the plasma is generated by the coil (16), provided on the upper surface of the process chamber (12), and the adjustment ring (50) is installed at the lower end of the generation chamber (14).

Abstract: The present disclosure is related to method for producing a semiconductor device comprising the steps of: providing a semiconductor substrate (1), comprising active components on the surface of said substrate, depositing a top layer (2) of dielectric material on the surface of said substrate or on other dielectric layers present on said surface, etching at least one first opening (7) at least through said top layer, filling said opening(s) at least with a first conductive material (8), and performing a first CMP step, to form said first conductive structures (3,26), etching at least one second opening (13) at least through said top layer, filling said opening(s) at least with a second conductive material (10), and performing a second CMP step, to form said second conductive structures (4,24), wherein the method comprises the step of depositing a common CMP stopping layer (5,25) on said dielectric top layer, before the steps of etching and filling said first opening(s), so that said same CMP stopping layer is

Abstract: A method of depositing a silicon and nitrogen containing film on a substrate. The method includes introducing silicon-containing precursor to a deposition chamber that contains the substrate, wherein the silicon-containing precursor comprises at least two silicon atoms. The method further includes generating at least one radical nitrogen precursor with a remote plasma system located outside the deposition chamber. Moreover, the method includes introducing the radical nitrogen precursor to the deposition chamber, wherein the radical nitrogen and silicon-containing precursors react and deposit the silicon and nitrogen containing film on the substrate. Furthermore, the method includes annealing the silicon and nitrogen containing film in a steam environment to form a silicon oxide film, wherein the steam environment includes water and acidic vapor.

Abstract: Methods of fabricating a silicon oxide layer using an inorganic silicon precursor and methods of fabricating a semiconductor device using the same are provided. The methods of fabricating a semiconductor device include forming a tunnel insulating layer and a charge storage layer on a substrate; forming a dielectric layer structure on the charge storage layer using an atomic layer deposition (ALD) method, the dielectric layer structure including a first dielectric layer formed of silicon oxide, a second dielectric layer on the first dielectric layer formed of a material different from the material forming the first dielectric layer, and a third dielectric layer formed of the silicon oxide on the second dielectric layer; and forming a control gate on the dielectric layer structure.

Abstract: When a layered structure of a transparent electrode layer and a metal layer is formed as a back side electrode layer over a surface on a side opposite to a side of incidence of light of a thin film solar battery, a time when formation of the transparent electrode layer is completed and a time when formation of the metal layer is started are made to coincide for one substrate.

Abstract: A chemical vapor deposition method such as an atomic-layer-deposition method for forming a patterned thin film includes applying a deposition inhibitor material to a substrate. The deposition inhibitor material is a hydrophilic polymer that is has in its backbone, side chains, or both backbone and side chains, multiple secondary or tertiary amide groups that are represented by the following acetamide structure: >N—C(?O)—. The deposition inhibitor material is patterned simultaneously or subsequently to its application to the substrate, to provide selected areas of the substrate effectively not having the deposition inhibitor material. A thin film is substantially deposited only in the selected areas of the substrate not having the deposition inhibitor material.

Abstract: An atomic layer deposition method includes providing a semiconductor substrate within a deposition chamber. A first metal halide-comprising precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. The first monolayer comprises metal and halogen of the metal halide. While flowing the first metal halide-comprising precursor gas to the substrate, H2 is flowed to the substrate within the chamber. A second precursor gas is flowed to the first monolayer effective to react with the first monolayer and form a second monolayer on the substrate. The second monolayer comprises the metal. At least some of the flowing of the first metal halide-comprising precursor gas, at least some of the flowing of the H2, and at least some of the flowing of the second precursor gas are repeated effective to form a layer of material comprising the metal on the substrate.

Abstract: A method includes an act of providing a crystalline substrate with a diamond-type lattice and an exposed substantially (111)-surface. The method also includes an act of forming a graphene layer or a graphene-like layer on the exposed substantially (111)-surface.

Abstract: For providing control of two-step or a multi-step deposition process, a method and a corresponding deposition system is provided comprising providing a deposition process having at least two sub-processes employing different sets of process parameters, wherein each set of process parameters comprises at least one process parameter. The method comprises controllably generating an actual value for at least one first process parameter by taking into account at least one previous value of the respective first process parameter, wherein each first process parameter is a process parameter of said at least two sets of process parameters.

Abstract: A “vertical” coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a target structure in a solution made up of a fine particle solute dispersed in a liquid solvent such that a “waterline” is formed by the upper (liquid/air) surface of the solution on a targeted linear surface region of the substrate. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the straight-line portion of the substrate surface contacted by the receding waterline. The substrate and staining solution are selected such that the liquid solvent has a stronger attraction to the substrate surface than to itself to produce the required pinning and upward curving waterline. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.

Abstract: A method of producing, at atmospheric pressure, an n-type semiconductive indium sulfide thin film on a substrate using an indium-containing precursor, hydrogen sulfide as a reactive gaseous precursor, and an inert carrier gas stream includes cyclically repeating first and second steps so as to produce an indium sulfide thin film of a desired thickness. The first method phase includes converting the indium-containing precursor to at least one of a dissolved and a gaseous phase, heating the substrate to a temperature in a range of 100° C. to 275° C., directing the indium containing precursor onto the substrate and supplying hydrogen sulfide to the indium-containing precursor in a mixing zone in an amount so as to provide an absolute concentration of hydrogen sulfide that is greater than zero and no greater than 1% by volume. The indium concentration of the indium-containing precursor is set so as to produce a compact In(OHx,Xy,Sz)3 film, where X=halide and x+y+2z=1 with z?0.

Abstract: Aminosilane precursors for depositing silicon-containing films, and methods for depositing silicon-containing films from these aminosilane precursors, are described herein. In one embodiment, there is provided an aminosilane precursor for depositing silicon-containing film comprising the following formula (I): (R1R2N)nSiR34-n??(I) wherein substituents R1 and R2 are each independently chosen from an alkyl group comprising from 1 to 20 carbon atoms and an aryl group comprising from 6 to 30 carbon atoms, at least one of substituents R1 and R2 comprises at least one electron withdrawing substituent chosen from F, Cl, Br, I, CN, NO2, PO(OR)2, OR, SO, SO2, SO2R and wherein R in the at least one electron withdrawing substituent is chosen from an alkyl group or an aryl group, R3 is chosen from H, an alkyl group, or an aryl group, and n is a number ranging from 1 to 4.

Abstract: A silicon dioxide material may be provided in sophisticated semiconductor devices in the form of a double liner including an undoped silicon dioxide material in combination with a high density plasma silicon dioxide, thereby providing reduced dependency on pattern density. In some illustrative embodiments, the silicon dioxide double liner may be used as a spacer material and as a hard mask material in process strategies for incorporating a strain-inducing semiconductor material.

Abstract: A film formation process is performed to form a silicon nitride film on a target substrate within a process field configured to be selectively supplied with a first process gas containing a silane family gas and a second process gas containing a nitriding gas. The method is preset to compose the film formation process of a main stage with an auxiliary stage set at one or both of beginning and ending of the film formation process. The main stage includes an excitation period of supplying the second process gas to the process field while exciting the second process gas by an exciting mechanism. The auxiliary stage includes no excitation period of supplying the second process gas to the process field while exciting the second process gas by the exciting mechanism.