Abstract: The present invention provides a method for manufacturing a semiconductor device having multiple gate dielectric thickness layers. The method, in one embodiment, includes forming a first layer of gate dielectric material over a semiconductor substrate in a first active region and a second active region of a semiconductor device, and patterning a masking layer to expose the first layer of gate dielectric material located in the first active region.

Abstract: A semiconductor device 100 includes an element-forming region having gate electrode 108 formed therein, and a circumferential region formed in the outer circumference of the element-forming region and having an element-isolating region 118 formed therein. On the main surface of the semiconductor substrate 101, there is formed a parallel pn layer having an N-type drift region 104 and P-type column regions 106 alternately arranged therein. In the circumferential region, there is formed a field electrode 120, but the field electrode 120 is not formed on the P-type column regions 106. The P-type column regions 106 in the circumferential region are formed with a depth larger than or equal to that of the P-type column regions 106 in the element-forming region.

Abstract: The present invention provides atomic layer deposition systems and methods that include metal compounds with at least one ?-diketiminate ligand. Such systems and methods can be useful for depositing metal-containing layers on substrates.

Abstract: A thin-film formation apparatus possesses a reaction chamber to be evacuated, a placing portion on which a substrate is placed inside the reaction chamber, a gas-dispersion guide installed over the placing portion for supplying a gas onto a substrate surface, a gas-supply port for introducing the gas into the gas-dispersion guide, a gas-dispersion plate disposed on the side of the substrate of the gas-dispersion guide and having multiple gas-discharge pores, a first exhaust port for exhausting, downstream of the gas-dispersion plate, the gas supplied onto the substrate surface from the gas-dispersion plate, and a second exhaust port for exhausting, upstream of the gas-dispersion plate, a gas inside the gas-dispersion guide via a space between the gas-dispersion guide and the gas-dispersion plate.

Abstract: Hemi-spherical structure and method for fabricating the same. A device includes discrete pillar regions on a substrate, and a pattern layer on the discrete support structures and the substrate. The pattern layer has hemi-spherical film regions on the discrete support structures respectively, and planarized portions on the substrate between the hemi-spherical film regions. Each of the hemi-spherical film regions in a position corresponding to each of the support structures serves as a hemi-spherical structure.

Abstract: A gate insulating film made of silicon oxynitride is disposed on the partial surface area of a semiconductor substrate. A gate electrode is disposed on the gate insulating film. Source and drain regions are disposed on both sides of the gate electrode. An existence ratio of subject nitrogen atoms to a total number of nitrogen atoms in the gate insulating film is 20% or smaller, wherein three bonds of each subject nitrogen atom are all coupled to silicon atoms and remaining three bonds of each of three silicon atoms connected to the subject nitrogen atom are all coupled to other nitrogen atoms.

Abstract: A chemical vapor deposition method for forming a dielectric material in a trench formed on a substrate. The method includes flowing a silicon-containing precursor into a process chamber housing the substrate, flowing an oxidizing gas into the chamber, and providing a hydroxyl-containing precursor in the process chamber. The method also includes reacting the silicon-containing precursor, oxidizing gas and hydroxyl-containing precursor to form the dielectric material in the trench. The ratio of the silicon-containing precursor to the oxidizing gas flowed into the chamber is increased over time to alter a rate of deposition of the dielectric material.

Abstract: An improved field effect transistor formed in the Group III nitride material system includes a two part structure in which a chemical vapor deposited passivation layer of silicon nitride encapsulates a previously sputtered-deposited layer of silicon nitride. The sputtered layer provides some of the benefits of passivation and the chemical vapor deposited layer provides an excellent environmental barrier.

Abstract: A method for forming a high density dielectric film by chemical vapor deposition. The method comprises: (a) a substrate is provided in a processing chamber; (b) a first gas is introduced into the processing chamber with a first pressure and adsorbed on the substrate, wherein the first gas comprises silicon-containing or carbon-containing gas; (c) the first gas is stopped, and the first pressure is lowered to a second pressure; (d) a second gas is introduced into the processing chamber with a third pressure, and forced to react with the first gas absorbed on the substrate and remained in the processing chamber, wherein the second gas comprises oxidizer or reduction agent; (e) the steps (b)˜(d) are repeated until a high density dielectric film is formed on the substrate.

Abstract: A method of depositing tensile or compressively stressed silicon nitride on a substrate is described. Silicon nitride having a tensile stress with an absolute value of at least about 1200 MPa can be deposited from process gas comprising silicon-containing gas and nitrogen-containing gas, maintained in an electric field having a strength of from about 25 V/mil to about 300 V/mil. The electric field is formed by applying a voltage at a power level of less than about 60 Watts across electrodes that are spaced apart by a separation distance that is at least about 600 mils. Alternatively, silicon nitride having a compressive stress with an absolute value of at least about 2000 MPa can be formed in an electric field having a strength of from about 400 V/mil to about 800 V/mil.

Abstract: A method for forming a gate dielectric layer is described. A silicon oxide layer is formed on a semiconductor substrate. Then, a first and a second nitrogen doping processes are performed in sequence to the silicon oxide layer using plasma comprising inert gas and gaseous nitrogen to form a gate dielectric layer. The first nitrogen doping process is performed at a lower power, a lower pressure and a higher inert gas to nitrogen gas ratio than those at the second nitrogen doping process. The combination of the deeper nitrogen distribution of the first nitrogen doping process and the shallower nitrogen distribution of the second nitrogen doping process produces a flatter total nitrogen distribution profile so that leakage current from electron tunneling through the gate dielectric layer can be reduced.

Abstract: A BiCMOS method for forming bipolar junction transistors and CMOS devices in a substrate. To avoid erosion of the bipolar junction transistor material layers, gate spacers for the CMOS devices are formed while a bipolar junction transistor photoresist layer is in place. The photoresist layer is used for etching the emitter polysilicon layer (for single polysilicon layer bipolar junction transistors) or for etching the base polysilicon layer (for double polysilicon layer bipolar junction transistors) prior to gate spacer etch.

Abstract: A method for forming an oxide film includes a first in-situ steam generation (ISSG) process using a 1%-H2 concentration in the ambient gas and a subsequent second ISSG process using a 5%-H2 concentration in the ambient gas, wherein the second ISSG process compensates an in-plane thickness distribution of the film formed by the first ISSG process. The time length for the first and second ISSG steps is determined based on a desired film thickness, a time length dependency of a film formed by the second ISSG process, and the oxidation rate of the first and second ISSG processes.

Abstract: A method for forming a thin film on a substrate layer by layer using plasma enhanced atomic layer deposition is described. The method comprises using a low power reduction step for at least one cycle in order to substantially avoid partial layer film growth, followed by using a high power reduction step for each cycle thereafter in order to increase deposition rate.

Abstract: A method of forming phoslon (PNO) comprising the following steps. A CVD reaction chamber having a reaction temperature of from about 300 to 600° C. is provided. From about 10 to 200 sccm PH3 gas, from about 50 to 4000 sccm N2 gas and from about 50 to 1000 sccm NH3 gas are introduced into the CVD reaction chamber. Either from about 10 to 200 sccm O2 gas or from about 50 to 1000 sccm N2O gas is introduced into the CVD reaction chamber. An HFRF power of from about 0 watts to 4 kilowatts is also employed. An LFRF power of from about 0 to 5000 watts may also be employed. Employing a phoslon etch stop layer in a borderless contact fabrication. Employing a phoslon lower etch stop layer and/or a phoslon middle etch stop layer in a dual damascene fabrication.

Abstract: A method of forming an aluminum containing film on a substrate includes providing a precursor having the chemical structure: Al(NR1R2)(NR3R4)(NR5R6); where each of R1, R2, R3, R4, R5 and R6 is independently selected from the group consisting of hydrogen and an alkyl group including at least two carbon atoms. The precursor is utilized to form a film on the substrate including at least one of aluminum oxide, aluminum nitride and aluminum oxy-nitride. Each of the R1–R6 groups can be the same or different and can by straight or branched chain alkyls. An exemplary precursor that has is useful in forming aluminum containing films is tris diethylamino aluminum.