Formed By Deposition From A Gas Or Vapor (epo) Patents (Class 257/E21.269)
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Patent number: 8110490Abstract: A method of manufacturing a semiconductor device comprising forming a gate oxide layer over a substrate subjecting the gate oxide layer to a first nitridation process, subjecting the gate oxide layer to a first anneal process after the first nitridation process, subjecting the gate oxide layer to a second nitridation process after the first anneal process, subjecting the gate oxide layer to a second anneal process after the second nitridation process, and forming a gate electrode over the gate oxide.Type: GrantFiled: August 15, 2007Date of Patent: February 7, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Matt Yeh, Da-Yuan Lee, Chi-Chun Chen, Hun-Jan Tao
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Patent number: 8093158Abstract: Provided are a semiconductor device manufacturing method and a substrate processing apparatus. The method comprise: a first process of forming a film containing a predetermined element on a substrate by supplying a source gas containing the predetermined element to a substrate processing chamber in which the substrate is accommodated; a second process of removing the source gas remaining in the substrate processing chamber by supplying an inert gas to the substrate processing chamber; a third process of modifying the predetermined element-containing film formed in the first process by supplying a modification gas that reacts with the predetermined element to the substrate processing chamber; a fourth process of removing the modification gas remaining in the substrate processing chamber by supplying an inert gas to the substrate processing chamber; and a filling process of filling an inert gas in a gas tank connected to the substrate processing chamber.Type: GrantFiled: March 30, 2010Date of Patent: January 10, 2012Assignee: Hitachi Kokusai Electric, Inc.Inventors: Taketoshi Sato, Masayuki Tsuneda
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Patent number: 8039374Abstract: Techniques for low temperature ion implantation are provided to improve throughput. Specifically, the pressure of the backside gas may temporarily, continually or continuously increase before the starting of the implant process, such that the wafer may be quickly cooled down from room temperature to be essentially equal to the prescribed implant temperature. Further, after the vacuum venting process, the wafer may wait an extra time in the load lock chamber before the wafer is moved out the ion implanter, in order to allow the wafer temperature to reach a higher temperature quickly for minimizing water condensation on the wafer surface. Furthermore, to accurately monitor the wafer temperature during a period of changing wafer temperature, a non-contact type temperature measuring device may be used to monitor wafer temperature in a real time manner with minimized condensation.Type: GrantFiled: March 19, 2010Date of Patent: October 18, 2011Assignee: Advanced Ion Beam Technology, Inc.Inventors: John D. Pollock, Zhimin Wan, Erik Collart
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Patent number: 8026606Abstract: A structure and a method for forming the same. The structure includes (a) an interlevel dielectric (ILD) layer; (b) a first electrically conductive line and a second electrically conductive line both residing in the ILD layer; (c) a diffusion barrier region residing in the ILD layer. The diffusion barrier region (i) physically isolates, (ii) electrically couples together, and (iii) are in direct physical contact with the first and second electrically conductive lines. The first and second electrically conductive lines each comprises a first electrically conductive material. The diffusion barrier region comprises a second electrically conductive material different from the first electrically conductive material. The diffusion barrier region is adapted to prevent a diffusion of the first electrically conductive material through the diffusion barrier region.Type: GrantFiled: August 25, 2009Date of Patent: September 27, 2011Assignee: International Business Machines CorporationInventors: Stephen Ellinwood Luce, Thomas Leddy McDevitt, Anthony Kendall Stamper
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Patent number: 7998878Abstract: A chemical vapor deposition method such as an atomic-layer-deposition method for forming a patterned thin film includes applying a deposition inhibitor material to a substrate. The deposition inhibitor material is a hydrophilic polymer that is soluble in an aqueous solution comprising at least 50 weight % water and has an acid content of less than 2.5 meq/g of polymer. The deposition inhibitor material is patterned simultaneously or subsequently to its application to the substrate, to provide selected areas of the substrate effectively not having the deposition inhibitor material. A thin film is substantially deposited only in the selected areas of the substrate not having the deposition inhibitor material.Type: GrantFiled: November 20, 2009Date of Patent: August 16, 2011Assignee: Eastman Kodak CompanyInventors: David H. Levy, Lee W. Tutt
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Patent number: 7985679Abstract: An atomic layer deposition method includes providing a semiconductor substrate within a deposition chamber. A first metal halide-comprising precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. The first monolayer comprises metal and halogen of the metal halide. While flowing the first metal halide-comprising precursor gas to the substrate, H2 is flowed to the substrate within the chamber. A second precursor gas is flowed to the first monolayer effective to react with the first monolayer and form a second monolayer on the substrate. The second monolayer comprises the metal. At least some of the flowing of the first metal halide-comprising precursor gas, at least some of the flowing of the H2, and at least some of the flowing of the second precursor gas are repeated effective to form a layer of material comprising the metal on the substrate.Type: GrantFiled: July 22, 2009Date of Patent: July 26, 2011Assignee: Micron Technology, Inc.Inventor: Guy T. Blalock
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Patent number: 7972898Abstract: The present invention relates to a process of making a zinc-oxide-based thin film semiconductor, for use in a transistor, comprising thin film deposition onto a substrate comprising providing a plurality of gaseous materials comprising first, second, and third gaseous materials, wherein the first gaseous material is a zinc-containing volatile material and the second gaseous material is reactive therewith such that when one of the first or second gaseous materials are on the surface of the substrate the other of the first or second gaseous materials will react to deposit a layer of material on the substrate, wherein the third gaseous material is inert and wherein a volatile indium-containing compound is introduced into the first reactive gaseous material or a supplemental gaseous material.Type: GrantFiled: September 26, 2007Date of Patent: July 5, 2011Assignee: Eastman Kodak CompanyInventors: Peter J. Cowdery-Corvan, David H. Levy, Thomas D. Pawlik, Diane C. Freeman, Shelby F. Nelson
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Patent number: 7939442Abstract: Strontium ruthenium oxide provides an effective interface between a ruthenium conductor and a strontium titanium oxide dielectric. Formation of the strontium ruthenium oxide includes the use of atomic layer deposition to form strontium oxide and subsequent annealing of the strontium oxide to form the strontium ruthenium oxide. A first atomic layer deposition of strontium oxide is preformed using water as an oxygen source, followed by a subsequent atomic layer deposition of strontium oxide using ozone as an oxygen source.Type: GrantFiled: April 10, 2009Date of Patent: May 10, 2011Assignee: Micron Technology, Inc.Inventors: Bhaskar Srinivasan, Vassil Antonov, John Smythe
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Patent number: 7927982Abstract: A silicon-based thin film mass-producing apparatus, including transparent electrodes placed to face in parallel to corresponding counter electrodes with a space therebetween, and silicon-based thin films are deposited on the transparent electrodes by feeding a raw material gas for depositing the silicon-based thin films into the chamber and by applying a DC pulse voltage to the counter electrodes to generate plasma. Unlike methods in which a radio frequency voltage is intermittently applied to perform discharge, a high plasma density distribution does not occur, and in-plane film thickness distribution does not occur. Furthermore, since the DC pulse voltage rises sharply, the ON period can be shortened. As a result, generation of a sheath ceases in the transient state before reaching the steady state, and the thickness of the sheath is small, which allows the space between the counter and transparent electrodes to decrease.Type: GrantFiled: March 26, 2009Date of Patent: April 19, 2011Assignee: NGK Insulators, Ltd.Inventors: Minoru Imaeda, Yuichiro Imanishi, Takao Saito
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Patent number: 7927981Abstract: A silicon-based thin film depositing apparatus, including a plurality of transparent electrodes disposed to face corresponding counter electrodes with a space therebetween. Subsequently, while injecting a raw material gas from raw material gas injection orifices toward the supporting electrodes and also injecting a barrier gas from barrier gas injection orifices in the same direction as the direction in which the raw material gas is injected, the gases are discharged from a gas outlet, and thereby, the pressure in a chamber is controlled to a pressure of more than 1 kPa. Then, a DC pulse voltage is applied to each counter electrode to deposit a silicon-based thin film. A DC pulse voltage is applied to perform discharge. Therefore, even in a state where the distance between the electrodes is increased, plasma can be generated efficiently, and the in-plane distribution of film thickness can be improved.Type: GrantFiled: March 26, 2009Date of Patent: April 19, 2011Assignee: NGK Insulators, Ltd.Inventors: Minoru Imaeda, Yuichiro Imanishi, Takao Saito
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Publication number: 20110065287Abstract: A method is provided for forming a metal-silicon-containing film on a substrate by pulsed chemical vapor deposition. The method includes providing the substrate in a process chamber, maintaining the substrate at a temperature suited for chemical vapor deposition of a metal-silicon-containing film by thermal decomposition of a metal-containing gas and a silicon-containing gas on the substrate, exposing the substrate to a continuous flow of the metal-containing gas, and during the continuous flow, exposing the substrate to sequential pulses of the silicon-containing gas.Type: ApplicationFiled: September 11, 2009Publication date: March 17, 2011Applicant: TOKYO ELECTRON LIMITEDInventor: Cory Wajda
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Patent number: 7897518Abstract: According to the present invention, when a nitridation process by plasma generated by a microwave is applied to a substrate with an oxide film having been formed thereon to form an oxynitride film, the microwave is intermittently supplied. By the intermittent supply of the microwave, ion bombardment is reduced in accordance with a decrease in electron temperature, and a diffusion velocity of nitride species in the oxide film lowers, which as a result makes it possible to prevent nitrogen from concentrating in a substrate-side interface of an oxynitride film to increase the nitrogen concentration therein. Consequently, it is possible to improve quality of the oxynitride film, resulting in a reduced leakage current, an improved operating speed, and improved NBTI resistance.Type: GrantFiled: April 9, 2010Date of Patent: March 1, 2011Assignee: Tokyo Electron LimitedInventors: Seiji Matsuyama, Toshio Nakanishi, Shigenori Ozaki, Hikaru Adachi, Koichi Takatsuki, Yoshihiro Sato
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Publication number: 20110045676Abstract: Methods of seasoning a remote plasma system are described. The methods include the steps of flowing a silicon-containing precursor into a remote plasma region to deposit a silicon containing film on an interior surface of the remote plasma system. The methods reduce reactions with the seasoned walls during deposition processes, resulting in improved deposition rate, improved deposition uniformity and reduced defectivity during subsequent deposition.Type: ApplicationFiled: August 18, 2009Publication date: February 24, 2011Applicant: Applied Materials, Inc.Inventors: Soonam Park, Soo Jeon, Toan Q. Tran, Jang-Gyoo Yang, Qiwei Liang, Dmitry Lubomirsky
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Patent number: 7884032Abstract: A system, method and apparatus is capable of producing layers of various materials stacked on one another on a substrate without exposing the substrate to the pressure and contaminants of ambient air until the stack is complete. In one aspect, the stack of layers can include both an insulative layer of one or more insulative films, and a conductive metal layer of one or more conductive metal layer films. In another aspect, a bias signal of positive and negative voltage pulses may be applied to a target of a deposition chamber to facilitate deposition of the target material in a suitable fashion. In yet another aspect, one or more of the deposition chambers may have associated therewith a pump which combines a turbomolecular pump and a cryogenic pump to generate an ultra high vacuum in that chamber. Other features are described and claimed.Type: GrantFiled: October 28, 2005Date of Patent: February 8, 2011Assignee: Applied Materials, Inc.Inventors: Mengqi Ye, Peijun Ding, Hougong Wang, Zhendong Liu
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Patent number: 7867916Abstract: A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.Type: GrantFiled: June 15, 2009Date of Patent: January 11, 2011Assignee: Palo Alto Research Center IncorporatedInventors: Sanjiv Sambandan, Robert A. Street, Ana Claudia Arias
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Patent number: 7858510Abstract: Protective caps residing at an interface between metal lines and dielectric diffusion barrier (or etch stop) layers are used to improve electromigration performance of interconnects. Protective caps are formed by depositing a first layer of aluminum-containing material over an exposed copper line by treating an oxide-free copper surface with an organoaluminum compound in an absence of plasma at a substrate temperature of at least about 350° C. The formed aluminum-containing layer is passivated either partially or completely in a chemical conversion which forms Al—N, Al—O or both Al—O and Al—N bonds in the layer. Passivation is performed in some embodiments by contacting the substrate having an exposed first layer with an oxygen-containing reactant and/or nitrogen-containing reactant in the absence of plasma. Protective caps can be formed on substrates comprising exposed ULK dielectric.Type: GrantFiled: January 19, 2010Date of Patent: December 28, 2010Assignee: Novellus Systems, Inc.Inventors: Ananda Banerji, George Andrew Antonelli, Jennifer O'loughlin, Mandyam Sriram, Bart van Schravendijk, Seshasayee Varadarajan
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Patent number: 7846795Abstract: A bit line of a semiconductor device includes a first interlayer dielectric film disposed on a semiconductor substrate, a plurality of bit line stacks disposed on the first interlayer dielectric film, a plurality of bit line spacers disposed on side walls of the bit line stacks, and a buffer film disposed on the bit line spacers, the first interlayer dielectric film and the bit line stacks; and a method for fabricating the same.Type: GrantFiled: June 18, 2008Date of Patent: December 7, 2010Assignee: Hynix Semiconductor Inc.Inventor: Jie Won Chung
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Patent number: 7825014Abstract: A method for fabricating a semiconductor device includes forming a pattern including a first layer including tungsten, performing a gas flowing process on the pattern in a gas ambience including nitrogen, and forming a second layer over the pattern using a source gas including nitrogen, wherein the purge is performed at a given temperature for a given period of time in a manner that a reaction between the first layer and the nitrogen used when forming the second layer is controlled.Type: GrantFiled: June 30, 2008Date of Patent: November 2, 2010Assignee: Hynix Semiconductor Inc.Inventors: Min-Gyu Sung, Hong-Seon Yang, Tae-Kwon Lee, Won Kim, Kwan-Yong Lim, Seung-Ryong Lee
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Publication number: 20100261355Abstract: A method for forming a high quality insulation layer on a semiconductor device is presented. The method includes a first step of supplying any one of a silicon source gas and an oxygen source gas into a process chamber in which a semiconductor substrate is placed; a second step of simultaneously supplying the silicon source gas and the oxygen source gas into the process chamber having undergone the first step and depositing a silicon oxide layer on the semiconductor substrate; and a third step of supplying any one of the silicon source gas and the oxygen source gas into the process chamber having undergone the second step.Type: ApplicationFiled: June 29, 2009Publication date: October 14, 2010Inventors: Sang Tae AHN, Ja Chun KU, Seung Joon JEON
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Patent number: 7795143Abstract: A substrate processing apparatus, including: a reaction container in which a substrate is processed; a seal cap, brought into contact with one end in an opening side of the reaction container via a first sealing member and a second sealing member so as to seal the opening of the reaction container air-tightly; a first gas channel, formed in a region between the first sealing member and the second sealing member in a state where the seal cap is in contact with the reaction container; a second gas channel, provided to the seal cap and through which the first gas channel is in communication with an inside of the reaction container; a first gas supply port that is provided to the reaction container and supplies a first gas to the first gas channel; and a second gas supply port that is provided to the reaction container and supplies a second gas into the reaction container, wherein a front end opening of the first gas supply port opening to the first gas channel, and a base opening of the second gas channel openinType: GrantFiled: August 9, 2007Date of Patent: September 14, 2010Assignee: Hitachi Kokusai Electric Inc.Inventors: Kiyohiko Maeda, Takeo Hanashima, Masanao Osanai
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Publication number: 20100173495Abstract: Aspects of the invention include a method and apparatus for processing a substrate using a multi-chamber processing system (e.g., a cluster tool) adapted to process substrates in one or more batch and/or single substrate processing chambers to increase the system throughput. In one embodiment, a system is configured to perform a substrate processing sequence that contains batch processing chambers only, or batch and single substrate processing chambers, to optimize throughput and minimize processing defects due to exposure to a contaminating environment. In one embodiment, a batch processing chamber is used to increase the system throughput by performing a process recipe step that is disproportionately long compared to other process recipe steps in the substrate processing sequence that are performed on the cluster tool. In another embodiment, two or more batch chambers are used to process multiple substrates using one or more of the disproportionately long processing steps in a processing sequence.Type: ApplicationFiled: March 16, 2010Publication date: July 8, 2010Inventors: Randhir Thakur, Steve G. Ghanayem, Joseph Yudovsky, Aaron Webb, Adam Alexander Brailove, Nir Merry, Vinay K. Shah, Andreas G. Hegedus
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Patent number: 7745872Abstract: An operation method for a non-volatile memory structure formed between two doping regions serving as bit lines in a semiconductor substrate, the non-volatile memory structure comprising a first conductive line serving as a select gate and being formed above the semiconductor substrate, two conductive blocks serving as floating gates and being formed at the two sides of the first conductive line and insulated from the first conductive line with two first dielectric spacers therebetween, a first dielectric layer formed on the two second conductive blocks, a second conductive line serving as a word line and being formed on the first dielectric layer and substantially perpendicular to the two doping regions.Type: GrantFiled: September 7, 2006Date of Patent: June 29, 2010Assignee: Skymedi CorporationInventor: Fuja Shone
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Publication number: 20100144162Abstract: A method of forming a conformal dielectric film having Si—N bonds on a semiconductor substrate by plasma enhanced chemical vapor deposition (PECVD) includes: introducing a nitrogen- and hydrogen-containing reactive gas and an additive gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the reaction space; and introducing a hydrogen-containing silicon precursor in pulses into the reaction space wherein a plasma is excited, thereby forming a conformal dielectric film having Si—N bonds on the substrate.Type: ApplicationFiled: September 3, 2009Publication date: June 10, 2010Applicant: ASM JAPAN K.K.Inventors: Woo Jin Lee, Akira Shimizu
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Publication number: 20100137626Abstract: An organic silane compound for forming a Si-containing film by plasma CVD is provided. The silane compound contains 2 or more silicon atoms bonded by an intervening straight chain or branched oxygen-containing hydrocarbon chain having 4 to 8 carbon atoms containing a bond represented by Cp—O—Cq wherein p and q independently represent number of carbon atoms with the proviso that 2?p?6 and 2?q?6 and the carbon chains do not contain an unsaturated bond which conjugates with the oxygen atom, wherein all of the 2 or more silicon atoms has 1 or more hydrogen atom or an alkoxy group having 1 to 4 carbon atoms.Type: ApplicationFiled: December 1, 2009Publication date: June 3, 2010Applicant: SHIN-ETSU CHEMICAL CO., LTD.Inventor: Yoshitaka Hamada
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Patent number: 7723241Abstract: According to the present invention, when a nitridation process by plasma generated by a microwave is applied to a substrate with an oxide film having been formed thereon to form an oxynitride film, the microwave is intermittently supplied. By the intermittent supply of the microwave, ion bombardment is reduced in accordance with a decrease in electron temperature, and a diffusion velocity of nitride species in the oxide film lowers, which as a result makes it possible to prevent nitrogen from concentrating in a substrate-side interface of an oxynitride film to increase the nitrogen concentration therein. Consequently, it is possible to improve quality of the oxynitride film, resulting in a reduced leakage current, an improved operating speed, and improved NBTI resistance.Type: GrantFiled: September 1, 2006Date of Patent: May 25, 2010Assignee: Tokyo Electron LimitedInventors: Seiji Matsuyama, Toshio Nakanishi, Shigenori Ozaki, Hikaru Adachi, Koichi Takatsuki, Yoshihiro Sato
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Patent number: 7709399Abstract: The present invention provides atomic layer deposition systems and methods that include metal compounds with at least one ?-diketiminate ligand. Such systems and methods can be useful for depositing metal-containing layers on substrates.Type: GrantFiled: July 29, 2008Date of Patent: May 4, 2010Assignee: Micron Technology, Inc.Inventor: Timothy A. Quick
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Publication number: 20100099271Abstract: A method for forming a silicon-based dielectric film on a substrate with a single deposition process operation using pulsed plasma enhanced chemical vapor deposition (PECVD) wherein the high frequency radio frequency power of the plasma is pulsed, allows enhanced control, efficiency and product quality of the PECVD process. Pulsing the high frequency RF power of the plasma reduces the deposited film thickness per unit time the high frequency RF power of the plasma is on. This yields silicon-based dielectric films that are both thin and conformal.Type: ApplicationFiled: October 17, 2008Publication date: April 22, 2010Applicant: NOVELLUS SYSTEMS, INC.Inventors: Dennis Hausmann, James S. Sims, Andrew Antonelli, Sesha Varadarajan, Bart Van Schravendijk
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Patent number: 7691696Abstract: Hemi-spherical structure and method for fabricating the same. A device includes discrete pillar regions on a substrate, and a pattern layer on the discrete support structures and the substrate. The pattern layer has hemi-spherical film regions on the discrete support structures respectively, and planarized portions on the substrate between the hemi-spherical film regions. Each of the hemi-spherical film regions in a position corresponding to each of the support structures serves as a hemi-spherical structure.Type: GrantFiled: March 13, 2008Date of Patent: April 6, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Chyi Liu, Chi-Hsin Lo
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Publication number: 20100041243Abstract: Aminosilane precursors for depositing silicon-containing films, and methods for depositing silicon-containing films from these aminosilane precursors, are described herein. In one embodiment, there is provided an aminosilane precursor for depositing silicon-containing film comprising the following formula (I): (R1R2N)nSiR34-n ??(I) wherein substituents R1 and R2 are each independently chosen from an alkyl group comprising from 1 to 20 carbon atoms and an aryl group comprising from 6 to 30 carbon atoms, at least one of substituents R1 and R2 comprises at least one electron withdrawing substituent chosen from F, Cl, Br, I, CN, NO2, PO(OR)2, OR, SO, SO2, SO2R and wherein R in the at least one electron withdrawing substituent is chosen from an alkyl group or an aryl group, R3 is chosen from H, an alkyl group, or an aryl group, and n is a number ranging from 1 to 4.Type: ApplicationFiled: August 12, 2008Publication date: February 18, 2010Applicant: AIR PRODUCTS AND CHEMICALS, INC.Inventors: Hansong Cheng, Manchao Xiao, Gauri Sankar Lal, Thomas Richard Gaffney, Chenggang Zhou, Jinping Wu
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Publication number: 20100025780Abstract: A semiconductor device of the present invention includes: a semiconductor layer; a gate insulation film provided on the semiconductor layer and including at least one of Hf and Zr; and a gate electrode provided on the gate insulation film and including a carbonitride which includes at least one of Hf and Zr.Type: ApplicationFiled: July 30, 2009Publication date: February 4, 2010Inventors: Akio KANEKO, Seiji Inumiya
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Patent number: 7645710Abstract: The present invention generally provides methods and apparatuses that are adapted to form a high quality dielectric gate layer on a substrate. Embodiments contemplate a method wherein a metal plasma treatment process is used in lieu of a standard nitridization process to form a high dielectric constant layer on a substrate. Embodiments further contemplate an apparatus adapted to “implant” metal ions of relatively low energy in order to reduce ion bombardment damage to the gate dielectric layer, such as a silicon dioxide layer and to avoid incorporation of the metal atoms into the underlying silicon. In general, the process includes the steps of forming a high-k dielectric and then terminating the surface of the deposited high-k material to form a good interface between the gate electrode and the high-k dielectric material.Type: GrantFiled: March 8, 2007Date of Patent: January 12, 2010Assignee: Applied Materials, Inc.Inventors: Christopher Sean Olsen, Thai Cheng Chua, Steven Hung, Patricia M. Liu, Tatsuya Sato, Alex M. Paterson, Valentin Todorow, John P. Holland
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Publication number: 20090305514Abstract: Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate, wherein the barrier layer comprises silicon and carbon and has a dielectric constant less than 4, depositing a dielectric initiation layer adjacent the barrier layer, and depositing a first dielectric layer adjacent the dielectric initiation layer, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less.Type: ApplicationFiled: July 21, 2009Publication date: December 10, 2009Inventors: Francimar Campana Schmitt, Li-Qun Xia, Son Van Nguyen, Shankar Venkataraman
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Publication number: 20090278224Abstract: A method for forming an amorphous silicon thin film is disclosed. In some embodiments, a method includes loading a substrate into a reaction chamber; and conducting a plurality of deposition cycles on the substrate. Each of at least two of the cycles includes: supplying a silicon precursor to the reaction chamber during a first time period; applying radio frequency power to the reaction chamber at least partly during the first time period; stopping supplying of the silicon precursor and applying of the radio frequency power during a second time period between the first time period and an immediately subsequent deposition cycle; and supplying hydrogen plasma to the reaction chamber during a third time period between the second time period and the immediately subsequent deposition cycle. The method allows formation of an amorphous silicon film having an excellent step-coverage and a low roughness at a relatively low deposition temperature.Type: ApplicationFiled: April 30, 2009Publication date: November 12, 2009Applicant: ASM GENITECH KOREA LTD.Inventors: Jong Su Kim, Hyung Sang Park, Yong Min Yoo, Hak Yong Kwon, Tae Ho Yoon
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Patent number: 7582562Abstract: An atomic layer deposition method includes providing a semiconductor substrate within a deposition chamber. A first metal halide-comprising precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. The first monolayer comprises metal and halogen of the metal halide. While flowing the first metal halide-comprising precursor gas to the substrate, H2 is flowed to the substrate within the chamber. A second precursor gas is flowed to the first monolayer effective to react with the first monolayer and form a second monolayer on the substrate. The second monolayer comprises the metal. At least some of the flowing of the first metal halide-comprising precursor gas, at least some of the flowing of the H2, and at least some of the flowing of the second precursor gas are repeated effective to form a layer of material comprising the metal on the substrate.Type: GrantFiled: October 6, 2005Date of Patent: September 1, 2009Assignee: Micron Technology, Inc.Inventor: Guy T. Blalock
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Patent number: 7582571Abstract: A substrate processing method using a substrate processing apparatus including: a process container holding a substrate to be processed therein; first gas supplying means having flow rate adjusting means for supplying a first process gas to the process container; and second gas supplying means supplying a second process gas to the process container, the substrate processing method including: a first step of controlling a flow rate of the first process gas to be a first flow rate by the flow rate adjusting means and supplying the first process gas in a first direction; a second step of discharging the first process gas from the process container; a third step of supplying the second process gas to the process container; and a fourth step of discharging the second process gas from the process container, in a repeated manner, wherein a step of stabilizing the flow rate of the process gas is set between a primary first step and a secondary first step performed subsequently to the primary first step.Type: GrantFiled: February 21, 2006Date of Patent: September 1, 2009Assignee: Tokyo Electron LimitedInventors: Tamaki Takeyama, Munehisa Futamura
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Patent number: 7572686Abstract: A process for depositing a thin film material on a substrate is disclosed, comprising simultaneously directing a series of gas flows from the output face of a delivery head of a thin film deposition system toward the surface of a substrate, and wherein the series of gas flows comprises at least a first reactive gaseous material, an inert purge gas, and a second reactive gaseous material, wherein the first reactive gaseous material is capable of reacting with a substrate surface treated with the second reactive gaseous material. A system capable of carrying out such a process is also disclosed.Type: GrantFiled: September 26, 2007Date of Patent: August 11, 2009Assignee: Eastman Kodak CompanyInventors: David H. Levy, Roger S. Kerr, Jeffrey T. Carey
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Patent number: 7569497Abstract: In a method for forming an insulating film, a film containing an organic curable material and provided on a substrate for an electronic device is irradiated with an energy plasma produced by a microwave irradiation through a planar antenna member having a plurality of slits to thereby cure the film containing the organic curable material and form the insulating film having a dielectric constant of 3 or less.Type: GrantFiled: January 25, 2005Date of Patent: August 4, 2009Assignee: Tokyo Electron LimitedInventors: Toshiaki Hongoh, Satohiko Hoshino
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Patent number: 7563718Abstract: A semiconductor substrate is loaded into a reaction chamber to form a tungsten layer. A source gas including tungsten (W) is introduced into the reaction chamber to grow a crystal nucleus of the tungsten on the semiconductor substrate. A reduction gas containing boron (B) is introduced into the reaction chamber to form a tungsten layer on the semiconductor substrate by actions of the source gas and the reduction gas. A hydrogen (H2) gas is introduced into the reaction chamber to remove the boron (B) remaining in the tungsten layer.Type: GrantFiled: December 29, 2006Date of Patent: July 21, 2009Assignee: Hynix Semiconductor Inc.Inventor: Choon Hwan Kim
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Publication number: 20090181550Abstract: A film formation process is performed to form a silicon nitride film on a target substrate within a process field configured to be selectively supplied with a first process gas containing a silane family gas and a second process gas containing a nitriding gas. The method is preset to compose the film formation process of a main stage with an auxiliary stage set at one or both of beginning and ending of the film formation process. The main stage includes an excitation period of supplying the second process gas to the process field while exciting the second process gas by an exciting mechanism. The auxiliary stage includes no excitation period of supplying the second process gas to the process field while exciting the second process gas by the exciting mechanism.Type: ApplicationFiled: January 6, 2009Publication date: July 16, 2009Inventors: Kazuhide Hasebe, Nobutake Nodera, Eun-jo Lee
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Patent number: 7541626Abstract: A transparent thin film transistor device includes a transparent substrate, and a high dielectric constant insulator layer disposed over the transparent substrate at a defined temperature. A transparent semiconductor layer is disposed over the insulator layer.Type: GrantFiled: March 28, 2006Date of Patent: June 2, 2009Assignee: Massachusetts Institute of TechnologyInventors: Il-Doo Kim, Harry L. Tuller
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Patent number: 7538003Abstract: A method for fabricating a metal oxide semiconductor (MOS) transistor comprises forming a source region of a first conductivity type and a drain region of the first conductivity type, which are separated from each other by a channel region, in upper regions of a semiconductor substrate, forming a gate stack on the channel region, and feeding hydrogen into junctions of the source and drain regions to neutralize dopants of the first conductivity type present within particular portions of the junctions.Type: GrantFiled: December 28, 2006Date of Patent: May 26, 2009Assignee: Hynix Semiconductor Inc.Inventors: Kyoung Bong Rouh, Min Yong Lee, Yong Soo Joung
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Publication number: 20090111284Abstract: Embodiments of the invention generally provide a method for depositing silicon-containing films. In one embodiment, a method for depositing silicon-containing material film on a substrate includes heating a substrate disposed in a processing chamber to a temperature less than about 550 degrees Celsius; flowing a nitrogen and carbon containing chemical comprising (H3C)—N?N—H into the processing chamber; flowing a silicon-containing source chemical with silicon-nitrogen bonds into the processing chamber; and depositing a silicon and nitrogen containing film on the substrate.Type: ApplicationFiled: January 5, 2009Publication date: April 30, 2009Inventors: Yaxin Wang, Yuji Maeda, Thomas C. Mele, Sean M. Seutter, Sanjeev Tandon, R. Suryanarayanan Iyer
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Patent number: 7524741Abstract: A method of forming a low temperature-grown buffer layer having the steps of: placing a Ga2O3 substrate in a MOCVD apparatus; providing a H2 atmosphere in the MOCVD apparatus and setting a buffer layer growth condition having an atmosphere temperature of 350° C. to 550° C.; and supplying a source gas having two or more of TMG, TMA and NH3 onto the Ga2O3 substrate in the buffer layer growth condition to form the low temperature-grown buffer layer on the Ga2O3 substrate.Type: GrantFiled: March 31, 2006Date of Patent: April 28, 2009Assignees: Toyoda Gosei Co., Ltd., Koha Co., Ltd.Inventors: Yasuhisa Ushida, Daisuke Shinoda, Daisuke Yamazaki, Koji Hirata, Yuhei Ikemoto, Naoki Shibata, Kazuo Aoki, Encarnacion Antonia Garcia Villora, Kiyoshi Shimamura
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Patent number: 7507678Abstract: Uniform oxynitride and nitride films can be formed by low-temperature and high-speed nitriding reaction not dependent on the nitriding time or nitriding temperature. A solid dielectric is provided on at least one of opposed surfaces of a pair of electrodes opposed to each other under a pressure of 300 (Torr) or higher, a nitrogen gas containing an oxide equal to or lower than 0.2% is introduced into a space between the pair of opposed electrodes, an electric field is applied to the nitrogen gas, and the resulting N2 (2nd p.s.) or N2 (H.I.R) active species is brought into contact with an object to be processed to form an oxynitride film/nitride film on a surface of the object to be processed.Type: GrantFiled: March 25, 2005Date of Patent: March 24, 2009Assignee: Sekesui Chemical Co., Ltd.Inventors: Norifumi Fujimura, Ryoma Hayakawa, Hiroya Kitahata, Tsuyoshi Uehara, Takuya Yara
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Publication number: 20090068853Abstract: Methods are disclosed of depositing a silicon oxide film on a substrate disposed in a substrate processing chamber. The substrate has a gap formed between adjacent raised surfaces. A first portion of the silicon oxide film is deposited over the substrate and within the gap using a high-density plasma process. Thereafter, a portion of the deposited first portion of the silicon oxide film is etched back. This includes flowing a halogen precursor through a first conduit from a halogen-precursor source to the substrate processing chamber, forming a high-density plasma from the halogen precursor, and terminating flowing the halogen precursor after the portion has been etched back. Thereafter, a halogen scavenger is flowed to the substrate processing chamber to react with residual halogen in the substrate processing chamber. Thereafter, a second portion of the silicon oxide film is deposited over the first portion of the silicon oxide film and within the gap using a high-density plasma process.Type: ApplicationFiled: September 4, 2008Publication date: March 12, 2009Applicant: Applied Materials, Inc.Inventors: Anchuan Wang, Young S. Lee, Manoj Vellaikal, Jason Thomas Bloking, Jin Ho Jeon, Hemant P. Mungekar
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Patent number: 7494937Abstract: A method for forming a strained metal silicon nitride film and a semiconductor device containing the strained metal silicon nitride film. The method includes exposing a substrate to a gas containing a metal precursor, exposing a substrate to a gas containing a silicon precursor, exposing the substrate to a gas containing a first nitrogen precursor configured to react with the metal precursor or the silicon precursor with a first reactivity characteristic, and exposing the substrate to a gas pulse containing a second nitrogen precursor configured to react with the metal precursor or the silicon precursor with a second reactivity characteristic different than the first reactivity characteristic such that a property of the metal silicon nitride film formed on the substrate changes to provide a strained metal silicon nitride film.Type: GrantFiled: March 30, 2007Date of Patent: February 24, 2009Assignee: Tokyo Electron LimitedInventor: Robert D. Clark
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Patent number: 7491656Abstract: A silicon oxide film (1701) serving as a gate insulating film of a semiconductor device contains Kr. Therefore, the stress in the silicon oxide film (1701) and the stress at the interface between silicon and the silicon oxide film are relaxed, and the silicon oxide film has a high quality even though it was formed at a low temperature. The uniformity of thickness of the silicon oxide film (1701) on the silicon of the side wall of a groove (recess) in the element isolating region is 30% or less. Consequently, the silicon oxide film (1701) has its characteristics and reliability superior to those of a silicon thermal oxide film, and the element isolating region can be made small, thereby realizing a high-performance transistor integrated circuit preferably adaptable to an SOI transistor and a TFT.Type: GrantFiled: September 20, 2004Date of Patent: February 17, 2009Assignee: Foundation for Advancement of International ScienceInventor: Tadahiro Ohmi
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Patent number: 7476609Abstract: A method for forming, by dry etch, an opening of a given shape in a silica glass layer, the layer having a doping profile similar to the shape and the etch plasma being a non-carbonated fluorinated plasma causing a non-directional etching.Type: GrantFiled: October 27, 2006Date of Patent: January 13, 2009Assignee: STMicroelectronics S.A.Inventor: Fabienne Judong
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Patent number: 7476612Abstract: In embodiments, a method for manufacturing a semiconductor device may include forming a diffusion preventing layer on a semiconductor substrate having a conductive layer, forming an intermetallic insulating layer on the diffusion preventing layer, forming a trench photo resist layer formed above the intermetallic insulating layer of a first photo resist material, forming a via hole photo resist layer of a second photo resist material at an upper portion and a sidewall in a contact hole of the trench photo resist layer, etching the intermetallic insulating layer and the diffusion preventing layer using the via hole photo resist layer and the trench photo resist layer to substantially simultaneously form a via hole and a trench, and filling the via hole and the trench with a metal thin film to form a metal line.Type: GrantFiled: November 28, 2006Date of Patent: January 13, 2009Inventor: Su Kon Kim
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Patent number: 7465679Abstract: A silicon oxide film is formed to cover an island non-monocrystalline silicon region by plasma CVD using an organic silane having ethoxy groups (e.g., TEOS) and oxygen as raw materials, while hydrogen chloride or a chlorine-containing hydrocarbon (e.g., trichloroethylene) of a fluorine-containing gas is added to the plasma CVD atmosphere, preferably in an amount of from 0.01 to 1 mol % of the atmosphere so as to reduce the alkali elements from the silicon oxide film formed and to improve the reliability of the film. Prior to forming the silicon oxide film, the silicon region may be treated in a plasma atmosphere containing oxygen and hydrogen chloride or a chlorine-containing hydrocarbon. The silicon oxide film is obtained at low temperatures and this has high reliability usable as a gate-insulating film in a semiconductor device.Type: GrantFiled: December 20, 1999Date of Patent: December 16, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Takeshi Fukada, Mitsunori Sakama, Yukiko Uehara, Hiroshi Uehara