On Silicon Body (epo) Patents (Class 257/E21.279)
  • Patent number: 11393724
    Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chieh Wu, Pang-Chi Wu, Kuo-Yi Chao, Mei-Yun Wang, Hsien-Huang Liao, Tung-Heng Hsieh, Bao-Ru Young
  • Patent number: 11251039
    Abstract: A film where a first layer and a second layer are laminated is formed on a substrate by performing: forming the first layer by performing a first cycle a predetermined number of times, the first cycle including non-simultaneously performing: supplying a source to the substrate, and supplying a reactant to the substrate, under a first temperature at which neither the source nor the reactant is thermally decomposed when the source and the reactant are present alone, respectively; and forming the second layer by performing a second cycle a predetermined number of times, the second cycle including non-simultaneously performing: supplying the source to the substrate, and supplying the reactant to the substrate, under a second temperature at which neither the source nor the reactant is thermally decomposed when the source and the reactant are present alone, respectively, the second temperature being different from the first temperature.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: February 15, 2022
    Inventors: Tsukasa Kamakura, Takaaki Noda, Yoshiro Hirose
  • Patent number: 10840118
    Abstract: In accordance with an exemplary embodiment, a substrate processing apparatus includes: a tube assembly having an inner space in which substrates are processed and assembled by laminating a plurality of laminates, a substrate holder configured to support the plurality of substrates in a multistage manner in the inner space of the tube assembly, a gas supply unit installed on one side of the tube assembly to supply a process gas to each of the plurality of substrates in the inner space; and an exhaust unit connected to the tube assembly to exhaust the process gas supplied into the inner space, the substrate processing apparatus that induces a laminar flow to supply a uniform amount of process gas to a top surface of the substrate.
    Type: Grant
    Filed: September 5, 2016
    Date of Patent: November 17, 2020
    Inventors: Cha Young Yoo, Sung Tae Je, Kyu Jin Choi, Ja Dae Ku, Jun Kim, Bong Ju Jung, Kyung Seok Park, Yong Ki Kim, Jae Woo Kim
  • Patent number: 10651083
    Abstract: A graded cap is formed upon an interconnect, such as a back end of line wire. The graded cap includes a microstructure that uniformly changes from a metal nearest the interconnect to a metal nitride most distal from the interconnect. The graded cap is formed by nitriding a metal cap that is formed upon the interconnect. During nitriding an exposed one or more perimeter portions of the metal cap become a metal nitride with a larger amount or concentration of Nitrogen while one or more inner portions of the metal cap nearest the interconnect may be maintained as the metal or become the metal nitride with a fewer amount or concentration of Nitrogen. The resulting graded cap includes a gradually or uniformly changing microstructure between the one or more inner portions and the one or more perimeter portions.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: May 12, 2020
    Assignee: International Business Machines Corporation
    Inventors: Andrew Tae Kim, Baozhen Li, Ernest Y. Wu, Chih-Chao Yang
  • Patent number: 10604845
    Abstract: A substrate processing apparatus includes: a mounting stand provided with a substrate mounting region in which a workpiece substrate is mounted; a process vessel for defining a process chamber including a first region and a second region through which the substrate mounting region passes in order; a precursor gas supply unit for supplying a precursor gas to the first region; a process gas supply unit for supplying a first gas or a second gas differing from the first gas to the second region; at least one plasma generating unit for generating plasma of the first gas or the second gas in the second region; and a control unit for executing a repetition control of repeating a first operation for supplying the first gas to the second region for a first time and a second operation for supplying the second gas to the second region for a second time.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: March 31, 2020
    Inventor: Takayuki Karakawa
  • Patent number: 10526483
    Abstract: A poly(ester-carbonate) copolymer comprises carbonate units of the formula (I); and ester units of the formula (II) wherein: T is a C2-20 alkylene, a C6-20 cycloalkylene, or a C6-20 arylene; and R1 and J are each independently a bisphenol A divalent group and a phthalimidine divalent group, provided that the phthalimidine divalent group is present in an amount of 40 to 50 mol % based on the total moles of the bisphenol A divalent groups and the C 1/2 divalent group, and the ester units are present in an amount of 40 to 60 mol % based on the sum of the moles of the carbonate units and the ester units; and wherein the poly(ester-carbonate) copolymer has a weight average molecular weight of 18,000 to 24,000 Daltons; and the composition has a Tg of 210 to 235° C. and a melt viscosity of less than 1050 Pa-s at 644 sec?1 and 350° C.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: January 7, 2020
    Inventors: Tony Farrell, Paul Dean Sybert, James Alan Mahood
  • Patent number: 10529584
    Abstract: Embodiments of the invention provide a method for in-situ selective deposition and etching for advanced patterning applications. According to one embodiment the method includes providing in a process chamber a substrate having a metal-containing layer thereon, and exposing the substrate to a gas pulse sequence to etch the metal-containing layer in the absence of a plasma, where the gas pulse sequence includes, in any order, exposing the substrate to a first reactant gas containing a halogen-containing gas, and exposing the substrate to a second reactant gas containing an aluminum alkyl. According to another embodiment, the substrate has an exposed first material layer and an exposed second material layer, and the exposing to the gas pulse sequence selectively deposits an additional material layer on the exposed first material layer but not on the exposed second material layer.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: January 7, 2020
    Assignee: Tokyo Electron Limited
    Inventor: Kandabara N. Tapily
  • Patent number: 10483282
    Abstract: Embodiments of the present disclosure generally relate to an improved method for forming a dielectric film stack used for inter-level dielectric (ILD) layers in a 3D NAND structure. In one embodiment, the method comprises providing a substrate having a gate stack deposited thereon, forming on exposed surfaces of the gate stack a first oxide layer using a first RF power and a first process gas comprising a TEOS gas and a first oxygen-containing gas, and forming over the first oxide layer a second oxide layer using a second RF power and a second process gas comprising a silane gas and a second oxygen-containing gas.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: November 19, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Michael Wenyoung Tsiang, Praket P. Jha, Xinhai Han, Bok Hoen Kim, Sang Hyuk Kim, Myung Hun Ju, Hyung Jin Park, Ryeun Kwan Kim, Jin Chul Son, Saiprasanna Gnanavelu, Mayur G. Kulkarni, Sanjeev Baluja, Majid K. Shahreza, Jason K. Foster
  • Patent number: 10453749
    Abstract: A substrate processing method for forming a self-aligned contact using selective SiO2 deposition is described in various embodiments. The method includes providing a planarized substrate containing a dielectric layer surface and a metal-containing surface, coating the dielectric layer surface with a metal-containing catalyst layer, and exposing the planarized substrate to a process gas containing a silanol gas for a time period that selectively deposits a SiO2 layer on the metal-containing catalyst layer on the dielectric layer surface. According to one embodiment, the method further includes depositing an etch stop layer on the SiO2 layer and on the metal-containing surfaces, depositing an interlayer dielectric layer on the planarized substrate, etching a recessed feature in the interlayer dielectric layer and stopping on the etch stop layer above the metal-containing surface, and filling the recessed feature with a metal.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: October 22, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Kandabara N. Tapily, Sangcheol Han, Soo Doo Chae
  • Patent number: 10422034
    Abstract: Disclosed herein are containing silicon-based films and compositions and methods for forming the same. The silicon-based films contain <50 atomic % of silicon. In one aspect, the silicon-based films have a composition SixCyNz wherein x is about 0 to about 55, y is about 35 to about 100, and z is about 0 to about 50 atomic weight (wt.) percent (%) as measured by XPS. In another aspect, the silicon-based films were deposited using at least one organosilicon precursor comprising two silicon atoms, at least one Si-Me group, and an ethylene or propylene linkage between the silicon atoms such as 1,4-disilapentane.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: September 24, 2019
    Inventors: Xinjian Lei, Anupama Mallikarjunan, Matthew R. MacDonald, Manchao Xiao
  • Patent number: 10276505
    Abstract: An integrated circuit (IC) device includes a lower wiring structure including a lower metal film. The lower wiring structure penetrates at least a portion of a first insulating film disposed over a substrate. The IC device further includes a capping layer covering a top surface of the lower metal film, a second insulating film covering the capping layer, an upper wiring structure penetrating the second insulating film and the capping layer, and electrically connected to the lower metal film, and an air gap disposed between the lower metal film and the second insulating film. The air gap has a width defined by a distance between the capping layer and the upper wiring structure.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: April 30, 2019
    Inventors: Young-Bae Kim, Sang-Hoon Ahn, Eui-Bok Lee, Su-Hyun Bark, Hyeok-Sang Oh, Woo-Jin Lee, Hoon-Seok Seo, Sung-Jin Kang
  • Patent number: 10256396
    Abstract: Provided are a magnetic sensor and a method of fabricating the same. The magnetic sensor includes: hall elements disposed in a substrate, a protection layer disposed on the substrate, a seed layer disposed on the protection layer, and an integrated magnetic concentrator (IMC) formed on the seed layer, the seed layer and the IMC each having an uneven surface.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: April 9, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Kwan Soo Kim, Dong Joon Kim, Seung Han Ryu, Hee Baeg An, Jong Yeul Jeong, Kyung Soo Kim, Kang Sup Shin
  • Patent number: 10229876
    Abstract: A wiring structure includes a substrate, a lower insulation layer on the substrate, a lower wiring in the lower insulation layer, a first etch-stop layer covering the lower wiring and including a metallic dielectric material, a second etch-stop layer on the first etch-stop layer and the lower insulation layer, an insulating interlayer on the second etch-stop layer, and a conductive pattern extending through the insulating interlayer, the second etch-stop layer and the first etch-stop layer and electrically connected to the lower wiring.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: March 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-Jung Kim, Young-Bae Kim, Jong-Sam Kim, Jin-Hyeung Park, Jeong-Hoon Ahn, Hyeok-Sang Oh, Kyoung-Woo Lee, Hyo-Seon Lee, Suk-Hee Jang
  • Patent number: 10204797
    Abstract: The disclosed methods may include depositing an amorphous carbon layer, a SiCN layer, and a TEOS layer; planarizing the semiconductor structure; performing a non-selective etch to remove the SiCN layer, the TEOS layer, and a portion of the amorphous carbon layer; and performing a selective etch of the amorphous carbon layer. The methods may reduce step height differences between first and second regions of the semiconductor structure.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: February 12, 2019
    Inventors: Jinsheng Gao, Daniel Jaeger, Michael Aquilino, Patrick Carpenter, Junsic Hong, Jessica Dechene, Haigou Huang
  • Patent number: 10174424
    Abstract: Methods for producing coatings on substrates are provided. These methods comprise the steps of introducing the substrate in a photo-initiated chemical vapor deposition reactor, introducing a gas precursor in the reactor, irradiating said gas precursor with UV radiation at a given wavelength, thereby at least partly photodissociating the gas precursor, until the coating is formed. In one method, the gas precursor is a mixture comprising carbon monoxide and hydrogen. In another method, the pressure in the react or is between about 0.75 and 1.25 atm and the gas precursor has an absorption cross section of about 5×10?16 cm2/molecule or less at said given wavelength. In another aspect, the substrate is ash.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: January 8, 2019
    Assignee: Polyvalor, Limited Partnership
    Inventors: Jason Robert Tavares, Christopher Alex Dorval Dion
  • Patent number: 10037884
    Abstract: Methods and apparatuses for depositing films in high aspect ratio features and trenches on substrates using atomic layer deposition and deposition of a sacrificial layer during atomic layer deposition are provided. Sacrificial layers are materials deposited at or near the top of features and trenches prior to exposing the substrate to a deposition precursor such that adsorbed precursor on the sacrificial layer is removed in an etching operation for etching the sacrificial layer prior to exposing the substrate to a second reactant and a plasma to form a film.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: July 31, 2018
    Assignee: Lam Research Corporation
    Inventors: Fung Suong Ou, Purushottam Kumar, Adrien LaVoie, Ishtak Karim, Jun Qian
  • Patent number: 9997351
    Abstract: A method may include generating a plasma in a plasma chamber and directing the ions comprising at least one of a condensing species and inert gas species from the plasma to a cavity within a substrate at a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate. The method may further include; depositing a fill material within the cavity using the condensing species, the depositing taking place concurrently with the directing the ions, wherein the fill material accumulates on a lower surface of the cavity at a first rate, and wherein the fill material accumulates on an upper portion of a sidewall of the cavity at a second rate less than the first rate.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: June 12, 2018
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Tsung-Liang Chen, John Hautala, Shurong Liang
  • Patent number: 9960144
    Abstract: A heating method includes an oxide film forming step and a heating step. The thickness of an oxide film is set in a first range that includes a first maximal thickness and a second maximal thickness and that is smaller than a second minimal thickness in the relationship with the laser absorption having a periodic profile. The first maximal thickness corresponds to a first maximal value a of the laser absorption. The second maximal thickness corresponds to a second maximal value of the laser absorption. The second minimal thickness corresponds to a second minimal value of the laser absorption, namely the minimal value of the laser absorption that appears between the second maximal value and a third maximal value, or the maximal value of the laser absorption that appears subsequent to the second maximal value.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: May 1, 2018
    Inventors: Takaya Nagahama, Koichi Shiiba, Yoshinori Imoto
  • Patent number: 9950317
    Abstract: Disclosed are a large-scale composite synthesis system, a reactor therefor, and a synthesis method using the same, wherein two or more different samples are vaporized in respective vaporizers, and are then fed into a reactor that has a relatively large transverse cross-sectional diameter compared to the connector for transporting the samples in a gas phase and is maintained at a temperature lower than that of the connector, thus producing a powder composite, the composite being synthesized while being electrostatically attached to an adherend surface.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: April 24, 2018
    Inventors: Hee-Yeon Kim, Guk-Hyeon Kwon
  • Patent number: 9920427
    Abstract: A semiconductor manufacturing apparatus according to an embodiment comprises a reaction chamber in which a semiconductor substrate is capable of being accommodated when a deposited film is to be formed on a surface of the semiconductor substrate. A first supplier supplies a source gas to a first area in the reaction chamber. A second supplier supplies an oxidation gas to a second area in the reaction chamber. A third supplier supplies a hydrogen gas to a third area between the first area and the second area in the reaction chamber. A stage moves the semiconductor substrate to any one of the first to third areas.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: March 20, 2018
    Inventors: Motoki Fujii, Fumiki Aiso, Hajime Nagano, Ryota Fujitsuka
  • Patent number: 9865738
    Abstract: A method of fabricating a fin field effect transistor (FinFET) is provided as follows. A fin structure is formed on a substrate. A gate pattern and a source/drain (S/D) electrode are formed on the fin structure. The gate pattern and the S/D electrode are spaced apart from each other. A blocking layer is on the fin structure to cover the gate pattern and the S/D electrode. A sacrificial pattern is formed on the blocking layer and between the gate pattern and S/D electrode. The sacrificial pattern has a first thickness and a first width. A capping layer is formed on the sacrificial layer. An air gap is formed by removing the sacrificial layer through the capping layer. The air gap is formed between the gate pattern and the S/D electrode and has the first thickness and the first width.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: January 9, 2018
    Inventor: Jin Gyun Kim
  • Patent number: 9721830
    Abstract: A method of manufacturing a semiconductor device comprising the steps of: forming a trench at an upper portion of a semiconductor substrate forming a preliminary filling insulation layer by coating a siloxane composition on the semiconductor substrate to fill the trench performing a low temperature curing process at a temperature in a range from about 50° C. to about 150° C. such that the preliminary filling insulation layer is transformed into a filling insulation layer including polysiloxane and forming an isolation layer by planarizing the filling insulation layer.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: August 1, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok-Han Park
  • Patent number: 9679770
    Abstract: A semiconductor device manufacturing method of the present invention includes forming a base film having a water-repellent surface on a substrate; forming a photosensitive film having a water-repellent surface on the base film; developing the photosensitive film to expose the base film, thereby forming a photosensitive film pattern; supplying a first spacer material on the photosensitive film and on the exposed base film; and removing at least a part of the first spacer material formed on a top surface of the photosensitive film and a top surface of the base film.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: June 13, 2017
    Inventor: Hidetami Yaegashi
  • Patent number: 9673144
    Abstract: A semiconductor device has a resistor area and wiring area selectively disposed on a semiconductor substrate. In this semiconductor device, a second interlayer insulating film is formed above the semiconductor substrate, and a thin-film resistor is disposed on the second interlayer insulating film in the resistor area. Vias that contact the thin-film resistor from below are formed in the second interlayer insulating film. A wiring line is disposed on the second interlayer insulating film in the wiring area. A dummy wiring line that covers the thin-film resistor from above is disposed in a third wiring layer that is in the same layer as the wiring line, and an insulating film is interposed between the thin-film resistor and the dummy wiring line.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: June 6, 2017
    Assignee: ROHM CO., LTD.
    Inventors: Isamu Nishimura, Michihiko Mifuji, Kazumasa Nishio
  • Patent number: 9618493
    Abstract: A substrate processing apparatus is provided that includes an ozonizer for generating ozone gas and an ozone sensor for detecting an ozone gas concentration. The substrate processing apparatus processes a substrate by using the ozone gas supplied from the ozonizer. The substrate processing apparatus includes a monitor unit for monitoring the ozone gas concentration detected by the ozone sensor and a control unit for detecting an abnormality of the ozone gas concentration based on the monitored ozone gas concentration and the monitored discharge power.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: April 11, 2017
    Assignee: Tokyo Electron Limited
    Inventor: Masaki Kondo
  • Patent number: 9613838
    Abstract: A batch-type vertical substrate processing apparatus includes a processing chamber into which a substrate holder configured to stack and hold a plurality of target substrates in a height direction is inserted; and a plurality of flanges formed to protrude from an inner wall of the processing chamber toward an internal space of the processing chamber along a planar direction and configured to divide the interior of the processing chamber into a plurality of processing subspaces along the height direction, wherein the flanges include insertion holes through which the substrate holder is inserted, and diameters of the insertion holes are small at an upper side of the processing chamber and become gradually larger toward a lower side of the processing chamber.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: April 4, 2017
    Inventors: Mitsuhiro Okada, Kazuhide Hasebe
  • Patent number: 9029228
    Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate. The layer of graphene may be formed in direct contact with the surface of the substrate, or an intervening layer of a material may be formed between the substrate surface and the graphene layer.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: May 12, 2015
    Assignees: SunEdision Semiconductor Limited (UEN201334164H), Kansas State University Research Foundation
    Inventors: Michael R. Seacrist, Vikas Berry, Phong Tuan Nguyen
  • Patent number: 9012286
    Abstract: Disclosed herein are various methods of forming FinFET semiconductor devices so as to tune the threshold voltage of such devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate to define at least one fin (or fins) for the device, prior to forming a gate structure above the fin (or fins), performing a first epitaxial growth process to grow a first semiconductor material on exposed portions of the fin (or fins) and forming the gate structure above the first semiconductor material on the fin (or fins).
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: April 21, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Min-Hwa Chi
  • Patent number: 8956937
    Abstract: The present invention discloses to a method of depositing the metal barrier layer comprising silicon dioxide. It is applied in the transistor device comprising a silicon substrate, a gate and a gate side wall. The method comprises the following steps: ions are implanted into the silicon substrate to form an active region in the said silicon substrate; a first dense silicon dioxide film is deposited; a second normal silicon dioxide film is deposited; the said transistor device is high temperature annealed. The present invention ensures that the implanted ion is not separated out of the substrate during the annealing. And it prevents the warping and fragment of the silicon surface.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: February 17, 2015
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: GuoFang Xuan, Fei Luo
  • Patent number: 8884310
    Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a semiconductor substrate. The method includes forming a carbon-containing layer on a front surface of a semiconductor substrate and depositing a metal film on the carbon layer. A thermal cycle degrades the carbon-containing layer, which forms graphene directly upon the semiconductor substrate upon cooling. In some embodiments, the carbon source is a carbon-containing gas, and the thermal cycle causes diffusion of carbon atoms into the metal film, which, upon cooling, segregate and precipitate into a layer of graphene directly on the semiconductor substrate.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: November 11, 2014
    Assignees: SunEdison Semiconductor Limited (UEN201334164H), KSU Research Foundation
    Inventors: Michael R. Seacrist, Vikas Berry
  • Patent number: 8790982
    Abstract: Oxidation methods and resulting structures including providing an oxide layer on a substrate and then reoxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions, in a substrate. The oxide layer may overlie the substrate and is proximate a gate structure on the substrate. The at least one oxidant may be oxygen, water, ozone, or hydrogen peroxide, or a mixture thereof. These oxidation methods provide a low-temperature oxidation process, less oxidation of the sidewalls of conductive layers in the gate structure, and less current leakage to the substrate from the gate structure.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: July 29, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Li Li, Pai-Hung Pan
  • Patent number: 8723340
    Abstract: The present invention relates to a process for the production of solar cells comprising a selective emitter using an improved etching-paste composition which has significantly improved selectivity for silicon layers.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: May 13, 2014
    Assignee: Merck Patent GmbH
    Inventors: Werner Stockum, Oliver Doll, Ingo Koehler
  • Patent number: 8609516
    Abstract: An atmospheric pressure chemical vapor deposition method for producing an N-type semiconductive metal sulfide thin film on a heated substrate includes converting an indium-containing precursor to at least one of a liquid phase and a gaseous phase. The indium-containing precursor is mixed with an inert carrier gas stream and hydrogen sulfide in a mixing zone so as to form a mixed precursor. A substrate is heated to a temperature in a range of 100° C. to 275° C. and the mixed precursor is directed onto the substrate. The hydrogen sulfide is supplied at a rate so as to obtain an absolute concentration of hydrogen sulfide in the mixing zone of no more than 1% by volume. The In-concentration of the indium containing precursor is selected so as to produce a compact indium sulfide film.
    Type: Grant
    Filed: March 14, 2009
    Date of Patent: December 17, 2013
    Assignee: Helmholtz-Zentrum Berlin fuer Materialien und Energie GmbH
    Inventors: Nicholas Allsop, Christian-Herbert Fischer, Sophie Gledhill, Martha Christina Lux-Steiner
  • Publication number: 20130277723
    Abstract: Some embodiments include methods of forming silicon dioxide in which silicon dioxide is formed across silicon utilizing a first treatment temperature of no greater than about 1000° C., and in which an interface between the silicon dioxide and the silicon is annealed utilizing a second treatment temperature which is at least about 1050° C. Some embodiments include methods of forming transistors in which a trench is formed to extend into monocrystalline silicon. Silicon dioxide is formed along multiple crystallographic planes along an interior of the trench utilizing a first treatment temperature of no greater than about 1000° C., and an interface between the silicon dioxide and the monocrystalline silicon is annealed utilizing a second treatment temperature which is at least about 1050° C. A transistor gate is formed within the trench, and a pair of source/drain regions is formed within the monocrystalline silicon adjacent the transistor gate. Some embodiments include DRAM cells.
    Type: Application
    Filed: April 19, 2012
    Publication date: October 24, 2013
    Inventors: Shivani Srivastava, Kunal Shrotri, Fawad Ahmed
  • Patent number: 8492281
    Abstract: A liquid composition used to carry out crystal anisotropic etching of a silicon substrate provided with an etching mask formed of a silicon oxide film with the silicon oxide film used as a mask includes cesium hydroxide, an alkaline organic compound, and water.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: July 23, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroyuki Abo, Taichi Yonemoto, Shuji Koyama, Kenta Furusawa, Keisuke Kishimoto
  • Patent number: 8338273
    Abstract: An epitaxy procedure for growing extremely low defect density non-polar and semi-polar III-nitride layers over a base layer, and the resulting structures, is generally described. In particular, a pulsed selective area lateral overgrowth of a group III nitride layer can be achieved on a non-polar and semi-polar base layer. By utilizing the novel P-MOCVD or PALE and lateral over growth over selected area, very high lateral growth conditions can be achieved at relatively lower growth temperature which does not affect the III-N surfaces.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: December 25, 2012
    Assignee: University of South Carolina
    Inventors: M. Asif Khan, Vinod Adivarahan
  • Publication number: 20120252224
    Abstract: A method of depositing a silicon oxide film and a silicon nitride film includes depositing the silicon oxide film and the silicon nitride film on a substrate, and a gas for forming the silicon nitride film further includes boron.
    Type: Application
    Filed: March 28, 2012
    Publication date: October 4, 2012
    Inventors: Atsushi ENDO, Masaki KUROKAWA, Hiroki IRIUDA
  • Patent number: 8232176
    Abstract: Methods to reduce film cracking in a dielectric layer are described. The methods may include the steps of depositing a first dielectric film on a substrate and removing a top portion of the first dielectric film by performing an etch on the film. The methods may also include depositing a second dielectric film over the etched first film, and removing a top portion of the second dielectric film. In addition, the methods may include annealing the first and second dielectric films to form the dielectric layer, where the removal of the top portions from the first and the second dielectric films reduces a stress level in the dielectric layer.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: July 31, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Dmitry Lubomirsky, Srinivas D. Nemani, Ellie Yieh
  • Patent number: 8202806
    Abstract: A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region. A barrier layer and a dielectric layer are deposited over the nonconducting region and over the active regions. Heat is applied to the integrated circuit causing the barrier layer to anneal.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: June 19, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Randhir P.S. Thakur, Ravi Iyer, Howard Rhodes
  • Patent number: 8193065
    Abstract: A method forms a structure has a substrate having at least one semiconductor channel region, a gate dielectric on the upper surface of the substrate over the semiconductor channel region, and a gate conductor on the gate dielectric. Asymmetric sidewall spacers are located on the sidewalls of the gate conductor and asymmetric source and drain regions are located within the substrate adjacent the semiconductor channel region. One source/drain region is positioned closer to the midpoint of the gate conductor than is the other source/drain region. The source and drain regions comprise a material that induces physical stress upon the semiconductor channel region.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: June 5, 2012
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey B. Johnson, Viorel C. Ontalus
  • Patent number: 8101529
    Abstract: A process for producing a carbon nanotube resistor that is capable of providing a highly reliable resistor or fuse. The process comprises the step of introducing a carbon nanotube in a volatile solvent to a first concentration and conducting ultrasonic treatment thereof to thereby obtain an initial solution; the dilution step of stepwise diluting the initial solution with a volatile solvent under ultrasonication so as to adjust the same to a second concentration, thereby obtaining a coating solution; and the step of applying the coating solution between a first electrode and a second electrode, wherein the first concentration is 1(E10?4 g/ml or higher and the second concentration lower than 1(E10?5 g/ml.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: January 24, 2012
    Assignee: NEC Corporation
    Inventor: Kaoru Narita
  • Patent number: 8021991
    Abstract: Oxide films are deposited under conditions generating a silicon-rich oxide in which silicon nanoclusters form either during deposition or during subsequent annealing. Such deposition conditions include those producing films with optical indices (n) greater than 1.46. The method of the present invention reduces the TID radiation-induced shifts for the oxides.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: September 20, 2011
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Harold L Hughes, Bernard J Mrstik, Reed K Lawrence, Patrick J McMarr
  • Patent number: 7964517
    Abstract: According to various embodiments, the present teachings include methods for reducing first wafer defects in a high-density plasma chemical vapor deposition process. In an exemplary embodiment, the method can include running a deposition chamber for deposition of film on a first batch of silicon wafers and then cleaning interior surfaces of the deposition chamber. The method can further include inserting a protective electrostatic chuck cover (PEC) wafer on an electrostatic chuck in the deposition chamber and applying power to bias the PEC wafer while simultaneously precoating the deposition chamber with an oxide. The exemplary method can also include re-starting the deposition chamber for deposition of film on a second batch of silicon wafers.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: June 21, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Rajneesh Jaiswal
  • Patent number: 7935643
    Abstract: The formation of a gap-filling silicon oxide layer with reduced tendency towards cracking is described. The deposition involves the formation of a flowable silicon-containing layer which facilitates the filling of trenches. Subsequent processing at high substrate temperature causes less cracking in the dielectric film than flowable films formed in accordance with methods in the prior art. A compressive liner layer deposited prior to the formation of the gap-filling silicon oxide layer is described and reduces the tendency for the subsequently deposited film to crack. A compressive capping layer deposited after a flowable silicon-containing layer has also been determined to reduce cracking. Compressive liner layers and compressive capping layers can be used alone or in combination to reduce and often eliminate cracking. Compressive capping layers in disclosed embodiments have additionally been determined to enable an underlying layer of silicon nitride to be transformed into a silicon oxide layer.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: May 3, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Jingmei Liang, Anjana M. Patel, Nitin K. Ingle, Shankar Venkataraman
  • Patent number: 7927976
    Abstract: Provided are reinforced composite stamps, devices and methods of making the reinforced composite stamps disclosed herein. Reinforced composite stamps of certain aspects of the present invention have a composition and architecture optimized for use in printing systems for dry transfer printing of semiconductor structures, and impart excellent control over relative spatial placement accuracy of the semiconductor structures being transferred. In some embodiments, for example, reinforced composite stamps of the present invention allow for precise and repeatable vertical motion of the patterned surface of the printing apparatus with self-leveling of the stamp to the surface of a contacted substrate. Reinforced composite stamps of certain aspect of the present invention achieve a uniform distribution of contact forces between the printing apparatus patterned surface and the top surface of a substrate being contacted by the reinforced composite stamp of the printing apparatus.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: April 19, 2011
    Assignee: Semprius, Inc.
    Inventor: Etienne Menard
  • Patent number: 7923378
    Abstract: A silicon-containing insulating film is formed on a target substrate by CVD, in a process field to be selectively supplied with a first process gas including di-iso-propylaminosilane gas and a second process gas including an oxidizing gas or nitriding gas. The film is formed by performing a plurality of times a cycle alternately including first and second steps. The first step performs supply of the first process gas, thereby forming an adsorption layer containing silicon on a surface of the target substrate. The second performs supply of the second process gas, thereby oxidizing or nitriding the adsorption layer on the surface of the target substrate. The second step includes an excitation period of supplying the second process gas to the process field while exciting the second process gas by an exciting mechanism.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: April 12, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhide Hasebe, Shigeru Nakajima, Jun Ogawa
  • Patent number: 7884022
    Abstract: Pitch multiplication is performed using a two step process to deposit spacer material on mandrels. The precursors of the first step react minimally with the mandrels, forming a barrier layer against chemical reactions for the deposition process of the second step, which uses precursors more reactive with the mandrels. Where the mandrels are formed of amorphous carbon and the spacer material is silicon oxide, the silicon oxide is first deposited by a plasma enhanced deposition process and then by a thermal chemical vapor deposition process. Oxygen gas and plasma-enhanced tetraethylorthosilicate (TEOS) are used as reactants in the plasma enhanced process, while ozone and TEOS are used as reactants in the thermal chemical vapor deposition process. The oxygen gas is less reactive with the amorphous carbon than ozone, thereby minimizing deformation of the mandrels caused by oxidation of the amorphous carbon.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: February 8, 2011
    Assignee: Round Rock Research, LLC
    Inventors: Jingyi Bai, Gurtej S Sandhu, Shuang Meng
  • Patent number: 7851385
    Abstract: The present invention generally provides apparatus and method for processing a semiconductor substrate. Particularly, embodiments of the present invention relate to a method and apparatus for forming semiconductor devices having a conformal silicon oxide layer formed at low temperature. One embodiment of the present invention provides a method for forming a semiconductor gate structure. The method comprises forming a gate stack on a semiconductor substrate, forming a conformal silicon oxide layer on the semiconductor substrate using a low temperature cyclic method, and forming a spacer layer on the conformal silicon oxide layer.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: December 14, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Matthew Spuller, Melody Agustin, Meiyee (Maggie Le) Shek, Li-Qun Xia, Reza Arghavani
  • Patent number: 7829393
    Abstract: A copper gate electrode, applied in a thin-film-transistor liquid crystal display (LCD) device, at least comprises a patterned copper layer formed on a glass substrate, and a barrier layer formed on the patterned copper layer. The barrier layer comprises at least one of nitrogen and phosphorus, or comprises an alloy formularized as M1M2R wherein M1 is cobalt (Co) or molybdenum (Mo), M2 is tungsten (W), molybdenum (Mo), rhenium (Re) or vanadium (V), and R is boron (B) or phosphorus (P).
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: November 9, 2010
    Assignee: Au Optronics Corp.
    Inventors: Yu-Wei Liu, Wen-Ching Tsai, Kuo-Yu Huang, Hui-Fen Lin
  • Patent number: 7829924
    Abstract: A trench isolation surrounding the lateral sides of an active region of a P-channel MIS transistor PTr and a trench isolation surrounding the lateral sides of an active region of an N-channel MIS transistor NTr have different film qualities.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: November 9, 2010
    Assignee: Panasonic Corporation
    Inventor: Susumu Akamatsu