Deposition From Gas Or Vapor (epo) Patents (Class 257/E21.274)
  • Patent number: 11757008
    Abstract: Layered structures described herein include electronic devices with 2-dimensional electron gas between polar-oriented cubic rare-earth oxide layers on a non-polar semiconductor. Layered structure includes a semiconductor device, comprising a III-N layer or rare-earth layer, a polar rare-earth oxide layer grown over the III-N layer or rare-earth layer, a gate terminal deposited or grown over the polar rare-earth oxide layer, a source terminal that is deposited or epitaxially grown over the layer, and a drain terminal that is deposited or grown over the layer.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: September 12, 2023
    Assignee: IQE plc
    Inventors: Rytis Dargis, Andrew Clark, Richard Hammond, Rodney Pelzel, Michael Lebby
  • Patent number: 11649546
    Abstract: A method for selectively depositing a metal oxide film is disclosed. In particular, the method comprises pulsing a metal or semi-metal precursor onto the substrate and pulsing an organic reactant onto the substrate. A reaction between the metal or semi-metal precursor and the organic reactant selectively forms a metal oxide film on either a dielectric layer or a metal layer.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: May 16, 2023
    Assignee: ASM IP Holding B.V.
    Inventors: Antti Niskanen, Eva Tois, Hidemi Suemori, Suvi Haukka
  • Patent number: 11211244
    Abstract: The present disclosure relates to a method of fabricating a semiconductor structure, the method includes forming an opening and depositing a metal layer in the opening. The depositing includes performing one or more deposition cycles, wherein each deposition cycle includes flowing a first precursor into a deposition chamber and performing an ultraviolet (UV) radiation process on the first precursor. The method further includes performing a first purging process in the deposition chamber to remove at least a portion of the first precursor, flowing a second precursor into the deposition chamber, and purging the deposition chamber to remove at least a portion of the second precursor.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing, Co., Ltd.
    Inventors: Christine Y. Ouyang, Ziwei Fang
  • Patent number: 11171047
    Abstract: Methods of forming semiconductor device with fluorine-incorporated metal nitride films are described. A substrate surface is exposed to a metal fluoride precursor to form a metal-fluorine species on the substrate surface. The substrate surface is exposed to a nitriding agent to react with the metal-fluorine species to form a fluorine-incorporated metal nitride film.
    Type: Grant
    Filed: June 28, 2020
    Date of Patent: November 9, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yixiong Yang, Srinivas Gandikota, Steven C. H. Hung, Jacqueline S. Wrench, Yongjing Lin, Susmit Singha Roy, Wei V. Tang, Shih Chung Chen
  • Patent number: 10612137
    Abstract: A method for selectively depositing a metal oxide film is disclosed. In particular, the method comprises pulsing a metal or semi-metal precursor onto the substrate and pulsing an organic reactant onto the substrate. A reaction between the metal or semi-metal precursor and the organic reactant selectively forms a metal oxide film on either a dielectric layer or a metal layer.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: April 7, 2020
    Assignee: ASM IP Holdings B.V.
    Inventors: Antti Niskanen, Eva Tois, Hidemi Suemori, Suvi Haukka
  • Patent number: 10403494
    Abstract: Mono-substituted TSA precursor Si-containing film forming compositions are disclosed. The precursors have the formula: (SiH3)2N—SiH2—X, wherein X is selected from a halogen atom; an isocyanato group; an amino group; an N-containing C4-C10 saturated or unsaturated heterocycle; or an alkoxy group. Methods for forming the Si-containing film using the disclosed mono-substituted TSA precursor are also disclosed.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: September 3, 2019
    Assignee: L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude
    Inventors: Jean-Marc Girard, Peng Zhang, Antonio Sanchez, Manish Khandelwal, Gennadiy Itov, Reno Pesaresi
  • Patent number: 10287675
    Abstract: A film deposition method for forming a film of a reaction product includes adsorbing a first process gas to a surface of a substrate; reacting the first process gas and a second process gas to generate a reaction product; and modifying a surface of the reaction product by plasma activating a plasma processing gas and supplying the plasma processing gas to the substrate, wherein in the modifying the surface of the reaction product, a first plasma processing gas is supplied to form a flow of the first plasma processing gas in a direction parallel to the surface of the substrate over an entire surface of the substrate, and also a second plasma processing gas containing hydrogen containing gas is supplied at an upstream side of the flow of the first plasma processing gas in the direction parallel to the surface of the substrate.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: May 14, 2019
    Assignee: Tokyo Electron Limited
    Inventor: Shigehiro Miura
  • Patent number: 10096516
    Abstract: Embodiments of the disclosure generally relate to a method of improving quality of a barrier layer suitable for forming high aspect ratio through substrate vias. In one example, a method for depositing a barrier layer includes depositing a barrier layer in a hole formed in a substrate, exposing the deposited barrier layer to a processing gas at a pressure greater than about 2 bars, and, maintaining a temperature of the substrate between about 150 degrees and about 700 degrees Celsius while in the presence of the processing gas.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: October 9, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Kurtis Leschkies, Steven Verhaverbeke
  • Patent number: 9978776
    Abstract: A pixel portion and a driver circuit driving the pixel portion are formed over the same substrate. At least a part of the driver circuit is formed using an inverted staggered thin film transistor in which an oxide semiconductor layer is used and a channel protective layer is provided over the oxide semiconductor layer serving as a channel formation region which is overlapped with the gate electrode. The driver circuit as well as the pixel portion is provided over the same substrate to reduce manufacturing costs.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: May 22, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Atsushi Umezaki
  • Patent number: 9964606
    Abstract: According to embodiments there is provided a magneto-resistive sensor module. The sensor module may comprise: an integrated circuit; magneto-resistive sensor elements arranged as a bridge circuit monolithically integrated on the integrated circuit; and a stress buffer layer arranged between the integrated circuit and the magneto-resistive sensor element. There is also a provided a method of manufacturing the magneto-resistive sensor module.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: May 8, 2018
    Assignee: NXP B.V.
    Inventor: Mark Isler
  • Patent number: 9837564
    Abstract: Photodiodes and nuclear batteries may utilize actinide oxides, such a uranium oxide. An actinide oxide photodiode may include a first actinide oxide layer and a second actinide oxide layer deposited on the first actinide oxide layer. The first actinide oxide layer may be n-doped or p-doped. The second actinide oxide layer may be p-doped when the first actinide oxide layer is n-doped, and the second actinide oxide layer may be n-doped when the first actinide oxide layer is p-doped. The first actinide oxide layer and the second actinide oxide layer may form a p/n junction therebetween. Photodiodes including actinide oxides are better light absorbers, can be used in thinner films, and are more thermally stable than silicon, germanium, and gallium arsenide.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: December 5, 2017
    Assignee: Los Alamos National Security, LLC
    Inventors: Milan Sykora, Igor Usov
  • Patent number: 9564329
    Abstract: A composite dielectric structure having one or more Leakage Blocking Layers (LBL) interleaved with one or more Laminate Dielectric Layers (LDL), Alloy Dielectric Layers (ADL), or Co-deposit Dielectric Layers (CDL). Each LDL, ADL, and CDL includes dopants incorporated in a respective base dielectric layer (BDL); where LDLs are formed by incorporating a doping layer into a BDL using a laminate method, ADLs are formed by incorporating a dopant into a BDL using an alloying method; and CDLs are formed by pulsing a BDL base material and a dopant together using a co-deposit method.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: February 7, 2017
    Assignee: AIXTRON, SE
    Inventors: Kay Song, Minghang Li, Brian Lu
  • Patent number: 9437419
    Abstract: A trialkylsilane-based silicon precursor compound may be expressed by Si(Ri)X, i=1-3, where each of “R1”, “R2”, and “R3” is a hydrogen or an alkyl having 1-5 carbon(s), all of “R1”, “R2”, and “R3” are not hydrogen, “X” is one of hydrogen, a hydroxyl group, an amide group, an alkoxide group, a halide group, or Si(R*)3, and “R*” is a hydrogen or an alkyl group having 1˜5 carbon(s).
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: September 6, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Younsoo Kim, Sangyeol Kang, Hiroki Sato, Tsubasa Shiratori, Naoki Yamada, Chayoung Yoo, Younjoung Cho, Chin Moo Cho, Jaehyoung Choi
  • Patent number: 9331261
    Abstract: A piezoelectric element includes, in sequence, a substrate containing metallic material; a first intermediate layer; a lower electrode layer; a piezoelectric layer; and an upper electrode layer. The first intermediate layer contains, as a main component, a nitrogen-containing silicon oxide having a silicon-nitrogen bond. The lower electrode layer contains a perovskite-type oxide in (100) preferential orientation. The piezoelectric layer contains a perovskite-type oxide in (001) or (100) preferential orientation.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: May 3, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takashi Kubo, Toshinari Noda
  • Patent number: 9034761
    Abstract: Disclosed are metal-containing precursors having the formula Compound (I) wherein: —M is a metal selected from Ni, Co, Mn, Pd; and —each of R-1, R2, R3, R4, R5, R6, R7, R8, R9, and R10 are independently selected from H; a C1-C4 linear, branched, or cyclic alkyl group; a C1-C4 linear, branched, or cyclic alkylsilyl group (mono, bis, or tris alkyl); a C1-C4 linear, branched, or cyclic alkylamino group; or a C1-C4 linear, branched, or cyclic fluoroalkyl group. Also disclosed are methods of synthesizing and using the disclosed metal-containing precursors to deposit metal-containing films on a substrate via a vapor deposition process.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: May 19, 2015
    Assignees: L'Air Liquide, SociétéAnonyme pour l'Etude et l'Exploitation des Procédés Georges Claude, American Air Liquide, Inc.
    Inventors: Clément Lansalot-Matras, Andrey V. Korolev
  • Patent number: 9029224
    Abstract: A method is provided for fabricating a High-K layer. The method includes providing a substrate, applying a first precursor gas on the substrate such that the substrate absorbs first precursor gas molecules in a chemical absorption process, and removing the unabsorbed first precursor gas using a first inert gas. The method also includes applying a second precursor gas on the substrate, and forming a first thin film on the substrate as a reaction product of the second precursor gas and the absorbed first precursor gas molecules. Further, the method includes removing unreacted second precursor gas and byproducts using a second inert gas, and forming a high-K layer on the substrate by forming a plurality of the first thin films layer-by-layer.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: May 12, 2015
    Assignee: Semiconductor Manufacturing International Corp.
    Inventors: Yong Chen, Yonggen He
  • Patent number: 8884407
    Abstract: A device includes a tube extending in a longitudinal direction and a hollow channel arranged in the tube. An end part of the tube is formed such that first electromagnetic radiation paths extending in the tube and outside of the hollow channel in the longitudinal direction are focused in a first focus.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: November 11, 2014
    Assignee: Infineon Technologies AG
    Inventors: Michael Sternad, Rainer Pelzer
  • Patent number: 8841182
    Abstract: Methods of treating metal-containing thin films, such as films comprising titanium carbide, with a silane/borane agent are provided. In some embodiments a film including titanium carbide is deposited on a substrate by an atomic layer deposition (ALD) process. The process may include a plurality of deposition cycles involving alternating and sequential pulses of a first source chemical that includes titanium and at least one halide ligand, a second source chemical that includes metal and carbon, where the metal and the carbon from the second source chemical are incorporated into the thin film, and a third source chemical, where the third source chemical is a silane or borane that at least partially reduces oxidized portions of the titanium carbide layer formed by the first and second source chemicals. The treatment can form a capping layer on the metal carbide film.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 23, 2014
    Assignee: ASM IP Holding B.V.
    Inventors: Jerry Chen, Vladimir Machkaoutsan, Brennan Milligan, Jan Willem Maes, Suvi Haukka, Eric Shero, Tom E. Blomberg, Dong Li
  • Patent number: 8759234
    Abstract: A system and method for manufacturing a semiconductor device is provided. An embodiment comprises forming a deposited layer using an atomic layer deposition (ALD) process. The ALD process may utilize a first precursor for a first time period, a first purge for a second time period longer than the first time period, a second precursor for a third time period longer than the first time period, and a second purge for a fourth time period longer than the third time period.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: June 24, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Wen Chang, Cheng-Yuan Tsai, Hsing-Lien Lin
  • Patent number: 8753985
    Abstract: Molecular layer deposition of silicon carbide is described. A deposition precursor includes a precursor molecule which contains silicon, carbon and hydrogen. Exposure of a surface to the precursor molecule results in self-limited growth of a single layer. Though the growth is self-limited, the thickness deposited during each cycle of molecular layer deposition involves multiple “atomic” layers and so each cycle may deposit thicknesses greater than typically found during atomic layer depositions. Precursor effluents are removed from the substrate processing region and then the surface is irradiated before exposing the layer to the deposition precursor again.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: June 17, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Brian Underwood, Abhijit Basu Mallick, Nitin K. Ingle
  • Patent number: 8728951
    Abstract: A method of processing a substrate includes performing a first exposure that comprises generating a plasma containing reactive gas ions in a plasma chamber and generating a bias voltage between the substrate and the plasma chamber. The method also includes providing a plasma sheath modifier having an aperture disposed between the plasma and substrate and operable to direct the reactive gas ions toward the substrate, and establishing a pressure differential between the plasma chamber and substrate region while the reactive gas ions are directed onto the substrate.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: May 20, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Ludovic Godet, Xianfeng Lu, Deepak A. Ramappa
  • Patent number: 8722548
    Abstract: In one exemplary embodiment, a method includes: forming at least one first monolayer of first material on a surface of a substrate by performing a first plurality of cycles of atomic layer deposition; thereafter, annealing the formed at least one first monolayer of first material under a first inert atmosphere at a first temperature between about 650° C. and about 900° C.; thereafter, forming at least one second monolayer of second material by performing a second plurality of cycles of atomic layer deposition, where the formed at least one second monolayer of second material at least partially overlies the annealed at least one first monolayer of first material; and thereafter, annealing the formed at least one second monolayer of second material under a second inert atmosphere at a second temperature between about 650° C. and about 900° C.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: May 13, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shintaro Aoyama, Robert D. Clark, Steven P. Consiglio, Marinus Hopstaken, Hemanth Jagannathan, Paul Charles Jamison, Gert Leusink, Barry Paul Linder, Vijay Narayanan, Cory Wajda
  • Patent number: 8652957
    Abstract: A dielectric such as a gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate oxides formed from elements such as zirconium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: February 18, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Publication number: 20130313657
    Abstract: In some embodiments, the present invention discloses a gate dielectric deposition process, including depositing a fluorinated hafnium oxide by an ALD process utilizing a fluorinated hafnium precursor and an oxidant. A two-step ALD deposition process can be used, including a fluorinated hafnium oxide layer deposition followed by a hafnium oxide layer deposition. Hafnium oxide can provide high dielectric constant, high density, large bandgap and good thermal stability. Fluorinated hafnium oxide can passivate interface states and bulk traps in the hafnium oxide, for example, by forming Si—F or Hf—F bonds, which can improve the reliability of the hafnium oxide gate dielectrics.
    Type: Application
    Filed: May 24, 2012
    Publication date: November 28, 2013
    Applicant: Intermolecular, Inc.
    Inventor: Jinhong Tong
  • Patent number: 8530361
    Abstract: A method for depositing a silicon containing film on a substrate using an organoaminosilane is described herein. The organoaminosilanes are represented by the formulas: wherein R is selected from a C1-C10 linear, branched, or cyclic, saturated or unsaturated alkyl group with or without substituents; a C5-C10 aromatic group with or without substituents, a C3-C10 heterocyclic group with or without substituents, or a silyl group in formula C with or without substituents, R1 is selected from a C3-C10 linear, branched, cyclic, saturated or unsaturated alkyl group with or without substituents; a C6-C10 aromatic group with or without substituents, a C3-C10 heterocyclic group with or without substituents, a hydrogen atom, a silyl group with substituents and wherein R and R1 in formula A can be combined into a cyclic group and R2 representing a single bond, (CH2)n chain, a ring, C3-C10 branched alkyl, SiR2, or SiH2.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: September 10, 2013
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Manchao Xiao, Xinjian Lei, Heather Regina Bowen, Mark Leonard O'Neill
  • Patent number: 8481372
    Abstract: In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: July 9, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Patent number: 8470693
    Abstract: A silicon oxide film (2) comprising an amorphous phase is deposited on a substrate (1) (see a step (b)) by a plasma CVD method using an SiH4 gas and an N2O gas. Subsequently, a sample comprising the silicon oxide film (2)/the substrate (1) is set on an RTA apparatus. The sample (=the silicon oxide film (2)/the substrate (1)) is heat-treated (rapid heating and rapid cooling) (see a step (c)). In this case, a temperature raising rate is 200° C./s, and a temperature in heat treatment is 1000° C.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: June 25, 2013
    Assignee: Hiroshima University
    Inventors: Shin Yokoyama, Yoshiteru Amemiya
  • Patent number: 8445367
    Abstract: In a method of manufacturing a semiconductor device, a plurality of sacrificial layers and a plurality of insulating interlayers are repeatedly and alternately on a substrate. The insulating interlayers include a different material from a material of the sacrificial layers. At least one opening through the insulating interlayers and the sacrificial layers are formed. The at least one opening exposes the substrate. The seed layer is formed on an inner wall of the at least one opening using a first silicon source gas. A polysilicon channel is formed in the at least one opening by growing the seed layer. The sacrificial layers are removed to form a plurality of grooves between the insulating interlayers. A plurality of gate structures is formed in the grooves, respectively.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: May 21, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Tae Noh, Hun-Hyeong Lim, Ki-Hyun Hwang, Jin-Gyun Kim, Sang-Ryol Yang
  • Patent number: 8431494
    Abstract: A film formation method of forming a silicon oxide film on a surface of an object to be processed in a process chamber includes absorbing a seed gas comprising a silane-based gas on the surface of the object to be processed by supplying the seed gas into the process chamber, forming a silicon film having an impurity by supplying a silicon-containing gas as a material gas, and an addition gas including the impurity into the process chamber, and oxidizing the silicon film to convert the silicon film into the silicon oxide film. Accordingly, the silicon oxide film having the high density and the high stress is formed on the surface of the object to be processed.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: April 30, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Hiroki Murakami, Kazuhide Hasebe, Kazuya Yamamoto, Toshihiko Takahashi, Daisuke Suzuki
  • Patent number: 8409984
    Abstract: Certain embodiments disclosed herein relate to the formation of multi-component oxide heterostructures (MCOH) using surface nucleation to pattern the atomic layer deposition (ALD) of perovskite material followed by patterned etch and metallization to produce ultra-high density MCOH nano-electronic devices. Applications include ultra-high density MCOH memory and logic, as well as electronic functionality based on single electrons, for example a novel flash memory cell Floating-Gate (FG) transistor with LaAlO3 as a gate tunneling dielectric. Other types of memory devices (DIMMS, DRAM, and DDR) made with patterned ALD of LaAlO3 as a gate dielectric are also possible.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: April 2, 2013
    Assignee: NexGen Semi Holding, Inc.
    Inventors: Mark Joseph Bennahmias, Michael John Zani, Jeffrey Winfield Scott
  • Patent number: 8377827
    Abstract: A method for forming a gate, which can improve the etching uniformity of the sidewalls of the gate, includes the following steps: forming a dielectric layer on a semiconductor substrate; forming a polysilicon layer on the dielectric layer; etching the polysilicon layer; performing an isotropic plasma etching process on the etched polysilicon layer by using a mixed gases containing a fluorine-based gas and oxygen gas; and cleaning the semiconductor substrate subjected to the isotropic plasma etching process, thereby forming a gate. The present invention further provides a method for forming a shallow trench isolation region, which can improve the filling quality of a subsequent spacer and the electrical properties of the resultant shallow trench isolation region, and a method for planarizing an etched surface of silicon substrate, which can improve the etching uniformity of the surface of silicon substrate.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: February 19, 2013
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Qiuhua Han, Haiyang Zhang, Qingtian Ma
  • Patent number: 8367530
    Abstract: A substrate processing apparatus, including: a reaction container in which a substrate is processed; a seal cap, brought into contact with one end in an opening side of the reaction container via a first sealing member and a second sealing member so as to seal the opening of the reaction container air-tightly; a first gas channel, formed in a region between the first sealing member and the second sealing member in a state where the seal cap is in contact with the reaction container; a second gas channel, provided to the seal cap and through which the first gas channel is in communication with an inside of the reaction container; a first gas supply port that is provided to the reaction container and supplies a first gas to the first gas channel; and a second gas supply port that is provided to the reaction container and supplies a second gas into the reaction container, wherein a front end opening of the first gas supply port opening to the first gas channel, and a base opening of the second gas channel openin
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: February 5, 2013
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Kiyohiko Maeda, Takeo Hanashima, Masanao Osanai
  • Patent number: 8367554
    Abstract: A method for forming a gate, which can improve the etching uniformity of the sidewalls of the gate, includes the following steps: forming a dielectric layer on a semiconductor substrate; forming a polysilicon layer on the dielectric layer; etching the polysilicon layer; performing an isotropic plasma etching process on the etched polysilicon layer by using a mixed gases containing a fluorine-based gas and oxygen gas; and cleaning the semiconductor substrate subjected to the isotropic plasma etching process, thereby forming a gate. The present invention further provides a method for forming a shallow trench isolation region, which can improve the filling quality of a subsequent spacer and the electrical properties of the resultant shallow trench isolation region, and a method for planarizing an etched surface of silicon substrate, which can improve the etching uniformity of the surface of silicon substrate.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: February 5, 2013
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Qiuhua Han, Haiyang Zhang, Qingtian Ma
  • Patent number: 8357619
    Abstract: A silicon-containing insulating film is formed on a target substrate by CVD, in a process field to be selectively supplied with a first process gas including di-iso-propylaminosilane gas and a second process gas including an oxidizing gas or nitriding gas. The film is formed by performing a plurality of times a cycle alternately including first and second steps. The first step performs supply of the first process gas, thereby forming an adsorption layer containing silicon on a surface of the target substrate. The second performs supply of the second process gas, thereby oxidizing or nitriding the adsorption layer on the surface of the target substrate. The second step includes an excitation period of supplying the second process gas to the process field while exciting the second process gas by an exciting mechanism.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: January 22, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhide Hasebe, Shigeru Nakajima, Jun Ogawa
  • Patent number: 8258053
    Abstract: In sophisticated semiconductor devices including transistors having a high-k metal gate electrode structure, disposable spacers may be provided on the encapsulating spacer element with a reduced width so as to not unduly increase a lateral offset of a strain-inducing material to be incorporated into the active region. For this purpose, a multi-layer deposition may be used in combination with a low pressure CVD process.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: September 4, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Matthias Kessler, Andreas Kurz
  • Patent number: 8203176
    Abstract: To make it possible to significantly suppress the leakage current in a semiconductor device having a capacitor structure using a dielectric film. There is provided a composite oxide dielectric which is mainly composed of Zr, Al and O, and which has a composition ratio of Zr and Al in a range of (1?x):x where 0.01?x?0.15, and has a crystal structure. When the dielectric is set to have the Al composition in the above described range and is crystallized, the relative dielectric constant of the dielectric can be significantly increased. When the dielectric is used as a dielectric film of a capacitor of a semiconductor device, the leakage current of the capacitor can be significantly reduced.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: June 19, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Nakagawa, Toru Tatsumi, Nobuyuki Ikarashi, Makiko Oshida
  • Patent number: 8187973
    Abstract: A method for manufacturing a semiconductor device which includes: alternately supplying a silicon source and an oxidant to deposit a silicon oxide film on a surface of a semiconductor substrate, wherein the silicon source is supplied under a supply condition where an adsorption amount of molecules of the silicon source on the semiconductor substrate is increased without causing an adsorption saturation of the molecules of the silicon source on the semiconductor substrate, and wherein the oxidant is supplied under a supply condition where impurities remain in the molecules of the silicon source adsorbed on the semiconductor substrate.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: May 29, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki Sekine, Kazuhei Yoshinaga
  • Publication number: 20120098107
    Abstract: The present invention relates to a process and system for depositing a thin film onto a substrate. One aspect of the invention is depositing a thin film metal oxide layer using atomic layer deposition (ALD).
    Type: Application
    Filed: December 29, 2011
    Publication date: April 26, 2012
    Inventors: Petri Raisanen, Jung Sung-hoon, Verghese Mohith
  • Patent number: 8163634
    Abstract: A method includes an act of providing a crystalline substrate with a diamond-type lattice and an exposed substantially (111)-surface. The method also includes an act of forming a graphene layer or a graphene-like layer on the exposed substantially (111)-surface.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: April 24, 2012
    Assignee: Alcatel Lucent
    Inventors: Jorge Manuel Garcia, Loren N. Pfeiffer
  • Patent number: 8163648
    Abstract: An atomic layer deposition method includes providing a semiconductor substrate within a deposition chamber. A first metal halide-comprising precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. The first monolayer comprises metal and halogen of the metal halide. While flowing the first metal halide-comprising precursor gas to the substrate, H2 is flowed to the substrate within the chamber. A second precursor gas is flowed to the first monolayer effective to react with the first monolayer and form a second monolayer on the substrate. The second monolayer comprises the metal. At least some of the flowing of the first metal halide-comprising precursor gas, at least some of the flowing of the H2, and at least some of the flowing of the second precursor gas are repeated effective to form a layer of material comprising the metal on the substrate.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: April 24, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Guy T. Blalock
  • Patent number: 8143145
    Abstract: A method of producing, at atmospheric pressure, an n-type semiconductive indium sulfide thin film on a substrate using an indium-containing precursor, hydrogen sulfide as a reactive gaseous precursor, and an inert carrier gas stream includes cyclically repeating first and second steps so as to produce an indium sulfide thin film of a desired thickness. The first method phase includes converting the indium-containing precursor to at least one of a dissolved and a gaseous phase, heating the substrate to a temperature in a range of 100° C. to 275° C., directing the indium containing precursor onto the substrate and supplying hydrogen sulfide to the indium-containing precursor in a mixing zone in an amount so as to provide an absolute concentration of hydrogen sulfide that is greater than zero and no greater than 1% by volume. The indium concentration of the indium-containing precursor is set so as to produce a compact In(OHx,Xy,Sz)3 film, where X=halide and x+y+2z=1 with z?0.
    Type: Grant
    Filed: March 14, 2009
    Date of Patent: March 27, 2012
    Assignee: Helmholtz-Zentrum Berlin fuer Materialien und Energie GmbH
    Inventors: Nicholas Allsop, Christian-Herbert Fischer, Sophie Gledhill, Martha Christina Lux-Steiner
  • Patent number: 8093158
    Abstract: Provided are a semiconductor device manufacturing method and a substrate processing apparatus. The method comprise: a first process of forming a film containing a predetermined element on a substrate by supplying a source gas containing the predetermined element to a substrate processing chamber in which the substrate is accommodated; a second process of removing the source gas remaining in the substrate processing chamber by supplying an inert gas to the substrate processing chamber; a third process of modifying the predetermined element-containing film formed in the first process by supplying a modification gas that reacts with the predetermined element to the substrate processing chamber; a fourth process of removing the modification gas remaining in the substrate processing chamber by supplying an inert gas to the substrate processing chamber; and a filling process of filling an inert gas in a gas tank connected to the substrate processing chamber.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: January 10, 2012
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Taketoshi Sato, Masayuki Tsuneda
  • Publication number: 20110312192
    Abstract: A film formation method of forming a silicon oxide film on a surface of an object to be processed in a process chamber includes absorbing a seed gas comprising a silane-based gas on the surface of the object to be processed by supplying the seed gas into the process chamber, forming a silicon film having an impurity by supplying a silicon-containing gas as a material gas, and an addition gas including the impurity into the process chamber, and oxidizing the silicon film to convert the silicon film into the silicon oxide film. Accordingly, the silicon oxide film having the high density and the high stress is formed on the surface of the object to be processed.
    Type: Application
    Filed: June 20, 2011
    Publication date: December 22, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Hiroki MURAKAMI, Kazuhide HASEBE, Kazuya YAMAMOTO, Toshihiko TAKAHASHI, Daisuke SUZUKI
  • Patent number: 8076251
    Abstract: Provided is a method of manufacturing a semiconductor device. The method includes: loading a substrate into a process vessel; performing a process to form an oxide, nitride, or oxynitride film on the substrate by alternately repeating: (a) forming a layer containing an element on the substrate by supplying and exhausting first and second source gases containing the element into and from the process vessel; and (b) changing the layer containing the element into an oxide, nitride, or oxynitride layer by supplying and exhausting reaction gas different from the first and second source gases into and from the process vessel; and unloading the substrate from the process vessel. The first source gas is more reactive than the second source gas, and an amount of the first source gas supplied into the process vessel is set to be less than that of the second source gas supplied into the process vessel.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: December 13, 2011
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Naonori Akae, Yoshiro Hirose, Yushin Takasawa, Yosuke Ota, Ryota Sasajima
  • Patent number: 8058729
    Abstract: The use of atomic layer deposition (ALD) to form a conductive titanium nitride layer produces a reliable structure for use in a variety of electronic devices. The structure is formed by depositing titanium nitride by atomic layer deposition onto a substrate surface using a titanium-containing precursor chemical such as TDEAT, followed by a mixture of ammonia and carbon monoxide or carbon monoxide alone, and repeating to form a sequentially deposited TiN structure. Such a TiN layer may be used as a diffusion barrier underneath another conductor such as aluminum or copper, or as an electro-migration preventing layer on top of an aluminum conductor. ALD deposited TiN layers have low resistivity, smooth topology, high deposition rates, and excellent step coverage and electrical continuity.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: November 15, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Brenda D Kraus, Eugene P. Marsh
  • Patent number: 8043981
    Abstract: Methods and apparatus for forming an oxide layer on a semiconductor substrate are disclosed. A two frequency plasma source is used to form a plasma in a plasma reactor. In various embodiments, different quantities of power are supplied to a power source operating at the first frequency and a power source operating at the second frequency over time.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: October 25, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Kai Ma, Yoshitaka Yokota, Christopher S. Olsen
  • Publication number: 20110256735
    Abstract: Methods for forming metal silicate films are provided. The methods comprise contacting a substrate with alternating and sequential vapor phase pulses of a silicon source chemical, metal source chemical, and an oxidizing agent, wherein the metal source chemical is the next reactant provided after the silicon source chemical. Methods according to some embodiments can be used to form silicon-rich hafnium silicate and zirconium silicate films with substantially uniform film coverages on substrate surface.
    Type: Application
    Filed: July 1, 2011
    Publication date: October 20, 2011
    Applicant: ASM AMERICA, INC.
    Inventors: Chang-Gong Wang, Eric Shero, Glen Wilk
  • Publication number: 20110256731
    Abstract: A method for fabricating the gate dielectric layer comprises forming a high-k dielectric layer over a substrate; forming an oxygen-containing layer on the high-k dielectric layer by an atomic layer deposition process; and performing an inert plasma treatment on the oxygen-containing layer.
    Type: Application
    Filed: April 14, 2010
    Publication date: October 20, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Yang LEE, Xiong-Fei YU, Jian-Hao CHEN, Cheng-Hao HOU, Da-Yuan LEE, Kuang-Yuan HSU
  • Patent number: 8039402
    Abstract: There is provide a method for forming a gate, which can improve the etching uniformity of the sidewalls of the gate, including the following steps: forming a dielectric layer on a semiconductor substrate; forming a polysilicon layer on the dielectric layer; etching the polysilicon layer; performing an isotropic plasma etching process on the etched polysilicon layer by using a mixed gases containing a fluorine-based gas and oxygen gas; and cleaning the semiconductor substrate subjected to the isotropic plasma etching process, thereby forming a gate. there are also provided a method for forming a shallow trench isolation region, which can improve the filling quality of a subsequent spacer and the electrical properties of the resultant shallow trench isolation region by improving the etching uniformity of sidewalls and bottom surface of the shallow trench, and a method for planarizating an etched surface of silicon substrate, which can improve the etching uniformity of the surface of silicon substrate.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: October 18, 2011
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Qiuhua Han, Haiyang Zhang, Qingtian Ma
  • Publication number: 20110250763
    Abstract: A plasma oxidation method includes the steps of: generating oxygen-containing plasma with a process gas containing oxygen; applying a bias voltage to a substrate placed on a stage; and radiating positive ions and negative ions in the oxygen-containing plasma onto the substrate so as to perform plasma oxidation of the substrate while controlling a bias potential of the substrate in such a manner that a maximum value Vmax and a minimum value Vmin of the bias potential and a plasma potential Vp satisfy a following relationship: Vmin<Vp<Vmax.
    Type: Application
    Filed: April 12, 2011
    Publication date: October 13, 2011
    Applicants: TOKAI UNIVERSITY EDUCATIONAL SYSTEM, FUJIFILM CORPORATION
    Inventors: Shuji TAKAHASHI, Haruo SHINDO