Of Silicon Nitride (epo) Patents (Class 257/E21.293)
  • Patent number: 10655221
    Abstract: A method for depositing an oxide film on a substrate by thermal ALD and PEALD, includes: providing a substrate in a reaction chamber; depositing a first oxide film on the substrate by thermal ALD in the reaction chamber; and without breaking a vacuum, continuously depositing a second oxide film on the first oxide film by PEALD in the reaction chamber.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: May 19, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Atsuki Fukazawa, Hideaki Fukuda
  • Patent number: 10431620
    Abstract: The present technique relates to a semiconductor device and an electronic appliance in which the reliability of the fine transistor can be maintained while the signal output characteristic is improved in a device formed by stacking semiconductor substrates.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: October 1, 2019
    Assignee: Sony Corporation
    Inventors: Koichi Baba, Takashi Kubodera, Toshihiko Miyazaki, Hiroaki Ammo
  • Patent number: 10262854
    Abstract: Methods and precursors for forming silicon nitride films are provided. In some embodiments, silicon nitride can be deposited by atomic layer deposition (ALD), such as plasma enhanced ALD. In some embodiments, deposited silicon nitride can be treated with a plasma treatment. The plasma treatment can be a nitrogen plasma treatment. In some embodiments the silicon precursors for depositing the silicon nitride comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%). In some embodiments, a method for depositing silicon nitride films comprises a multi-step plasma treatment.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: April 16, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Shang Chen, Viljami Pore, Ryoko Yamada, Antti Juhani Niskanen
  • Patent number: 10170298
    Abstract: Processes for depositing SiO2 films on a wafer surface utilizing an aminosilane compound as a silicon precursor are described.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: January 1, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Wenbo Yan, Cong Trinh, Ning Li, Victor Nguyen, Mihaela Balseanu, Li-Qun Xia, Mark Saly
  • Patent number: 10038078
    Abstract: A novel plasma process is introduced as an improvement over conventional plasma processes during formation of spacers for FinFET devices. Under this novel plasma process, an oxide layer is grown over sidewall materials and low energy plasma gas is used for the over-etching of the corner areas of the sidewalls. The oxide layer can effectively protect the sidewall materials during the over-etching by the low energy plasma gas and thus to reduce the aforementioned CD losses introduced by the low energy plasma gas. This improved low energy plasma etching technique can protect the fin structure from CD losses as compared to the conventional low energy plasma process, and also avoid damaging fin silicon structure with reduced Si losses as compared to the conventional high energy plasma process.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: July 31, 2018
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Hailan Yi, Tong Lei, Yongyue Chen
  • Patent number: 9953873
    Abstract: Chip structures and fabrication methods for forming such chip structures. A first device structure has a structural feature comprised of a first dielectric material and a second device structure has a structural feature comprised of a second dielectric material. A semiconductor layer has a first section adjacent to the structural feature of the first device structure and a second section adjacent to the structural feature of the second device structure. The first section of the semiconductor layer has a popped relationship relative to the structural feature comprised of the first dielectric material. The second section of the semiconductor layer includes a portion that has a pinned relationship relative to a portion of the structural feature comprised of the second dielectric material.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: April 24, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Bhupesh Chandra, Claude Ortolland, Gregory G. Freeman, Viorel Ontalus, Christopher D. Sheraw, Timothy J. McArdle, Paul Chang
  • Patent number: 9818784
    Abstract: The present technique relates to a semiconductor device and an electronic appliance in which the reliability of the fine transistor can be maintained while the signal output characteristic is improved in a device formed by stacking semiconductor substrates.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: November 14, 2017
    Assignee: Sony Corporation
    Inventors: Koichi Baba, Takashi Kubodera, Toshihiko Miyazaki, Hiroaki Ammo
  • Patent number: 9761456
    Abstract: A method of manufacturing a semiconductor device includes (a) providing a substrate and (b) forming a film including a first element, a second element and a third element in a same group as the second element on the substrate by performing a cycle a predetermined number of times, the cycle including: (b-1) supplying a halogen-based source gas including the first element to the substrate; (b-2) supplying a first reactive gas including the second element and reactive with the halogen-based source gas; and (b-3) supplying a second reactive gas including the third element without mixing the second reactive gas with the first reactive gas, wherein the second reactive gas is reactive with the halogen-based source gas and unreactive with the first reactive gas.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: September 12, 2017
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Kimihiko Nakatani, Kazuhiro Harada, Masahito Kitamura
  • Patent number: 9576792
    Abstract: Methods and precursors for forming silicon nitride films are provided. In some embodiments, silicon nitride can be deposited by atomic layer deposition (ALD), such as plasma enhanced ALD. In some embodiments, deposited silicon nitride can be treated with a plasma treatment. The plasma treatment can be a nitrogen plasma treatment. In some embodiments the silicon precursors for depositing the silicon nitride comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%). In some embodiments, a method for depositing silicon nitride films comprises a multi-step plasma treatment.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: February 21, 2017
    Assignee: ASM IP HOLDING B.V.
    Inventors: Shang Chen, Viljami Pore, Ryoko Yamada, Antti Juhani Niskanen
  • Patent number: 9484217
    Abstract: A method for making contact openings for connecting a transistor from a stack of layers comprising an active layer made of a semi-conductor material, a silicide layer on the top of the active layer, a nitride-based layer on the top of the silicide layer, and an electrically insulating layer on the top of the nitride-based layer, includes opening for forming, in the insulating layer, an exposing opening on the nitride-based layer and delimited by flanks of the insulating layer, and removing the nitride-based layer by modifying the nitride-based layer at the opening using plasma wherein CxHy is introduced where x is the proportion of carbon and y is the proportion of hydrogen ions and comprising ions heavier than hydrogen. The conditions of plasma being so chosen as to modify a portion of the nitride-based layer and to form a protective carbon film on the flanks of the insulating layer.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: November 1, 2016
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventor: Nicolas Posseme
  • Patent number: 9035384
    Abstract: A semiconductor device includes a first fin-shaped silicon layer on a substrate and a second fin-shaped silicon layer on the substrate, each corresponding to the dimensions of a sidewall pattern around a dummy pattern. A silicide in upper portions of n-type and p-type diffusion layers in the upper portions of the first and second fin-shaped silicon layers. A metal gate line is connected to first and second metal gate electrodes and extends in a direction perpendicular to the first fin-shaped silicon layer and the second fin-shaped silicon layer. A first contact is in direct contact with the n-type diffusion layer in the upper portion of the first pillar-shaped silicon layer, and a second contact is in direct contact with the p-type diffusion layer in the upper portion of the second pillar-shaped silicon layer.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: May 19, 2015
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9029228
    Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate. The layer of graphene may be formed in direct contact with the surface of the substrate, or an intervening layer of a material may be formed between the substrate surface and the graphene layer.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: May 12, 2015
    Assignees: SunEdision Semiconductor Limited (UEN201334164H), Kansas State University Research Foundation
    Inventors: Michael R. Seacrist, Vikas Berry, Phong Tuan Nguyen
  • Patent number: 9018104
    Abstract: There is provided a method for manufacturing a semiconductor device, including forming an insulating film having a prescribed composition and a prescribed film thickness on a substrate by alternately performing the following steps prescribed number of times: supplying one of the sources of a chlorosilane-based source and an aminosilane-based source to a substrate in a processing chamber, and thereafter supplying the other source, to form a first layer containing silicon, nitrogen, and carbon on the substrate; and supplying a reactive gas different from each of the sources, to the substrate in the processing chamber, to modify the first layer and form a second layer.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: April 28, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Yoshiro Hirose, Kenji Kanayama, Norikazu Mizuno, Yushin Takasawa, Yosuke Ota
  • Patent number: 9006840
    Abstract: A semiconductor device includes a plurality of semiconductor chips in a stack structure and a through-silicon via suitable for passing through the chips and transfer a signal from or to one or more of the chips. Each of the chips includes a buffering block disposed in path of the through-silicon via, and suitable for buffering the signal, an internal circuit, and a delay compensation block suitable for applying delay corresponding to the buffering blocks of the chips to the signal, wherein the delay compensation blocks of the chips compensates for delay difference of the signal transferred to and from the internal circuit of the chip, due to operations of the buffering block, based on stack information for distinguishing the chips.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: April 14, 2015
    Assignee: SK Hynix Inc.
    Inventors: Sang-Hoon Shin, Young-Ju Kim
  • Patent number: 8999846
    Abstract: An integrated circuit structure includes a plurality of insulator layers (connected to each other) that form a laminated structure. Further included are via openings within each of the insulator layers, and conductive via material within the via openings. The conductive via material within corresponding via openings of adjacent insulator layers are electrically connected to form continuous electrical via paths through the insulator layers between the top surface and the bottom surface of the laminated structure. Within each of the continuous electrical via paths, the via openings are positioned relative to each other to form a diagonal structural path of the conductive via material through the laminated structure. The corresponding via openings of the adjacent insulator layers partially overlap each other. The diagonal structural paths are non-perpendicular to the top surface and the bottom surface.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Luke D. LaCroix, Mark C. H. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
  • Patent number: 8987829
    Abstract: A semiconductor device may include a p-channel semiconductor active region and an n-channel semiconductor active region. An element isolation insulating layer electrically isolates the p-channel semiconductor active region from the n-channel semiconductor active region. An insulating layer made of a different material, being in contact with both ends, in its channel length direction, of the p-channel semiconductor active region applies a compression stress in the channel length direction to a channel of the p-channel semiconductor active region. The p-channel semiconductor active region is surrounded by the insulating layer, in the channel length direction, of the p-channel semiconductor active region and by the element isolation insulating layer, parallel to the channel length direction, of the p-channel semiconductor active region. The n-channel semiconductor active region is surrounded by the element isolation insulating layer.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Shimooka, Takashi Izumida, Hiroki Okamoto
  • Patent number: 8980689
    Abstract: Provided is a method of fabricating a multi-chip stack package. The method includes preparing single-bodied lower chips having a single-bodied lower chip substrate having a first surface and a second surface disposed opposite the first surface, bonding unit package substrates onto the first surface of the single-bodied lower chip substrate to form a single-bodied substrate-chip bonding structure, separating the single-bodied substrate-chip bonding structure into a plurality of unit substrate-chip bonding structures, preparing single-bodied upper chips having a single-bodied upper chip substrate, bonding the plurality of unit substrate-chip bonding structures onto a first surface of the single-bodied upper chip substrate to form a single-bodied semiconductor chip stack structure, and separating the single-bodied semiconductor chip stack structure into a plurality of unit semiconductor chip stack structures.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung-Soo Kwak, Cha-Jea Jo, Tae-Je Cho, Sang-Uk Han
  • Patent number: 8981441
    Abstract: According to one embodiment, a manufacturing method of a magnetic memory includes forming a magnetoresistive element in a cell array section on a semiconductor substrate, forming a dummy element in a peripheral circuit section on the semiconductor substrate, the dummy element having the same stacked structure as the magnetoresistive element and being arranged at the same level as the magnetoresistive element, collectively flattening the magnetoresistive element and the dummy element, applying a laser beam to the dummy element to form the dummy element into a non-magnetic body, and forming an upper electrode on the flattened magnetoresistive element.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Noma, Hiroshi Watanabe, Shinya Kobayashi
  • Patent number: 8952452
    Abstract: Semiconductor devices, and a method of manufacturing the same, include a gate insulating film pattern over a semiconductor substrate. A gate electrode is formed over the gate insulating film pattern. A spacer structure is formed on at least one side of the gate electrode and the gate insulating film pattern. The spacer structure includes a first insulating film spacer contacting the gate insulating film pattern, and a second insulating film spacer on an outer side of the first insulating film spacer. The semiconductor device has an air gap between the first insulating film spacer and the second insulating film spacer.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Seong Kang, Yoon-Hae Kim, Jong-Shik Yoon
  • Patent number: 8951878
    Abstract: It is an object of the present invention to provide a method for manufacturing an SOI substrate having an SOI layer that can be used in practical applications with high yield even when a flexible substrate such as a glass substrate or a plastic substrate is used. Further, it is another object of the present invention to provide a method for manufacturing a thin semiconductor device using such an SOI substrate with high yield. When a single-crystal semiconductor substrate is bonded to a flexible substrate having an insulating surface and the single-crystal semiconductor substrate is separated to manufacture an SOI substrate, one or both of bonding surfaces are activated, and then the flexible substrate having an insulating surface and the single-crystal semiconductor substrate are attached to each other.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: February 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiro Jinbo, Hironobu Shoji, Hideto Ohnuma, Shunpei Yamazaki
  • Patent number: 8952512
    Abstract: A wafer-level package structure of a light emitting diode and a manufacturing method thereof are provided in the present invention. The wafer-level package structure of a light emitting diode includes a die, a first insulating layer, at least two wires, bumps, an annular second insulating layer on the wires and the insulating layer, the annular second insulating layer surrounding an area between the bumps and there being spaces arranged between the second insulating layer and the bumps; a light reflecting cup on the second insulating layer; at least two discrete lead areas and leads in the lead areas. The technical solution of the invention reduces the area required for the substrate; and the electrodes can be extracted in the subsequent structure of the package without gold wiring to thereby further reduce the volume of the package.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: February 10, 2015
    Assignee: China Wafer Level CSP Ltd.
    Inventors: Junjie Li, Wenbin Wang, Qiuhong Zou, Guoqing Yu, Wei Wang
  • Patent number: 8946021
    Abstract: On a silicon substrate is formed a stacked body by alternately stacking a plurality of silicon oxide films and silicon films, a trench is formed in the stacked body, an alumina film, a silicon nitride film and a silicon oxide film are formed in this order on an inner surface of the trench, and a channel silicon crystalline film is formed on the silicon oxide film. Next, a silicon oxide layer is formed at an interface between the silicon oxide film and the channel silicon crystalline film by performing thermal treatment in an oxygen gas atmosphere.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: February 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshio Ozawa
  • Patent number: 8927433
    Abstract: Provided is a technology for forming a conductive via hole to implement a three dimensional stacked structure of an integrated circuit. A method for forming a conductive via hole according to an embodiment of the present invention comprises: filling inside of a via hole structure that is formed in one or more of an upper portion and a lower portion of a substrate with silver by using a reduction and precipitation of silver in order to connect a plurality of stacked substrates by a conductor; filling a portion that is not filled with silver inside of the via hole structure by flowing silver thereinto; and sublimating residual material of silver oxide series, which is generated during the flowing, on an upper layer inside of the via hole structure filled with silver.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: January 6, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventor: Jin-Yeong Kang
  • Patent number: 8921174
    Abstract: Disclosed herein is a method for fabricating a complementary tunneling field effect transistor based on a standard CMOS IC process, which belongs to the field of logic devices and circuits of field effect transistors in ultra large scaled integrated (ULSI) circuits. In the method, an intrinsic channel and body region of a TFET are formed by means of complementary P-well and N-well masks in the standard CMOS IC process to form a well doping, a channel doping and a threshold adjustment by implantation. Further, a bipolar effect in the TFET can be inhibited via a distance between a gate and a drain on a layout so that a complementary TFET is formed. In the method according to the invention, the complementary tunneling field effect transistor (TFET) can be fabricated by virtue of existing processes in the standard CMOS IC process without any additional masks and process steps.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: December 30, 2014
    Assignee: Peking University
    Inventors: Ru Huang, Qianqian Huang, Zhan Zhan, Yingxin Qiu, Yangyuan Wang
  • Patent number: 8916478
    Abstract: A CMOS SGT manufacturing method includes a step of forming first and second fin-shaped silicon layers on a substrate, forming a first insulating film around the first and second fin-shaped silicon layers, and forming first and second pillar-shaped silicon layers; a step of forming n-type diffusion layers; a step of forming p-type diffusion layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers in upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing the first and second polysilicon gate electrodes, etching the first and second polysilicon gate electrodes, and then depositing a metal to form first and second metal gate electrodes.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: December 23, 2014
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 8906811
    Abstract: A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epitaxial growth process including a plurality of growth/etch cycles may be used at low temperatures in an ultra-high vacuum ambient, thereby obtaining a substantially bottom to top fill behavior.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: December 9, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thorsten Kammler, Andy Wei, Ina Ostermay
  • Patent number: 8901010
    Abstract: Methods for protecting a texturized region and a lightly doped diffusion region of a solar cell to improve solar cell lifetime and efficiency are disclosed. In an embodiment, an example method includes providing a solar cell having a front side which faces the sun during normal operation and a back side opposite the front side, a silicon substrate and where the silicon substrate includes a texturized region and a lightly doped diffusion region. The method includes placing the solar cell on a receiving medium with the front side of the solar cell placed on an upper surface of the receiving medium, where the upper surface of the receiving medium prevents damage to the to the lightly doped diffusion region and damage to the texturized region on the front side of the solar cell during a contact printing process or transferring. In an embodiment, the lightly doped diffusion region has a doping concentration below 1×1019 cm?3 and the receiving medium includes a material having a moh's hardness in the range of 5-10.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 2, 2014
    Assignee: SunPower Corporation
    Inventors: Staffan Westerberg, Florito Dennis Tingchuy Vicente, Michael Cudzinovic, Princess Carmi Tomada, Jemellee Guiao
  • Patent number: 8896110
    Abstract: Embodiments of the present disclosure describe techniques and configurations for paste thermal interface materials (TIMs) and their use in integrated circuit (IC) packages. In some embodiments, an IC package includes an IC component, a heat spreader, and a paste TIM disposed between the die and the heat spreader. The paste TIM may include particles of a metal material distributed through a matrix material, and may have a bond line thickness, after curing, of between approximately 20 microns and approximately 100 microns. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 25, 2014
    Assignee: Intel Corporation
    Inventors: Wei Hu, Zhizhong Tang, Syadwad Jain, Rajen S. Sidhu
  • Patent number: 8895455
    Abstract: To form an insulating film with extremely low concentration of impurities such as carbon, hydrogen, nitrogen, chlorine, etc in a film. There are provided the steps of forming a specific element-containing layer on a substrate by supplying source gas containing a specific element into a processing container in which the substrate is accommodated; changing the specific element-containing layer into a nitride layer, by activating and supplying gas containing nitrogen into the processing container; and changing the nitride layer into an oxide layer or an oxynitride layer, by activating and supplying gas containing oxygen into the processing container; with this cycle set as one cycle and performed for at least one or more times.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: November 25, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Naonori Akae, Yoshiro Hirose
  • Patent number: 8889568
    Abstract: Disclosed are: a method for producing a silicon nitride film, wherein generation of blisters at the periphery of a substrate is suppressed when a silicon nitride film is formed through application of a bias power; and an apparatus for producing a silicon nitride film. Specifically disclosed are a method and apparatus for producing a silicon nitride film, wherein a silicon nitride film used for a semiconductor element is formed on a substrate by plasma processing. In the method and apparatus for producing a silicon nitride film, a bias is applied to the substrate at time (b1), and a starting material gas SiH4 for the silicon nitride film is started to be supplied at time (b3) after the application of the bias.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: November 18, 2014
    Assignee: Mitsubishi Heavy Industries, Ltd.
    Inventors: Seiji Nishikawa, Hidetaka Kafuku, Tadashi Shimazu
  • Patent number: 8889523
    Abstract: A semiconductor process includes the following steps. A substrate having a recess is provided. A decoupled plasma nitridation process is performed to nitride the surface of the recess for forming a nitrogen containing liner on the surface of the recess. A nitrogen containing annealing process is then performed on the nitrogen containing liner.
    Type: Grant
    Filed: January 2, 2012
    Date of Patent: November 18, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Te-Lin Sun, Chien-Liang Lin, Yu-Ren Wang, Ying-Wei Yen
  • Patent number: 8883571
    Abstract: A method of manufacturing a transistor includes: forming an oxide semiconductor film and a gate electrode on a substrate, the oxide semiconductor film having a channel region, and the gate electrode facing the channel region; and forming an insulating film covering the gate electrode and the oxide semiconductor film. Infiltration of moisture from the insulating film into the oxide semiconductor film is suppressed by the substrate.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: November 11, 2014
    Assignee: Sony Corporation
    Inventors: Narihiro Morosawa, Motohiro Toyota
  • Patent number: 8884336
    Abstract: A light emitting device according to the embodiment includes a first electrode; a light emitting structure including a first semiconductor layer over the first electrode, an active layer over the first semiconductor layer, and a second semiconductor layer over the second semiconductor layer; a second electrode over the second semiconductor layer; and a connection member having one end making contact with the first semiconductor layer and the other end making contact with the second semiconductor layer to form a schottky contact with respect to one of the first and second semiconductor layers.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: November 11, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Hwan Hee Jeong
  • Patent number: 8884310
    Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a semiconductor substrate. The method includes forming a carbon-containing layer on a front surface of a semiconductor substrate and depositing a metal film on the carbon layer. A thermal cycle degrades the carbon-containing layer, which forms graphene directly upon the semiconductor substrate upon cooling. In some embodiments, the carbon source is a carbon-containing gas, and the thermal cycle causes diffusion of carbon atoms into the metal film, which, upon cooling, segregate and precipitate into a layer of graphene directly on the semiconductor substrate.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: November 11, 2014
    Assignees: SunEdison Semiconductor Limited (UEN201334164H), KSU Research Foundation
    Inventors: Michael R. Seacrist, Vikas Berry
  • Patent number: 8884377
    Abstract: In one embodiment, first and second pattern structures respectively include first and second conductive line patterns and first and second hard masks sequentially stacked, and at least portions thereof extends in a first direction. The insulation layer patterns contact end portions of the first and second pattern structures. The first pattern structure and a first insulation layer pattern of the insulation layer patterns form a first closed curve shape in plan view, and the second pattern structure and a second insulation layer pattern of the insulation layer patterns form a second closed curve shape in plan view. The insulating interlayer covers upper portions of the first and second pattern structures and the insulation layer patterns, a first air gap between the first and second pattern structures, and a second air gap between the insulation layer patterns.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sok-Won Lee, Joon-Hee Lee, Jung-Dal Choi, Seong-Min Jo
  • Patent number: 8865543
    Abstract: The embodiments of the present invention provide a Ge-based NMOS device structure and a method for fabricating the same. By using the method, double dielectric layers of germanium oxide (GeO2) and metal oxide are deposited between the source/drain region and the substrate. The present invention not only reduces the electron Schottky barrier height of metal/Ge contact, but also improves the current switching ratio of the Ge-based Schottky and therefore, it will improve the performance of the Ge-based Schottky NMOS transistor. In addition, the fabrication process is very easy and completely compatible with the silicon CMOS process. As compared with conventional fabrication method, the Ge-based NMOS device structure and the fabrication method in the present invention can easily and effectively improve the performance of the Ge-based Schottky NMOS transistor.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: October 21, 2014
    Assignee: Peking University
    Inventors: Ru Huang, Zhiqiang Li, Xia An, Yue Guo, Xing Zhang
  • Patent number: 8846542
    Abstract: The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: September 30, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kevin R. Shea, Thomas M. Graettinger
  • Patent number: 8846464
    Abstract: An approach for controlling a critical dimension (CD) of a RMG of a semiconductor device is provided. Specifically, embodiments of the present invention allow for CD consistency between a dummy gate and a subsequent RMG. In a typical embodiment, a dummy gate having a cap layer is formed over a substrate. A re-oxide layer is then formed over the substrate and around the dummy gate. A set of doping implants will then be implanted in the substrate, and the re-oxide layer will subsequently be removed (after the set of doping implants have been implanted). A set of spacers will then be formed along a set of side walls of the dummy gate and an epitaxial layer will be formed around the set of side walls. Thereafter, the dummy gate will be replaced with a metal gate (e.g., an aluminum or tungsten body having a high-k metal liner there-around).
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 30, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Bingwu Liu, Baofu Zhu, Nam Sung Kim
  • Patent number: 8846550
    Abstract: The negative effect of oxygen on some metal films can be reduced or prevented by contacting the films with a treatment agent comprising silane or borane. In some embodiments, one or more films in an NMOS gate stack are contacted with a treatment agent comprising silane or borane during or after deposition.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 30, 2014
    Assignee: ASM IP Holding B.V.
    Inventors: Eric Shero, Suvi Haukka
  • Patent number: 8841183
    Abstract: On a silicon substrate is formed a stacked body by alternately stacking a plurality of silicon oxide films and silicon films, a trench is formed in the stacked body, an alumina film, a silicon nitride film and a silicon oxide film are formed in this order on an inner surface of the trench, and a channel silicon crystalline film is formed on the silicon oxide film. Next, a silicon oxide layer is formed at an interface between the silicon oxide film and the channel silicon crystalline film by performing thermal treatment in an oxygen gas atmosphere.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: September 23, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshio Ozawa
  • Patent number: 8796149
    Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. An emitter is formed in a device region defined in a substrate. An intrinsic base is formed on the emitter. A collector is formed that is separated from the emitter by the intrinsic base. The collector includes a semiconductor material having an electronic bandgap greater than an electronic bandgap of a semiconductor material of the device region.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: James W. Adkisson, David L. Harame, Qizhi Liu
  • Patent number: 8785330
    Abstract: A method for producing a structure including an active part with a first and a second suspended zone. The method includes machining the front face of a first substrate to define the lateral contours of at least one first suspended zone according to a first thickness less than that of the first substrate forming a stop layer of etching of the first suspended zone under the suspended zone, forming on the front face of the first substrate a sacrificial layer, machining from the rear face of the first substrate up to releasing the sacrificial layer to form at least one second suspended zone to reach the stop layer of the first suspended zone, and releasing the first and second suspended zones.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: July 22, 2014
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Philippe Robert, Sophie Giroud
  • Patent number: 8779435
    Abstract: A semiconductor wafer has a plurality of optical semiconductor devices (namely, semiconductor lasers) which are formed from epitaxially grown layers and arranged across the surface of the semiconductor wafer. The InGaAs epitaxial layer of the semiconductor wafer has an opening (or groove) which continuously extends along and between the plurality of optical semiconductor devices, and which exposes the layer underlying the InGaAs epitaxial layer to at least the layer overlying the InGaAs epitaxial layer. The semiconductor wafer may be scribed along this opening to form a vertically extending crack therein.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: July 15, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Masato Negishi
  • Patent number: 8772173
    Abstract: A method of manufacturing a semiconductor device includes providing a substrate having a gate structure, a source region, and a drain region formed thereon, and the gate structure includes a gate insulating layer and a gate electrode. The method also includes forming a first stress layer on the substrate, removing the first stress layer, and forming a second stress layer on the substrate.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: July 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-kwan Yu, Dong-suk Shin, Pan-kwi Park, Ki-eun Kim
  • Patent number: 8772175
    Abstract: A CMOS SGT manufacturing method includes a step of forming first and second fin-shaped silicon layers on a substrate, forming a first insulating film around the first and second fin-shaped silicon layers, and forming first and second pillar-shaped silicon layers; a step of forming n-type diffusion layers; a step of forming p-type diffusion layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers in upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing the first and second polysilicon gate electrodes, etching the first and second polysilicon gate electrodes, and then depositing a metal to form first and second metal gate electrodes.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: July 8, 2014
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 8765549
    Abstract: Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. In an embodiment, a capacitor is formed between a through via and a lower level metallization layer. The capacitor may be, for example, a planar capacitor formed on the substrate or on a dielectric layer formed over the substrate.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hua Chang, Shin-Puu Jeng, Der-Chyang Yeh, Shang-Yun Hou, Wen-Chih Chiou
  • Patent number: 8765608
    Abstract: Methods for making a semiconductor device are disclosed. The method includes forming a plurality of gate stacks on a substrate, forming an etch buffer layer on the substrate, forming a dielectric material layer on the etch buffer layer, forming a hard mask layer on the substrate, wherein the hard mask layer includes one opening, and etching the dielectric material layer to form a plurality of trenches using the hard mask layer and the etch buffer layer as an etch mask.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ya Hui Chang
  • Patent number: 8759977
    Abstract: An integrated circuit structure includes a plurality of insulator layers (connected to each other) that form a laminated structure. Further included are via openings within each of the insulator layers, and conductive via material within the via openings. The conductive via material within corresponding via openings of adjacent insulator layers are electrically connected to form continuous electrical via paths through the insulator layers between the top surface and the bottom surface of the laminated structure. Within each of the continuous electrical via paths, the via openings are positioned relative to each other to form a diagonal structural path of the conductive via material through the laminated structure. The corresponding via openings of the adjacent insulator layers partially overlap each other. The diagonal structural paths are non-perpendicular to the top surface and the bottom surface.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: June 24, 2014
    Assignee: International Business Machines Corporation
    Inventors: Luke D. LaCroix, Mark C. H. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
  • Patent number: 8753989
    Abstract: High tensile stress in a deposited layer, such as a silicon nitride layer, may be achieved utilizing one or more techniques employed either alone or in combination. In one embodiment, a silicon nitride film having high tensile stress may be formed by depositing the silicon nitride film in the presence of a porogen. The deposited silicon nitride film may be exposed to at least one treatment selected from a plasma or ultraviolet radiation to liberate the porogen. The silicon nitride film may be densified such that a pore resulting from liberation of the porogen is reduced in size, and Si—N bonds in the silicon nitride film are strained to impart a tensile stress in the silicon nitride film. In another embodiment, tensile stress in a silicon nitride film may be enhanced by depositing a silicon nitride film in the presence of a nitrogen-containing plasma at a temperature of less than about 400° C., and exposing the deposited silicon nitride film to ultraviolet radiation.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: June 17, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Mihaela Balseanu, Michael S. Cox, Li-Qun Xia, Mei-Yee Shek, Jia Lee, Vladimir Zubkov, Tzu-Fang Huang, Rongping Wang, Isabelita Roflox, Hichem M'Saad
  • Patent number: 8716149
    Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a gate structure. An atomic layer deposition (ALD) process is performed to deposit a spacer around the gate structure. The ALD process includes alternating flowing ionized radicals of a first precursor across the semiconductor substrate and flowing a chlorosilane precursor across the semiconductor substrate to deposit the spacer.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: May 6, 2014
    Assignee: GlobalFoundries, Inc.
    Inventors: Fabian Koehler, Sergej Mutas, Dina Triyoso, Itasham Hussain