Abstract: In fabricating a microelectromechanical structure (MEMS), a method of forming a narrow gap in the MEMS includes a) depositing a layer of sacrificial material on the surface of a supporting substrate, b) photoresist masking and at least partially etching the sacrificial material to form at least one blade of sacrificial material, c) depositing a structural layer over the sacrificial layer, and d) removing the sacrificial layer including the blade of the sacrificial material with a narrow gap remaining in the structural layer where the blade of sacrificial material was removed.

Abstract: In a method of manufacturing a semiconductor device, an isolation pattern is formed on a substrate. The isolation pattern includes an opening that exposes a portion of the substrate. A preliminary polysilicon layer is formed on the substrate and the isolation pattern to partially fill up the opening. A sacrificial layer is formed on the preliminary polysilicon layer. The sacrificial layer is partially etched to expose a portion of the preliminary polysilicon layer formed on a shoulder portion of the isolation pattern. A first polysilicon layer is formed by etching the exposed portion of the preliminary polysilicon layer to enlarge an upper width of the opening. After the etched sacrificial layer is removed, a second polysilicon layer is formed on the first polysilicon layer to fill up the enlarged opening.

Abstract: Example embodiments are directed to a method of planarizing a semiconductor device. A first CMP process may be performed on an insulating layer to remove a stepped structure of the insulating layer. A second CMP process may be performed to planarize the insulating layer with the stepped structure removed until a given pattern is exposed. A process temperature of the first CMP process may be higher than that of the second CMP process. Accordingly, an initial stepped structure may be more readily removed in a planarization process of a surface of the semiconductor device, which may reduce the CMP process time and may increase the degree of planarization.

Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.

Abstract: An integrated circuit device, e.g., a memory device, includes a substrate, and a plurality of rows of active regions in the substrate, the active regions arranged in a staggered pattern such that active regions of a first row are aligned with portions of an isolation region separating active regions of an adjacent second row. Source and drain regions are in the active regions and are arranged such that each active region comprises a drain region disposed between two source regions. A plurality of word line structures are on the substrate, arranged transverse to the rows of active regions such that that word line structures cross the active regions between the source regions and the drain regions. Respective rows of conductive pads are disposed between respective adjacent word lines structures, including first conductive pads on the source regions, second conductive pads on the drain regions, and third conductive on isolation regions separating active regions.

Abstract: Following CMP, a magnetic tunnel junction stack may protrude through the oxide that surrounds it, making it susceptible to possible shorting to its sidewalls. The present invention overcomes this problem by depositing silicon nitride spacers on these sidewalls prior to oxide deposition and CMP. So, even though the stack may protrude through the top surface of the oxide after CMP, the spacers serve to prevent possible later shorting to the stack.

Abstract: Provided is a method of manufacturing a semiconductor device with enhanced electrical characteristics. The method includes disposing a substrate on a substrate support in a process chamber, pre-heating the substrate on the substrate support adjusted to a temperature from 300 to 400° C. for 60 seconds or more, forming a silicon protective layer on the substrate by supplying a silicon source gas into the process chamber and heating the substrate on the substrate support adjusted to a temperature from 300 to 400° C. for 10 seconds or more, and forming a tungsten layer on the silicon protective layer.

Abstract: A method for producing a semiconductor device, polishing method, and polishing apparatus, suppressing occurrence of dishing and erosion in a flattening process by polishing of a metal film for constituting an interconnection of a semiconductor device having a multilayer interconnection structure. The production method includes the steps of: forming a passivation film exhibiting an action of inhibiting an electrolytic reaction of a metal at the surface of the metal film; selectively removing the passivation film on a projecting portion so as to expose the projecting portion of the metal film at the surface; removing the exposed projecting portion of the metal film by electrolytic polishing so as to flatten unevenness of the surface of the metal film; and removing the metal film present on an insulation film from the metal film with the flattened surface by electrolytic composite polishing combining electrolytic polishing and mechanical polishing so as to form an interconnection.

Abstract: The invention utilizes colloidal silica soot (62) in a semiconductor process for chemical-mechanical planarizing a semiconductor integrated circuit workpiece (24) with a slurry (60). The particulate abrasive agent colloidal solid sphere fused silica soot (62) provides a beneficial CMP slurry/process for semiconductor device manufacturing compared to standard semiconductor CMP slurries with conventional colloidal sol-gel or fumed silica.

Abstract: In an independent GaN film manufactured by creating a GaN layer on a base heterosubstrate using vapor-phase deposition and then removing the base substrate, owing to layer-base discrepancy in thermal expansion coefficient and lattice constant, warp will be a large ±40 ?m to ±100 ?m. Since with that warp device fabrication by photolithography is challenging, reducing the warp to +30 ?m to ?20 ?m is the goal. The surface deflected concavely is ground to impart to it a damaged layer that has a stretching effect, making the surface become convex. The damaged layer on the surface having become convex is removed by etching, which curtails the warp. Alternatively, the convex surface on the side opposite the surface having become convex is ground to generate a damaged layer. With the concave surface having become convex due to the damaged layer, suitably etching off the damaged layer curtails the warp.

Abstract: A method of forming a shallow trench isolation (STI) region in a silicon substrate creates an STI region that extends above a top surface of the silicon substrate. A planarizing dielectric layer is formed on the substrate and extends above the field oxide regions. The planarizing dielectric layer is removed by chemical mechanical polishing or blanket etch back, for example, as well as those portions of the field oxide regions that extend above the top surface of the substrate and the active regions. The step height is thereby eliminated or significantly reduced.

Abstract: A method of forming a structure, an array of structures and a memory cell, the method of fabricating a structure, including: (a) forming a trench in a substrate; (b) depositing a first layer of polysilicon on a surface of the substrate, the first layer of polysilicon filling the trench; (c) chemical-mechanical-polishing the first layer of polysilicon at a first temperature to expose the surface of the substrate; (d) removing an upper portion of the first polysilicon from the trench; (e) depositing a second layer of polysilicon on the surface of the substrate, the second layer of polysilicon filling the trench; and (f) chemical-mechanical-polishing the second layer of polysilicon at a second temperature to expose the surface of the substrate, the second temperature different from the first temperature.

Abstract: A method of forming a pre-metal dielectric (PMD) layer is disclosed. In the method, after a nitride liner layer is formed on a substrate having a transistor, a USG layer is deposited thereon and then planarized. Next, ion implantation and annealing are performed for gettering, first in a gate region and then in a non-gate region of the USG layer. The USG layer is generally free from plasma damage and has a good gap-fill capability. Further, ion implantation and annealing after deposition of the USG layer may enhance a gap-fill capability, a gettering capability, and electrical properties of a transistor.

Abstract: A method for forming a multi-level semiconductor device to eliminate conductive interconnect protrusions following a WAT test, the method including forming a first metallization layer; carrying out a wafer acceptance testing (WAT) process; and, then carrying out a chemical mechanical polish (CMP) on the metallization layer.

Abstract: In the case that a stacked layer, in which another metal layer is stacked on an Al layer or Al alloy layer having a low resistance, is used as a wiring material, an etchant is provided which can etch to a substantially equal etching rate by executing only one etching on the each metal layer composing the stacked layer. A method of manufacturing a substrate for an electronic device uses the etchant, producing an electronic device having the substrate. In order to achieve the object, the etchant has fluoric acid, periodic acid and sulfuric acid wherein the total weight ratio of the fluoric acid and periodic acid is 0.05˜30 wt %, the weight ratio of the sulfuric acid is 0.05˜20 wt %, the weight ratio of periodic acid to fluoric acid is 0.01˜2 wt %. Also each layer of wiring (5, 12, 14) formed by stacking Al layer or Al alloy layer and Ti layer or Ti alloy layer can be uniformly etched to substantially equal etching rate by the etchant.

Abstract: Disclosed in a method of forming a copper wiring in a semiconductor device. A copper layer buries a damascene pattern in which an interlayer insulating film of a low dielectric constant. The copper layer is polished by means of a chemical mechanical polishing process to form a copper wiring within a damascene pattern. At this time, the chemical mechanical polishing process is overly performed so that the top surface of the copper wiring is concaved and is lower than the surface of the interlayer insulating film of the low dielectric constant neighboring it. Furthermore, an annealing process is performed so that the top surface of the copper wiring is changed from the concaved shape to a convex shape while stabilizing the copper wiring. A copper anti-diffusion insulating film is then formed on the entire structure including the top surface of the copper wiring having the convex shape.

Abstract: A method of forming multiple conductive structures in a semiconductor device includes forming spacers adjacent side surfaces of a mask, where the mask and the spacers are formed on a conductive layer. The method also includes etching at least one trench in a portion of the conductive layer not covered by the spacers or the mask. The method may further include depositing a material over the semiconductor device, removing the mask and etching the conductive layer to remove portions of the conductive layer not covered by the spacers or the material, where remaining portions of the conductive layer form the conductive structures.

Abstract: A wet-etch composition may include: peracetic acid (PAA); and a fluorinated acid; a relative amount of the PAA in the composition being sufficient to ensure an etch rate of (P-doped-SiGe):(P-doped-Si) that is substantially the same as an etch rate of (N-doped-SiGe):(N-doped-Si). Such a wet-etch composition is hereafter referred to as a PAA-based etchant and can be used to make, e.g., a CMOS MBCFET, an electrode of a capacitor, etc.

Abstract: On a substrate are sequentially formed a first interconnection 203, a diffusion barrier film 205 and a second insulating film 207, and on the upper surface of the second insulating film 207 is then formed a sacrificial film 213. Next, a via hole 211 and an interconnection trench 217 are formed, and on the sacrificial film 213 are then formed a barrier metal film 219 and a copper film 221. CMP for removing the extraneous copper film 221 and barrier metal film 219 are conducted in a two-step process, i. e., the first polishing where polishing is stopped on the surface of the barrier metal film 219 and the second polishing where the remaining barrier metal film 219 and the tapered sacrificial film 213 are polished.

Abstract: A method for removing a metal oxide overlayer over a target polishing surface in conjunction with a chemical mechanical polishing (CMP) process to improve polishing uniformity including providing a substrate target polishing surface having a layer of an oxide of a metal overlying said metal to be chemically mechanically polished; removing the layer of an oxide of the metal using an oxide removal solution prior to performing a CMP process with an abrasive slurry; and, polishing the target polishing surface according to an a CMP process with an abrasive slurry including at least one of an oxidizer and a complexing agent.

Abstract: A method for Chemical-Mechanical Polishing utilizes a two step process. The first step utilizes a slurry with abrasive particles which become embedded into a conditioned polishing pad having small cavities in the surface. During the second step the slurry flow is discontinued and the final polishing is performed using the embedded small abrasive particles. Using this method dishing has been reduced considerably, and has enabled the fabrication of a Damascene metal gate NMOSFET fabricated with Atomic Layer Deposition (ALD).

Abstract: Two problems seen in CMP as currently executed are a tendency for slurry particles to remain on the surface and the formation of a final layer of oxide. These problems have been solved by adding to the slurry a quantity of TMAH or TBAH. This has the effect of rendering the surface being polished hydrophobic. In that state a residual layer of oxide will not be left on the surface at the conclusion of CMP. Nor will many slurry abrasive particles remain cling to the freshly polished surface. Those that do are readily removed by a simple rinse or buffing. As an alternative, the CMP process may be performed in three stages—first convention CMP, then polishing in a solution of TMAH or TBAH, and finally a gentle rinse or buffing.

Abstract: According to one exemplary embodiment, a method comprises a step of etching a trench in an ILD layer, said trench having sidewalls and a bottom surface. The method further comprises determining a height of the sidewalls of the trench. The method further comprises filling the trench with interconnect metal such the interconnect metal extends above the trench. According to this exemplary embodiment, the method further comprises performing a CMP process to remove a portion of the interconnect metal. In the present invention, the height of the sidewalls of the trench is utilized to control an amount of polishing performed in the CMP process. The remaining portion of interconnect metal in the trench forms an interconnect line, where the thickness of the interconnect line is controlled by utilizing the height of the sidewalls of the trench to control the amount of polishing in the CMP process.

Abstract: The invention provides a method of polishing a substrate comprising a noble metal comprising (i) contacting the substrate with a CMP system and (ii) abrading at least a portion of the substrate to polish the substrate. The CMP system comprises an abrasive and/or polishing pad, a liquid carrier, and a sulfonic acid compound.

Abstract: Provided are an aqueous dispersion for chemical mechanical polishing, which planarizes a surface to be polished and has high shelf stability, a chemical mechanical polishing process excellent in selectivity when surfaces of different materials are polished, and a production process of a semiconductor device. A first aqueous dispersion contains a water-soluble quaternary ammonium salt, an inorganic acid salt, abrasive grains and an aqueous medium. A second aqueous dispersion contains at least a water-soluble quaternary ammonium salt, another basic organic compound other than the water-soluble quaternary ammonium salt, an inorganic acid salt, a water-soluble polymer, abrasive grains and an aqueous medium.