Abstract: A substrate processing method includes a first process of supplying an etching liquid to a peripheral portion of a substrate while rotating the substrate having a metal polycrystalline film formed on a front surface thereof; a second process of supplying a rinse liquid to a portion of the substrate closer to a center side of the substrate than a supply position of the etching liquid in the first process while rotating the substrate; a third process of supplying the etching liquid to the peripheral portion of the substrate while rotating the substrate; a fourth process of supplying the rinse liquid to a portion of the substrate closer to the center side of the substrate than a supply position of the etching liquid in the third process while rotating the substrate; and a fifth process of drying the substrate after the fourth process.

Abstract: A substrate processing method includes performing a liquid processing, detecting a temperature, generating temperature distribution information and determining whether a result of the liquid processing is good or bad. The liquid processing is performed on a substrate by using a processing unit. A temperature of a central portion of the substrate and a temperature of an edge portion of the substrate in the liquid processing are detected by using multiple sensors provided in the processing unit. The temperature distribution information indicating an in-surface temperature distribution of the substrate in the liquid processing is generated based on one or more parameter values defining a processing condition for the liquid processing and the temperature of the central portion of the substrate and the temperature of the edge portion of the substrate. Whether the result of the liquid processing is good or bad is determined based on the temperature distribution information.

Abstract: A grinding apparatus includes a grinding unit, a grinding feeding mechanism, and a grinding water supply unit. The grinding water supply unit includes a nozzle that jets grinding water to grindstones, and a biasing mechanism that biases the nozzle upward. The nozzle is configured to be movable downward against the upward biasing according to a downward movement of the grinding unit. The grinding apparatus further includes an upper limit stopping section that sets an upper limit position for upward movement of the nozzle biased upward by the biasing mechanism, for forming a gap through which the grinding wheel is passed, between the nozzle and the mount.

Abstract: A semiconductor structure formation method and a mask are provided.

Abstract: Electroplating systems according to embodiments of the present technology may include a plating chamber configured to deposit metal material onto substrates positioned in the plating chamber. The plating chamber may include a rotor and a vessel. The electroplating systems may include at least one of baffle positioned in the plating chamber. The at least one baffle may define a plurality of slots. The at least one baffle may be configured to limit or prevent fluid from splashing the rotor or the plating chamber during operation of the plating chamber.

Abstract: The present disclosure relates to a method for growing III-V compound semiconductors on silicon-on-insulators. Starting from {111}-oriented Si seed surfaces between a buried oxide layer and a patterned mask layer, the III-V compound semiconductor is grown within lateral trenches by metal organic chemical vapor deposition such that the non-defective portion of the III-V compound semiconductor formed on the buried oxide layer is substantially free of crystalline defects and has high crystalline quality.

Abstract: A low temperature deposited (400° C. or less) dielectric passivation layer is formed on physically exposed surfaces of a material stack including a multilayered magnetic tunnel junction (MTJ) pillar and a top electrode. A laser anneal is then performed to improve the physical and chemical properties of the low temperature deposited dielectric passivation layer, without negatively impacting the multilayered MTJ pillar.

Abstract: The transistor includes a first gate electrode, a first insulating film over the first gate electrode, an oxide semiconductor film over the first insulating film, a source electrode over the oxide semiconductor film, a drain electrode over the oxide semiconductor film, a second insulating film over the oxide semiconductor film, the source electrode, and the drain electrode, and a second gate electrode over the second insulating film. The first insulating film includes a first opening. A connection electrode electrically connected to the first gate electrode through the first opening is formed over the first insulating film. The second insulating film includes a second opening that reaches the connection electrode. The second gate electrode includes an oxide conductive film and a metal film over the oxide conductive film. The connection electrode and the second gate electrode are electrically connected to each other through the metal film.

Abstract: Provided is a treatment liquid for a semiconductor with ruthenium, containing a hypobromite ion. Also provided is a treatment liquid for a semiconductor with ruthenium, containing at least a bromine-containing compound, an oxidizing agent, a basic compound, and water which are added and mixed, wherein the liquid has the bromine-containing compound added in an amount of 0.01 mass % or more and less than 2 mass % as a bromine element content with respect to the total mass of the liquid, has the oxidizing agent added in an amount of 0.1 mass % or more and 10 mass % or less with respect to the total mass, and has a pH of 8 or more and 14 or less. Further provided is a method of producing a treatment liquid for a semiconductor with ruthenium, including a step of mixing a bromine-containing compound with a solution containing a hypochlorous acid compound and a basic compound.

Abstract: The present application provides a programmable memory device. The programmable memory device includes: an access transistor, comprising an active region formed in a substrate and a gate structure formed on the substrate, wherein the active region has a linear top view shape, the gate structure has a first portion and a second portion, the first portion is intersected with a section of the active region away from end portions of the active region, and the second portion is laterally spaced apart from the active region; and a capacitor, using a portion of the active region as a terminal, and further comprising an electrode and a dielectric layer, wherein the electrode is disposed on the portion of the active region and spaced apart from the gate structure, and at least a portion of the dielectric layer is sandwiched between the electrode and the portion of the active region.

Abstract: A method for fabricating an integrated circuit device is disclosed. A substrate is provided and an integrated circuit area is formed on the substrate. The integrated circuit area includes a dielectric stack. A seal ring is formed in the dielectric stack and around a periphery of the integrated circuit area. A trench is formed around the seal ring and exposing a sidewall of the dielectric stack. The trench is formed within a scribe line. A moisture blocking layer is formed on the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.

Abstract: A semiconductor device according to the present embedment includes a substrate having a first region provided with a semiconductor element and a second region provided from the first region to an end. A material film is provided above the first and second regions. A first metal film is provided on the material film in the second region or on the material film between the first region and the second region. A trench, which caves in toward the substrate from a surface of the material film in the first region and from a surface of the material film under the first metal film, is provided in the material film between the first metal film and the first region.

Abstract: A word line layout includes a substrate, a first word line group, a second word line group, and an I-shaped third word line. The first word line group is disposed on the substrate and includes a plurality of L-shaped first word lines, and each of the first word lines has a first segment and a second segment connected to each other. The second word line group is disposed on the substrate and includes a plurality of L-shaped second word lines, and each of the second word lines has a first segment and a second segment connected to each other. The first word line group and the second word line group are arranged in juxtaposition and symmetric to each other. The I-shaped third word line is disposed on the outer side of the first word line group and the second word line group.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric layer, and a vertical stack of memory elements located at levels of the electrically conductive layers between a respective vertically neighboring pair of the insulating layers. Each of the memory elements includes a first memory material portion, and a second memory material portion that is vertically spaced from and is electrically isolated from the first memory material portion by at least one blocking dielectric material portion.

Abstract: A display panel includes a base substrate, a pixel including a thin film transistor and a display element, a first signal line connected to the pixel, and a second signal line disposed on a layer different from the first signal line. At least one of the first signal line and the second signal line includes a lower layer including a conductive material and an upper layer disposed on the lower layer and including a conductive material. The upper layer has an etch selectivity in a range equal to or greater than about 0.5 and equal to or smaller than about 3 with respect to the lower layer.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes forming a gate structure over the substrate. The gate structure has a first sidewall. The method includes forming a spacer element over the first sidewall of the gate structure. The method includes forming a source/drain portion adjacent to the spacer element and the gate structure. The source/drain portion has a first top surface. The method includes depositing an etch stop layer over the first top surface of the source/drain portion. The etch stop layer is made of nitride. The method includes forming a dielectric layer over the etch stop layer. The dielectric layer has a second sidewall and a bottom surface, the etch stop layer is in direct contact with the bottom surface, and the spacer element is in direct contact with the second sidewall.

Abstract: An Nblock layer is deposited onto a semiconductor substrate that includes metal deposits. A titanium nitride (TiN) layer is deposited directly onto the Nblock layer; an oxide layer is deposited directly onto the TiN layer; and a via hole is formed through the oxide and TiN layer to contact bottom interconnect. The via hole is aligned to one of the metal deposits in the substrate.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first source/drain structure and a second source/drain structure in a substrate. The method includes forming a first dielectric layer over the first source/drain structure, the second source/drain structure, and the substrate. The method includes forming a gate electrode in the first trench. The method includes removing the first dielectric layer. The method includes forming a first conductive strip structure over the first source/drain structure and the substrate. The method includes partially removing the first conductive strip structure to form a second trench in the first conductive strip structure. The method includes forming a second dielectric layer in the second trench.

Abstract: A method for processing a semiconductor device in accordance with various embodiments may include: depositing a first metallization material over a semiconductor body; performing a heating process so as to form at least one region in the semiconductor body including a eutectic of the first metallization material and material of the semiconductor body; and depositing a second metallization material over the semiconductor body so as to contact the semiconductor body via the at least one region in the semiconductor body.

Abstract: An Nblock layer is deposited onto a semiconductor substrate that includes metal deposits. A titanium nitride (TiN) layer is deposited directly onto the Nblock layer; an oxide layer is deposited directly onto the TiN layer; and a via hole is formed through the oxide and TiN layer to contact bottom interconnect. The via hole is aligned to one of the metal deposits in the substrate.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate having a first top surface, and an interconnection line over the first top surface of the substrate. The interconnection line has a sidewall. The semiconductor device structure also includes a first spacer over the sidewall of the interconnection line. The first spacer has a first concave surface which concaves towards the sidewall of the interconnection line. The semiconductor device structure further includes a dielectric layer covering the substrate, the interconnection line and the first spacer.

Abstract: According to one embodiment, the semiconductor body of the first portion includes a first semiconductor part and a second semiconductor part. The first semiconductor part extends in the stacking direction. The second semiconductor part is provided between the first semiconductor part and the first electrode layer, and has an end located closer to the first electrode layer side than the first semiconductor part. The first insulating film of the second portion includes a first insulating part and a second insulating part. The first insulating part extends in the stacking direction. The second insulating part is provided between the first insulating part and the second electrode layer, and has an end located closer to the second electrode layer side than the first insulating part.

Abstract: Example embodiments of inventive concepts provide a method for inspecting and/or observing photoresist patterns. The inspecting and/or observing methods may include forming at least an anti-reflective layer on a substrate, forming a fluorescent photoresist pattern on the anti-reflective layer, the fluorescent photoresist pattern having fluorescence, and observing and/or inspecting a shape of the fluorescent photoresist pattern using a fluorescence microscope.

Abstract: A process for generating a compact alumina passivation layer on an aluminum component includes rinsing the component in deionized water for at least one minute, drying it for at least one minute, and exposing it to concentrated nitric acid, at a temperature below 10° C., for one to 30 minutes. The process also includes rinsing the component in deionized water for at least one minute, drying it for at least one minute, and exposing it to NH4OH for one second to one minute. The process further includes rinsing the component in deionized water for at least one minute and drying it for at least one minute. A component for use in a plasma processing system includes an aluminum component coated with an AlxOy film having a thickness of 4 to 8 nm and a surface roughness less than 0.05 ?m greater than a surface roughness of the component without the AlxOy film.

Abstract: Methods and apparatus entailing an interconnect structure comprising interconnect features disposed in dielectric material over a substrate. Each interconnect feature comprises an interconnect member and a via extending between the interconnect member and a conductive member formed within the dielectric material. A through-silicon-via (TSV) structure is formed laterally offset from the interconnect structure by forming a first portion of the TSV structure with a first conductive material and forming a second portion of the TSV structure with a second conductive material. Forming the second portion of the TSV structure occurs substantially simultaneously with forming one of the interconnect features.

Abstract: A method of forming a metal layer may include forming an opening in a substrate; forming a liner over sidewalls of the opening; filling the opening with a first metal; etching a top surface of the first metal to form a recessed top surface below a top surface of the substrate; and exposing the recessed top surface of the first metal to a solution, the solution containing a second metal different from the first metal, the exposing causing the recessed top surface of the first metal to attract the second metal to form a cap layer over the recessed top surface of the first metal.

Abstract: A stack including an alternating plurality of first material layers and second material layers is provided. A memory opening is formed and at least a contiguous semiconductor material portion including a semiconductor channel is formed therein. The contiguous semiconductor material portion includes an amorphous or polycrystalline semiconductor material. A metallic material portion is provided at a bottom surface of the semiconductor channel, at a top surface of the semiconductor channel, or on portions of an outer sidewall surface of the semiconductor channel. An anneal is performed to induce diffusion of a metal from the metallic material portion through the semiconductor channel, thereby inducing conversion of the amorphous or polycrystalline semiconductor material into a crystalline semiconductor material. The crystalline semiconductor material has a relatively large grain size due to the catalytic crystallization process, and can provide enhanced charge carrier mobility.

Abstract: Radiation detectors and methods of fabricating radiation detectors are provided. One method includes mechanically polishing at least a first surface of a semiconductor wafer using a polishing sequence including a plurality of polishing steps, wherein a last polishing step of the polishing sequence includes polishing with a slurry having a grain size smaller than about 0.1 ?m to create a polished first surface. The method also includes applying (i) an encapsulation layer on a top of the polished first surface to seal the polished first surface and (ii) a photoresist layer on top of the encapsulation layer on the polished first surface. The method further includes creating undercuts of the encapsulation layer under the photoresist layer. The method additionally includes partially etching the polished first surface of the semiconductor via the openings in the photoresist layer and in the encapsulation layer to partially etch the semiconductor creating etched regions.

Abstract: Embodiments of the present invention include diffusion barriers, methods for forming the barriers, and semiconductor devices utilizing the barriers. The diffusion barrier comprises a self-assembled monolayer (SAM) on a semiconductor substrate, where one surface of the SAM is disposed in contact with and covalently bonded to the semiconductor substrate, and one surface of the monolayer is disposed in contact with and covalently bonded to a metal layer. In some embodiments, the barrier comprises an assembly of one or more monomeric subunits of the following structure: Si—(CnHy)-(LM)m where n is from 1 to 20, y is from 2n?2 to 2n, m is 1 to 3, L is a Group VI element, and M is a metal, such as copper. In some embodiments, (CnHy) can be branched, crosslinked, or cyclic.

Abstract: This disclosure is directed to a method of forming a gate pattern and a semiconductor device. The method comprises: providing a plurality of stacked structures which are parallel to each other and extend continuously in a first direction, and which are composed of a gate material bar and an etching barrier bar thereon; leaving second resist regions between gaps to be formed adjacent to each other across gate bars by a second photolithography process; selectively removing the etching barrier bars by a second etching process; forming a third resist layer having a plurality of openings parallel to each other and extending continuously in a second direction substantially perpendicular to the first direction by a third photolithography process; and forming the gate pattern by a third etching process. The method is capable of having a larger photolithography process window and better controlling the shape and size of a gate pattern.

Abstract: A blocking semiconductor layer minimizes penetration of implant species into a semiconductor layer beneath the blocking semiconductor layer. The blocking semiconductor layer may have grains with relatively fine or small grain sizes and/or may have a dopant in a relatively low concentration to minimize penetration of implant species into the semiconductor layer beneath the blocking semiconductor layer.

Abstract: Non-planar semiconductor devices are provided that include at least one semiconductor nanowire suspended above a semiconductor oxide layer that is present on a first portion of a bulk semiconductor substrate. An end segment of the at least one semiconductor nanowire is attached to a first semiconductor pad region and another end segment of the at least one semiconductor nanowire is attached to a second semiconductor pad region. The first and second pad regions are located above and are in direct contact with a second portion of the bulk semiconductor substrate which is vertically offsets from the first portion. The structure further includes a gate surrounding a central portion of the at least one semiconductor nanowire, a source region located on a first side of the gate, and a drain region located on a second side of the gate which is opposite the first side of the gate.

Abstract: A method for forming a nanowire field effect transistor (FET) device, the method includes forming a suspended nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, removing exposed portions of the nanowire left unprotected by the spacer structure, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region.

Abstract: An etchant includes about 50% by weight to about 70% by weight of phosphoric acid, about 1% by weight to about 5% by weight of nitric acid, about 10% by weight to about 20% by weight of acetic acid, about 0.1% by weight to about 2% by weight of a corrosion inhibition agent including an azole-based compound and a remainder of water.

Abstract: A light emitting element having a recess-protrusion structure on a substrate is provided. A semiconductor light emitting element 100 has a light emitting structure of a semiconductor 20 on a first main surface of a substrate 10. The first main surface of the substrate 10 has substrate protrusion portion 11, the bottom surface 14 of each protrusion is wider than the top surface 13 thereof in a cross-section, or the top surface 13 is included in the bottom surface 14 in a top view of the substrate. The bottom surface 14 has an approximately polygonal shape, and the top surface 13 has an approximately circular or polygonal shape with more sides than that of the bottom surface 14.

Abstract: An etchant according to exemplary embodiments of the present invention includes about 0.5 wt % to about 20 wt % of persulfate, about 0.01 wt % to about 2 wt % of a fluorine compound, about 1 wt % to about 10 wt % of inorganic acid, about 0.5 wt % to about 5 wt % of a cyclic amine compound, about 0.1 wt % to about 5 wt % of a chlorine compound, about 0.05 wt % to about 3 wt % of copper salt, about 0.1 wt % to about 10 wt % of organic acid or organic acid salt, and water.

Abstract: A method of producing a transistor includes providing a substrate including in order a first electrically conductive material layer and a second electrically conductive material layer. A resist material layer is deposited over the second electrically conductive material layer. The resist material layer is patterned to expose a portion of the second electrically conductive material layer. Some of the second electrically conductive material layer is removed to create a reentrant profile in the second electrically conductive material layer and to expose a portion of the first electrically conductive material layer. The second electrically conductive material layer is caused to overhang the first electrically conductive material layer by removing some of the first electrically conductive material layer.

Abstract: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).

Abstract: The present invention relates to a method for manufacturing an acceleration sensor. In the method, thin SOI-wafer structures are used, in which grooves are etched, the walls of which are oxidized. A thick layer of electrode material, covering all other material, is grown on top of the structures, after which the surface is ground and polished chemo-mechanically, thin release holes are etched in the structure, structural patterns are formed, and finally etching using a hydrofluoric acid solution is performed to release the structures intended to move and to open a capacitive gap.

Abstract: A method of forming a semiconductor device includes forming a transistor gate stack over a substrate having an active area and a shallow trench isolation (STI) region. First sidewall spacers are formed on the transistor gate stack, and an isotropic etch process is applied to isotropically remove an excess portion of a metal layer included within the transistor gate stack, the excess portion left unprotected by the first sidewall spacers. Second sidewall spacers are formed on the transistor gate stack, the second sidewall spacers completely encapsulating the metal layer of the transistor gate stack.

Abstract: In one exemplary embodiment of the invention, a semiconductor structure includes: a substrate; and a plurality of devices at least partially overlying the substrate, where the plurality of devices include a first device coupled to a second device via a first raised source/drain having a first length, where the first device is further coupled to a second raised source/drain having a second length, where the first device comprises a transistor, where the first raised source/drain and the second raised source/drain at least partially overly the substrate, where the second raised source/drain comprises a terminal electrical contact, where the second length is greater than the first length.

Abstract: Various semiconductor devices and methods of testing such devices are disclosed. In one aspect, a method of manufacturing is provided that includes forming a bore from a backside of a semiconductor chip through a buried insulating layer and to a semiconductor device layer of the semiconductor chip. A conductor structure is formed in the bore to establish an electrically conductive pathway between the semiconductor device layer and the conductor structure. The conductor structure may provide a diagnostic pathway.

Abstract: A method of removing silicon nitride over a semiconductor surface for forming shallow junctions. Sidewall spacers are formed along sidewalls of a gate stack that together define lightly doped drain (LDD) regions or source/drain (S/D) regions. At least one of the sidewall spacers, LDD regions and S/D regions include an exposed silicon nitride layer. The LDD or S/D regions include a protective dielectric layer formed directly on the semiconductor surface. Ion implanting implants the LDD regions or S/D regions using the sidewall spacers as implant masks. The exposed silicon nitride layer is selectively removed, wherein the protective dielectric layer when the sidewall spacers include the exposed silicon nitride layer, or a replacement protective dielectric layer formed directly on the semiconductor surface after ion implanting when the LDD or S/D regions include the exposed silicon nitride layer, protects the LDD or S/D regions from dopant loss due to etching during selectively removing.

Abstract: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).

Abstract: Methods of forming a top oxide around a charge storage material layer of a memory cell and methods of improving quality of a top oxide around a charge storage material layer of a memory cell are provided. The method can involve providing a charge storage layer on a semiconductor substrate, a nitride layer on the charge storage layer, and a first poly layer on the nitride layer, and converting at least a portion of the nitride layer to a top oxide. By converting at least a portion of a nitride layer to a top oxide layer, the quality of the resultant top oxide layer can be improved.

Abstract: The microelectronic device interconnects are fabricated by a process that utilizes a silicon-based interlayer dielectric material layer, such as carbon-doped oxide, and a chemical mixture selective to materials used in the formation of the interconnects, including, but not limited to, copper, cobalt, tantalum, and/or tantalum nitride, to remove the interlayer dielectric material layer between adjacent interconnects thereby forming air gaps therebetween.

Abstract: A method for manufacturing a liquid crystal display includes simultaneously forming a gate electrode and a gate bus line on a transparent dielectric substrate, simultaneously forming a channel layer, an ohmic contact layer, and source/drain electrodes by forming a gate insulation film, an amorphous silicon film, a doped amorphous silicon film, and a metal film on the transparent dielectric substrate on which the gate electrode and the gate bus line are formed and etching the metal film, the amorphous silicon film, and the doped amorphous silicon film, and forming a pixel electrode by forming a protective film and a transparent metal film on the transparent dielectric substrate upon which the source/drain electrodes are formed and finely etching the transparent metal film through a lift-off process using a stripper solution.

Abstract: A process for making a latching zip-mode actuated mono wafer MEMS switch especially suited to capacitance coupled signal switching of microwave radio frequency signals is disclosed. The single wafer fabrication process used for the switch employs sacrificial layers and liquid removal of these layers in order to also provide needed permanent physical protection for an ultra fragile switch moving arm member. Latched operation of the achieved MEMS switch without use of conventional holding electrodes or magnetic fields is also achieved. Fabrication of a single MEMS switch is disclosed however large or small arrays may be achieved. A liquid removal based fabrication process is disclosed.

Abstract: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).

Abstract: A latching zip-mode actuated mono wafer MEMS switch especially suited to capacitance coupled signal switching of microwave radio frequency signals is disclosed. The single wafer fabrication process used for the switch employs sacrificial layers and liquid removal of these layers in order to also provide needed permanent physical protection for an ultra fragile switch moving arm member. Latched operation of the achieved MEMS switch without use of conventional holding electrodes or magnetic fields is also achieved. Fabrication of a single MEMS switch is disclosed however large or small arrays may be achieved.