Abstract: The reliability of a porous Low-k film is improved. The mean diameter of first pores and second pores in an interlayer insulation film of a second fine layer including a porous Low-k film is set at 1.0 nm or more and less than 1.45 nm. This prevents the formation of a modified layer over the surface of the interlayer insulation film by process damages. Further, the formation of the moisture-containing modified layer is inhibited to prevent oxidation of a barrier film and a main conductor film forming respective wirings. This prevents deterioration of breakdown voltage between respective wirings. This prevents deterioration of the EM lifetime of wirings formed adjacent to the interlayer insulation film and the inter-wiring TDDB lifetime of the wirings.
Abstract: According to one embodiment, a method for manufacturing a semiconductor device, includes forming a mask film on a base material. The base material includes a first portion made of a first material and a second portion made of a second material. The mask film includes a third portion located immediately above the first portion and made of a third material and a fourth portion located immediately above the second portion and made of a fourth material. The mask film has an opening formed in both the third portion and the fourth portion. The method includes selectively removing the first portion and the second portion respectively by etching using the mask film as a mask under a condition such that etching rate of the fourth material is higher than that of the third material and etching rate of the first material is higher than that of the second material.
Abstract: A method of producing, at atmospheric pressure, an n-type semiconductive indium sulfide thin film on a substrate using an indium-containing precursor, hydrogen sulfide as a reactive gaseous precursor, and an inert carrier gas stream includes cyclically repeating first and second steps so as to produce an indium sulfide thin film of a desired thickness. The first method phase includes converting the indium-containing precursor to at least one of a dissolved and a gaseous phase, heating the substrate to a temperature in a range of 100° C. to 275° C., directing the indium containing precursor onto the substrate and supplying hydrogen sulfide to the indium-containing precursor in a mixing zone in an amount so as to provide an absolute concentration of hydrogen sulfide that is greater than zero and no greater than 1% by volume. The indium concentration of the indium-containing precursor is set so as to produce a compact In(OHx,Xy,Sz)3 film, where X=halide and x+y+2z=1 with z?0.
Type:
Grant
Filed:
March 14, 2009
Date of Patent:
March 27, 2012
Assignee:
Helmholtz-Zentrum Berlin fuer Materialien und Energie GmbH
Inventors:
Nicholas Allsop, Christian-Herbert Fischer, Sophie Gledhill, Martha Christina Lux-Steiner
Abstract: A method for fabricating a semiconductor device includes forming a plurality of plugs over a die region and an edge bead removal (EBR) region of a wafer, forming metal lines coupled to the plugs, removing the metal lines in the EBR region, forming an inter-layer dielectric layer over the wafer, and forming a plurality of contact holes that expose the metal lines by selectively etching the inter-layer dielectric layer through a dry etch process using a plasma etch device.
Type:
Application
Filed:
July 9, 2010
Publication date:
June 30, 2011
Inventors:
Hae-Jung Lee, Kang-Pok Lee, Kyeong-Hyo Lee
Abstract: In a method for forming a pattern of a semiconductor device, an ultra fine pattern is formed using a spacer patterning technology to overcome resolution limits of an exposer. A silicon-containing resist enhancement lithography assisted by a chemical shrink (RELACS) layer is formed with a spin-con-coating method in a track apparatus over a photoresist pattern. As a result, a cross-linking reaction is generated between the RELACS layer and the photoresist patterns to form the spacer, and the spacer is used as a mask in the patterning process.
Abstract: The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. There is provided a method of forming a strained channel transistor structure on a substrate, comprising the steps of: forming a source stressor recess comprising a deep source recess and a source extension recess; forming a drain stressor recess comprising a deep drain recess and a drain extension recess; and subsequently forming a source stressor in said source stressor recess and a drain stressor in said drain stressor recess. The deep source/drain and source/drain extension stressors are formed by an uninterrupted etch process and an uninterrupted epitaxy process.
Type:
Grant
Filed:
May 17, 2006
Date of Patent:
August 19, 2008
Assignees:
Chartered Semiconductor Manufacturing Ltd., International Business Machines Corporation
Inventors:
Yung Fu Chong, Kevin K. Dezfulian, Zhijiong Luo, Huilong Zhu