Physical Or Chemical Etching Of Layer, E.g., To Produce A Patterned Layer From Pre-deposited Extensive Layer (epo) Patents (Class 257/E21.305)
  • Patent number: 9577049
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a semiconductor layer over the substrate. The semiconductor layer includes a transition metal chalcogenide. The semiconductor device structure includes a source electrode and a drain electrode over and connected to the semiconductor layer and spaced apart from each other by a gap. The source electrode and the drain electrode are made of graphene.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: February 21, 2017
    Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan University
    Inventors: Shih-Yen Lin, Chong-Rong Wu, Chi-Wen Liu
  • Patent number: 9035418
    Abstract: A shallow trench isolation (STI) structure includes a top surface formed completely of silicon nitride. The top surface of the STI structure is coplanar with a top substrate surface or extends above the top substrate surface. The STI structures include further dielectric materials beneath the silicon nitride and an oxide liner and any portions that extend above the substrate surface are formed of silicon nitride.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: May 19, 2015
    Assignee: WAFERTECH, LLC
    Inventors: Daniel Piper, Franklin Chiang, Ganesh Yerubandi
  • Patent number: 8980752
    Abstract: A method of forming a plurality of spaced features includes forming sacrificial hardmask material over underlying material. The sacrificial hardmask material has at least two layers of different composition. Portions of the sacrificial hardmask material are removed to form a mask over the underlying material. Individual features of the mask have at least two layers of different composition, with one of the layers of each of the individual features having a tensile intrinsic stress of at least 400.0 MPa. The individual features have a total tensile intrinsic stress greater than 0.0 MPa. The mask is used while etching into the underlying material to form a plurality of spaced features comprising the underlying material. Other implementations are disclosed.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: March 17, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Farrell Good, Baosuo Zhou, Xiaolong Fang, Fatma Arzum Simsek-Ege
  • Patent number: 8980762
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a film having different filling properties dependent on space width above the patterning film to cover the first line patterns and the second line patterns to form the film on the first line patterns and on the first inter-line pattern space while making a cavity in the first inter-line pattern space and to form the film on at least a bottom portion of the second inter-line pattern space and a side wall of each of the second line patterns. The method includes performing etch-back of the film to remove the film on the first line patterns and on the first inter-line pattern space while causing the film to remain on at least the side wall of the second line patterns.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazunori Iida, Yuji Kobayashi
  • Patent number: 8969102
    Abstract: A method of testing a device includes setting a potential of a cap terminal of the device to a first voltage, setting a potential of a self test plate of the device to a testing voltage, and detecting a first displacement of a proof mass of the device when the cap terminal is set to the first voltage and the self test plate is set to the testing voltage. The method includes setting a potential of the cap terminal of the device to a second voltage, detecting a second displacement of the proof mass of the device when the cap terminal is set to the second voltage and the self test plate is set to the testing voltage, and comparing the first displacement and the second displacement to evaluate an electrical connection between the cap terminal and a cap of the device.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: March 3, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Peter S. Schultz
  • Patent number: 8946784
    Abstract: A backside illuminated image sensor having a photodiode and a first transistor in a sensor region and located in a first substrate, with the first transistor electrically coupled to the photodiode. The image sensor has logic circuits formed in a second substrate. The second substrate is stacked on the first substrate and the logic circuits are coupled to the first transistor through bonding pads, the bonding pads disposed outside of the sensor region.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ying Chen, Meng-Hsun Wan, Dun-Nian Yaung, Pao-Tung Chen, Jen-Cheng Liu
  • Patent number: 8853085
    Abstract: A method for defining a template for directed self-assembly (DSA) materials includes patterning a resist on a stack including an ARC and a mask formed over a hydrophilic layer. A pattern is formed by etching the ARC and the mask to form template lines which are trimmed to less than a minimum feature size (L). Hydrophobic spacers are formed on the template lines and include a fractional width of L. A neutral brush layer is grafted to the hydrophilic layer. A DSA material is deposited between the spacers and annealed to form material domains in a form of alternating lines of a first and a second material wherein the first material in contact with the spacers includes a width less than a width of the lines. A metal is added to the domains forming an etch resistant second material. The first material and the spacers are removed to form a DSA template pattern.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jassem A. Abdallah, Matthew E. Colburn, Steven J. Holmes, Chi-Chun Liu
  • Patent number: 8815740
    Abstract: A method for forming a pattern according to an embodiment, includes forming above a first film film patterns of a second film; forming film patterns of the first film by etching the first film using the film patterns of the second film as a mask; converting the film patterns of the second film into film patterns whose width are narrower than the film patterns of the first film by performing a slimming process; forming film patterns of a third film on both sidewalls of the film patterns of the first film and the film patterns of the second film after the slimming process; and etching the first film using the film patterns of the third film as a mask after the film patterns of the second film being removed.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazunori Horiguchi, Takashi Ohashi
  • Patent number: 8810030
    Abstract: A MEMS device (20) with stress isolation includes elements (28, 30, 32) formed in a first structural layer (24) and elements (68, 70) formed in a second structural layer (26), with the layer (26) being spaced apart from the first structural layer (24). Fabrication methodology (80) entails forming (92, 94, 104) junctions (72, 74) between the layers (24, 26). The junctions (72, 74) connect corresponding elements (30, 32) of the first layer (24) with elements (68, 70) of the second layer (26). The fabrication methodology (80) further entails releasing the structural layers (24, 26) from an underlying substrate (22) so that all of the elements (30, 32, 68, 70) are suspended above the substrate (22) of the MEMS device (20), wherein attachment of the elements (30, 32, 68, 70) with the substrate (22) occurs only at a central area (46) of the substrate (22).
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: August 19, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Aaron A. Geisberger
  • Patent number: 8803296
    Abstract: A device has a microelectromechanical system (MEMS) component with at least one surface and a coating disposed on at least a portion of the surface. The coating has a compound of the formula M(CnF2n+1Or), wherein M is a polar head group and wherein n?2r. The value of n may range from 2 to about 20, and the value of r may range from 1 to about 10. The value of n plus r may range from 3 to about 30, and a ratio of n:r may have a value of about 2:1 to about 20:1.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: August 12, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: William Robert Morrison, Mark Christopher Fisher, Murali Hanabe, Ganapathy Subramaniam Sivakumar, Simon Joshua Jacobs
  • Patent number: 8716133
    Abstract: A three photomask image transfer method. The method includes using a first photomask, defining a set of mandrels on a hardmask layer on a substrate; forming sidewall spacers on sidewalls of the mandrels, the sidewall spacers spaced apart; removing the set of mandrels; using a second photomask, removing regions of the sidewall spacers forming trimmed sidewall spacers and defining a pattern of first features; forming a pattern transfer layer on the trimmed sidewall spacers and the hardmask layer not covered by the trimmed sidewall spacers; using a third photomask, defining a pattern of second features in the transfer layer, at least one of the second features abutting at least one feature of the pattern of first features; and simultaneously transferring the pattern of first features and the pattern of second features into the hardmask layer thereby forming a patterned hardmask layer.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shyng-Tsong Chen, Ryan O. Jung, Neal V. Lafferty, Yunpeng Yin
  • Patent number: 8647981
    Abstract: Some embodiments include methods of forming a pattern. First lines are formed over a first material, and second lines are formed over the first lines. The first and second lines form a crosshatch pattern. The first openings are extended through the first material. Portions of the first lines that are not covered by the second lines are removed to pattern the first lines into segments. The second lines are removed to uncover the segments. Masking material is formed between the segments. The segments are removed to form second openings that extend through the masking material to the first material. The second openings are extended through the first material. The masking material is removed to leave a patterned mask comprising the first material having the first and second openings therein. In some embodiments, spacers may be formed along the first and second lines to narrow the openings in the crosshatch pattern.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: February 11, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Vishal Sipani
  • Patent number: 8592321
    Abstract: A method for fabricating an aperture is disclosed. The method includes the steps of: forming a hard mask containing carbon on a surface of a semiconductor substrate; and using a non-oxygen element containing gas to perform a first etching process for forming a first aperture in the hard mask.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: November 26, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Feng-Yi Chang, Yi-Po Lin, Jiunn-Hsiung Liao, Shang-Yuan Tsai, Chih-Wen Feng, Shui-Yen Lu, Ching-Pin Hsu
  • Patent number: 8569080
    Abstract: A method of packaging a light emitting diode comprising: providing a flexible substrate with a heat-conducting layer, an insulating layer covering on a surface of the heat-conducting layer and an electrically conductive layer positioned on the insulating layer; etching the conductive layer to form a gap in the conductive layer and expose a part of the insulating layer, the conductive layer being separated by the gap into a first electrode and a second electrode isolated from each other; stamping the flexible substrate with a mold at the position of the gap to form a recess in the flexible substrate; positioning a light emitting element on the conductive layer and electrically connecting the light emitting element to the conductive layer; and forming an encapsulation to cover the light emitting element.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: October 29, 2013
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Li-Hsiang Chen, Hsin-Chiang Lin, Pin-Chuan Chen
  • Patent number: 8569180
    Abstract: The present invention is related shielding integrated devices using CMOS fabrication techniques to form an encapsulation with cavity. The integrated circuits are completed first using standard IC processes. A wafer-level hermetic encapsulation is applied to form a cavity above the sensitive portion of the circuits using IC-foundry compatible processes. The encapsulation and cavity provide a hermetic inert environment that shields the sensitive circuits from EM interference, noise, moisture, gas, and corrosion from the outside environment.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: October 29, 2013
    Assignee: mCube Inc.
    Inventor: Xiao (Charles) Yang
  • Patent number: 8546265
    Abstract: A method for manufacturing a silicon structure according to the present invention includes, in a so-called dry-etching process wherein gas-switching is employed, the steps of: etching a portion in the silicon region at a highest etching rate under a high-rate etching condition such that the portion does not reach the etch stop layer; subsequently etching under a transition etching condition in which an etching rate is decreased with time from the highest etching rate in the high-rate etching condition; and thereafter, etching the silicon region under a low-rate etching condition of a lowest etching rate in the transition etching condition.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: October 1, 2013
    Assignee: SPP Technologies Co., Ltd.
    Inventors: Yoshiyuki Nozawa, Takashi Yamamoto
  • Patent number: 8530327
    Abstract: A shallow trench isolation (STI) structure and methods for forming the same provide an STI structure with a top surface formed completely of silicon nitride. The methods for forming the STI structures provide for at least one nitride deposition step followed by a further nitride deposition step to re-fill divots that occur along the upper portions of the trench sidewalls.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: September 10, 2013
    Assignee: Wafertech, LLC
    Inventors: Daniel Piper, Franklin Chiang, Ganesh Yerubandi
  • Patent number: 8492278
    Abstract: A method of forming a plurality of spaced features includes forming sacrificial hardmask material over underlying material. The sacrificial hardmask material has at least two layers of different composition. Portions of the sacrificial hardmask material are removed to form a mask over the underlying material. Individual features of the mask have at least two layers of different composition, with one of the layers of each of the individual features having a tensile intrinsic stress of at least 400.0 MPa. The individual features have a total tensile intrinsic stress greater than 0.0 MPa. The mask is used while etching into the underlying material to form a plurality of spaced features comprising the underlying material. Other implementations are disclosed.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: July 23, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Farrell Good, Baosuo Zhou, Xiaolong Fang, Fatma Arzum Simsek-Ege
  • Patent number: 8450172
    Abstract: In sophisticated semiconductor devices, non-insulating materials with extremely high internal stress level may be used in the contact level in order to enhance performance of circuit elements, such as field effect transistors, wherein the non-insulating material may be appropriately “encapsulated” by dielectric material. Consequently, a desired high strain level may be obtained on the basis of a reduced layer thickness, while still providing the insulating characteristics required in the contact level.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: May 28, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ralf Richter, Hartmut Ruelke, Joerg Hohage
  • Patent number: 8399894
    Abstract: A wiring electrode is provided on a mount substrate. A light emitting element is provided on the wiring electrode to connect electrically with the wiring electrode and is configured to emit a blue to ultraviolet light. A reflective film is provided above the light emitting element to cover the light emitting element so that a space is interposed between the reflective film and the light emitting element. The reflective film is capable of transmitting the blue to ultraviolet light. A fluorescent material layer is provided above the light emitting element to cover the light emitting element so that the reflective film is located between the fluorescent material layer and the light emitting element. A light from the fluorescent material layer is reflected by the reflective film.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: March 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideto Furuyama
  • Patent number: 8362553
    Abstract: A method includes forming elongate structures on a first substrate, such that the material composition of each elongate structure varies along its length so as to define first and second physically different sections in the elongate structures. First and second physically different devices are then defined in the elongate structures. Alternatively, the first and second physically different sections may be defined in the elongate structures after they have been fabricated. The elongate structures may be encapsulated and transferred to a second substrate. The invention provides an improved method for the formation of a circuit structure that requires first and second physically different devices to be provided on a common substrate. In particular, only one transfer step is necessary.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: January 29, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Thomas Heinz-Helmut Altebaeumer, Stephen Day, Jonathan Heffernan
  • Patent number: 8338282
    Abstract: A method for encapsulating a micro component positioned on and/or in a substrate, including: depositing at least one sacrificial material covering the micro component, making a cap covering the sacrificial material, removing the sacrificial material via at least one opening formed through the cap and forming a cavity in which the micro component is positioned, depositing, at least on the cap, at least one layer of plugging material that plugs the at least one opening, and performing a localized deposition of at least one portion of mechanically reinforcing material of the cap, covering at least the cap, wherein the mechanically reinforcing material is not subsequently etched.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: December 25, 2012
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Jean-Louis Pornin, Charlotte Gillot
  • Patent number: 8338291
    Abstract: A method of producing a transistor includes providing a substrate including in order a first electrically conductive material layer and a second electrically conductive material layer. A resist material layer is deposited over the second electrically conductive material layer. The resist material layer is patterned to expose a portion of the second electrically conductive material layer. Some of the second electrically conductive material layer is removed to create a reentrant profile in the second electrically conductive material layer and to expose a portion of the first electrically conductive material layer. The second electrically conductive material layer is caused to overhang the first electrically conductive material layer by removing some of the first electrically conductive material layer.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: December 25, 2012
    Assignee: Eastman Kodak Company
    Inventors: Lee W. Tutt, Shelby F. Nelson
  • Patent number: 8298954
    Abstract: A cap material layer is deposited on a metal nitride layer. An antireflective coating (ARC) layer, an organic planarizing layer (OPL), and patterned line structures are formed upon the cap material layer. The pattern in the patterned line structures is transferred into the ARC layer and the OPL. Exposed portions of the cap material layer are etched simultaneously with the etch removal of the patterned line structures and the ARC layer. The OPL is employed to etch the metal nitride layer. The patterned cap material layer located over the metal nitride layer protects the top surface of the metal nitride layer, and enables high fidelity reproduction of the pattern in the metal nitride layer without pattern distortion. The metal nitride layer is subsequently employed as an etch mask for pattern transfer into an underlying layer.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: John C. Arnold, Sean D. Burns, Matthew E. Colburn, David V. Horak, Yunpeng Yin
  • Patent number: 8217476
    Abstract: A method for manufacturing a micromechanical component and the micromechanical component produced thereby. This component is preferably a diaphragm or a diaphragm layer which is independently produced for the purpose of subsequent assembly with other components.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: July 10, 2012
    Assignee: Robert Bosch GmbH
    Inventors: Karl-Heinz Kraft, Simon Armbruster, Arnim Hoechst
  • Patent number: 8168508
    Abstract: A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: May 1, 2012
    Assignee: Intel Corporation
    Inventors: Benjamin Chu-Kung, Uday Shah, Ravi Pillarisetty, Been-Yih Jin, Marko Radosavljevic, Willy Rachmady
  • Patent number: 8168520
    Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention forms at least one pair of gate electrodes having end portions opposed to each other across a gap.
    Type: Grant
    Filed: May 21, 2009
    Date of Patent: May 1, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Gaku Sudo
  • Patent number: 8143082
    Abstract: A single integrated wafer package includes a micro electromechanical system (MEMS) wafer, an active device wafer, and a seal ring. The MEMS wafer has a first surface and includes at least one MEMS component on its first surface. The active device wafer has a first surface and includes an active device circuit on its first surface. The seal ring is adjacent the first surface of the MEMS wafer such that a seal is formed about the MEMS component. An external contact is provided on the wafer package. The external contact is accessible externally to the wafer package and is electrically coupled to the active device circuit of the active device wafer.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: March 27, 2012
    Assignee: Avago Technologies Wireless IP (Singapore) Pte. Ltd.
    Inventors: Thomas E. Dungan, Ronald S. Fazzio
  • Publication number: 20110269309
    Abstract: Provided are a photoresist composition having superior adhesion to an etch target film, a method of forming a pattern by using the photoresist composition, and a method of manufacturing a thin-film transistor (TFT) substrate. The photoresist composition includes an alkali-soluble resin; a photosensitive compound; a solvent; and 0.01 to 0.1 parts by weight of a compound represented by Formula 1: wherein R is one of hydrogen, an alkyl having 1 to 10 carbon atoms, a cycloalkyl having 4 to 8 carbon atoms, and a phenyl group.
    Type: Application
    Filed: December 29, 2010
    Publication date: November 3, 2011
    Applicants: DONGWOO FINE-CHEM CO., LTD, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Pil-Soon HONG, Gwui-Hyun PARK, Jin-Ho JU, Jean-Ho SONG, Sang-Tae KIM, Seong-Hyeon KIM, Won-Young CHANG, Jong-Heum YOON, Eun-Sang LEE, Min-Ju IM
  • Publication number: 20110248412
    Abstract: A chip identification for organic laminate packaging and methods of manufacture is provided. The method includes forming a material on a wafer which comprises a plurality of chips. The method further includes modifying the material to provide a unique identification for each of the plurality of chips on the wafer. The organic laminate structure includes a chip with a device and a material placed on the chip which is modified to have a unique identification mark for the chip.
    Type: Application
    Filed: April 8, 2010
    Publication date: October 13, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Albert J. BANACH, Timothy H. DAUBENSPECK, Wolfgang SAUTER
  • Publication number: 20110250745
    Abstract: Some embodiments include methods of forming patterns in substrates by utilizing block copolymer assemblies as patterning materials. A block copolymer assembly may be formed over a substrate, with the assembly having first and second subunits arranged in a pattern of two or more domains. Metal may be selectively coupled to the first subunits relative to the second subunits to form a pattern of metal-containing regions and non-metal-containing regions. At least some of the block copolymer may be removed to form a patterned mask corresponding to the metal-containing regions. A pattern defined by the patterned mask may be transferred into the substrate with one or more etches. In some embodiments, the patterning may be utilized to form integrated circuitry, such as, for example, gatelines.
    Type: Application
    Filed: April 7, 2010
    Publication date: October 13, 2011
    Inventors: Dan Millward, Scott Sills
  • Publication number: 20110223699
    Abstract: A semiconductor device having good TFT characteristics is realized. By using a high purity target as a target, using a single gas, argon (Ar), as a sputtering gas, setting the substrate temperature equal to or less than 300° C., and setting the sputtering gas pressure from 1.0 Pa to 3.0 Pa, the film stress of a film is made from ?1×1010 dyn/cm2 to 1×1010 dyn/cm2. By thus using a conducting film in which the amount of sodium contained within the film is equal to or less than 0.3 ppm, preferably equal to or less than 0.1 ppm, and having a low electrical resistivity (equal to or less than 40 ??·cm), as a gate wiring material and a material for other wirings of a TFT, the operating performance and the reliability of a semiconductor device provided with the TFT can be increased.
    Type: Application
    Filed: March 8, 2011
    Publication date: September 15, 2011
    Inventors: Toru Takayama, Keiji Sato, Shunpei Yamazaki
  • Patent number: 8017956
    Abstract: A wiring electrode is provided on a mount substrate. A light emitting element is provided on the wiring electrode to connect electrically with the wiring electrode and is configured to emit a blue to ultraviolet light. A reflective film is provided above the light emitting element to cover the light emitting element so that a space is interposed between the reflective film and the light emitting element. The reflective film is capable of transmitting the blue to ultraviolet light. A fluorescent material layer is provided above the light emitting element to cover the light emitting element so that the reflective film is located between the fluorescent material layer and the light emitting element. A light from the fluorescent material layer is reflected by the reflective film.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: September 13, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideto Furuyama
  • Patent number: 8012811
    Abstract: A feature is formed in an integrated circuit by providing one or more layers to be patterned, providing a first layer overlying the one or more layers to be patterned, and providing a second layer overlying the first layer. The second layer is patterned to form a raised feature with one or more sidewalls. Subsequently, the first layer is processed such that components of the first layer deposit on the one or more sidewalls of the raised feature to form a mask. The mask is used to pattern the one or more layers to be patterned.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: September 6, 2011
    Assignee: International Business Machines Corporation
    Inventors: Kuan-Neng Chen, John Christopher Arnold, Niranjana Ruiz
  • Patent number: 8013330
    Abstract: Disclosed are a compound for an organic electroluminescent device (organic EL device) which is improved in luminous efficiency, fully secured of driving stability, and of simple constitution and an organic EL device using said compound. The compound for an organic EL device has two indolocarbazole skeletons each of which is bonded to an aromatic group or two skeletons similar thereto. The organic EL device comprises a light-emitting layer disposed between an anode and a cathode piled one upon another on a substrate and said light-emitting layer comprises a phosphorescent dopant and the aforementioned compound for an organic EL device as a host material.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: September 6, 2011
    Assignee: Nippon Steel Chemical Co., Ltd
    Inventors: Masaki Komori, Toshihiro Yamamoto, Takahiro Kai, Katsuhide Noguchi, Hiroshi Miyazaki
  • Patent number: 8008657
    Abstract: Disclosed are an organic electroluminescent device (organic EL device) which is improved in luminous efficiency, fully secured of driving stability, and of simple constitution and a compound useful for the fabrication of said organic EL device. The compound for the organic EL device has an indolocarbazole structure or a structure similar thereto in the molecule wherein an aromatic group is bonded to the nitrogen atom in the indolocarbazole. The organic EL device has a light-emitting layer disposed between an anode and a cathode piled one upon another on a substrate and said light-emitting layer comprises a phosphorescent dopant and the aforementioned compound for an organic electroluminescent device as a host material.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: August 30, 2011
    Assignee: Nippon Steel Chemical Co., Ltd.
    Inventors: Takahiro Kai, Masaki Komori, Toshihiro Yamamoto, Katsuhide Noguchi, Hiroshi Miyazaki
  • Patent number: 8003539
    Abstract: A method for making a semiconductor device is provided which comprises (a) creating a data set (301) which defines a set of tiles for a polysilicon deposition process; (b) deriving a polysilicon deposition mask set (311) from the data set, wherein the polysilicon deposition mask set includes a plurality of polysilicon tiles (303); (c) deriving an epitaxial growth mask set (321) from the data set, wherein the epitaxial growth mask set includes a plurality of epitaxial tiles (305); and (d) using the polysilicon deposition mask set and the epitaxial growth mask set to make a semiconductor device (331); wherein the epitaxial growth mask set is derived from the data set by using at least a portion of the tile pattern defined in the data set for at least a portion of the tile pattern defined in the epitaxial deposition mask set.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: August 23, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Omar Zia, Ruiqi Tian, Edward O. Travis
  • Publication number: 20110189844
    Abstract: A method for encapsulating a micro component positioned on and/or in a substrate, including the following steps: depositing at least one sacrificial material covering the micro component, making a cap covering the sacrificial material, removing the sacrificial material via at least one opening formed through the cap, forming a cavity in which the micro component is positioned, depositing, on the cap, at least one layer of plugging material capable of plugging the opening, localized deposition of a portion of mechanically reinforcing material of the cap, covering at least the cap.
    Type: Application
    Filed: February 2, 2011
    Publication date: August 4, 2011
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE. ALT.
    Inventors: Jean-Louis PORNIN, Charlotte Gillot
  • Patent number: 7981772
    Abstract: A method is shown for fabricating nanostructures, and more particularly, to methods of fabricating silicon nanowires. The method of manufacturing a nanowire includes forming a sandwich structure of SiX material and material Si over a substrate and etching the sandwich structure to expose sidewalls of the Si material and the SiX material. The method further includes etching the SiX material to expose portions of the Si material and etching the exposed portions of the Si material. The method also includes breaking away the Si material to form silicon nanowires.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: July 19, 2011
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Andres Bryant, Edward J. Nowak, Jeffrey W. Sleight
  • Patent number: 7977211
    Abstract: The current invention presents a method for thinning wafers. The method uses a two-step process, whereby first the carrier wafer (2) is thinned and in a second step the device wafer (1) is thinned. The method is based on imprinting the combined thickness non-uniformities of carrier (2) and glue layer (3) essentially on the carrier (2), with a resulting low TTV of the wafer (100) after thinning.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: July 12, 2011
    Assignees: IMEC, Katholieke Universiteit Leuven
    Inventor: Ricardo Cotrin Teixeira
  • Patent number: 7977168
    Abstract: An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: July 12, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Honda, Yasuyuki Arai
  • Publication number: 20110136340
    Abstract: A method of fabricating a semiconductor device facilitates the forming of a conductive pattern of features having different widths. A conductive layer is formed on a substrate, and a mask layer is formed on the conductive layer. First spaced apart patterns are formed on the mask layer and a second pattern including first and second parallel portion is formed beside the first patterns on the mask layer. First auxiliary masks are formed over ends of the first patterns, respectively, and a second auxiliary mask is formed over the second pattern as spanning the first and second portions of the second pattern. The mask layer is then etched to form first mask patterns below the first patterns and a second mask pattern below the second pattern. The first and second patterns and the first and second auxiliary masks are removed. The conductive layer is then etched using the first and second mask patterns as an etch mask.
    Type: Application
    Filed: October 14, 2010
    Publication date: June 9, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Hwang Sim, Yoon-Moon PARK, Keon-Soo KIM, Min-Sung SONG, Young-Ho LEE
  • Patent number: 7947548
    Abstract: A method includes forming elongate structures (5) on a first substrate (3), such that the material composition of each elongate structure (7) varies along its length so as to define first and second physically different sections in the elongate structures. First and second physically different devices (1, 2) are then defined in the elongate structures. Alternatively, the first and second physically different sections may be defined in the elongate structures after they have been fabricated. The elongate structures may be encapsulated and transferred to a second substrate (7). The invention provides an improved method for the formation of a circuit structure that requires first and second physically different devices (1,2) to be provided on a common substrate. In particular, only one transfer step is necessary.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: May 24, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Thomas Heinz-Helmut Altebaeumer, Stephen Day, Jonathan Heffernan
  • Patent number: 7915736
    Abstract: Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. In one embodiment, a method of forming an interconnect in a microfeature workpiece includes forming a hole extending through a terminal and a dielectric layer to at least an intermediate depth in a substrate of a workpiece. The hole has a first lateral dimension in the dielectric layer and a second lateral dimension in the substrate proximate to an interface between the dielectric layer and the substrate. The second lateral dimension is greater than the first lateral dimension. The method further includes constructing an electrically conductive interconnect in at least a portion of the hole and in electrical contact with the terminal.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: March 29, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, William M. Hiatt, Richard L. Stocks
  • Publication number: 20110068436
    Abstract: Methods and structures for enhancing the homogeneity in a ratio of perimeter to surface area among heterogeneous features in different substrate regions. At least one shape on the substrate includes an added edge effective to reduce a difference in the perimeter-to-surface area ratio between the features in a first substrate region and features in a second substrate region. The improved homogeneity in the perimeter-to-surface area ratio reduces variations in a thickness of a conformal layer deposited across the features in the first and second substrate regions.
    Type: Application
    Filed: September 24, 2009
    Publication date: March 24, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James A. Culp, John J. Ellis-Monaghan, Jeffrey P. Gambino, Kirk D. Peterson, Jed H. Rankin
  • Patent number: 7892977
    Abstract: In a method for forming hard mask patterns of a semiconductor device first hard mask patterns are formed on a semiconductor substrate. Second hard mask patterns are formed and include first patterns which are substantially perpendicular to the first hard mask patterns and second patterns which are positioned between the first hard mask patterns. Third hard mask patterns are formed between the first patterns.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: February 22, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Woo Yung Jung
  • Publication number: 20110014788
    Abstract: A display panel structure having a circuit element disposed thereon and method of manufacture are provided. The display panel includes a substrate and the circuit element disposed on the substrate. The circuit element has a first interface layer and a first conductive layer. Both the first interface layer and the first conductive layer have cooper materials. The material which makes the first interface layer includes a reactant or a compound of the material which makes the first conductive layer. The method for manufacturing includes the following steps: forming a first interface layer on the substrate; forming a first conductive layer on the first interface layer; and etching the first conductive and interface layers to form a pattern. The existence of the first interface reduces the penetration of the first conductive layer on the substrate and improves the adhesive force between the first conductive layer and the substrate.
    Type: Application
    Filed: August 13, 2010
    Publication date: January 20, 2011
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Chun-Nan Lin, Kuo-Yuan Tu, Shu-Feng Wu, Wen-Ching Tsai
  • Patent number: 7867902
    Abstract: In a method of forming a contact structure, a first insulation layer including a first contact hole is formed on a substrate. A metal layer including tungsten is formed to fill the first contact hole. A planarization process is performed on the metal layer until the first insulation layer is exposed to form a first contact. A second contact is grown from the first contact. The second contact is formed without performing a photolithography process and an etching process to prevent misalignments.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: January 11, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-Hun Choi, Chang-Ki Hong, Hyun-Jun Sim, Yoon-Ho Son
  • Patent number: 7843025
    Abstract: A manufacturing method for a micromechanical semiconductor element includes providing on a semiconductor substrate a patterned stabilizing element having at least one opening. The opening is arranged such that it allows access to a first region in the semiconductor substrate, the first region having a first doping. Furthermore, a selective removal of at least a portion of the semiconductor material having the first doping out of the first region of the semiconductor substrate is provided. In addition, a membrane is produced above the first region using a first epitaxy layer applied on the stabilizing element. In a further method step, at least a portion of the first region is used to produce a cavity underneath the stabilizing element. In this manner, the present invention provides for the production of the patterned stabilizing element by means of a second epitaxy layer, which is applied on the semiconductor substrate.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: November 30, 2010
    Assignee: Robert Bosch GmbH
    Inventors: Hubert Benzel, Frank Schaefer, Simon Armbruster, Gerhard Lammel, Christoph Schelling, Joerg Brasas
  • Publication number: 20100263998
    Abstract: Vertical integrated MEMS switches, design structures and methods of fabricating such vertical switches is provided herein. The method of manufacturing a MEMS switch, includes forming at least two vertically extending vias in a wafer and filling the at least two vertically extending vias with a metal to form at least two vertically extending wires. The method further includes opening a void in the wafer from a bottom side such that at least one of the vertically extending wires is moveable within the void.
    Type: Application
    Filed: April 20, 2009
    Publication date: October 21, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Felix P. Anderson, Edward C. Cooney, III, Thomas L. Mcdevitt, Anthony K. Stamper