Of Silicon Body, E.g., For Gettering (epo) Patents (Class 257/E21.318)
E Subclasses
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Patent number: 8268705Abstract: The present invention is a method for producing an SOI wafer comprising at least a step of forming an ion-implanted damaged layer by ion-implanting a neutral element electrically inactive in silicon from one surface of the base wafer or the bond wafer, in which ion-implanting in the step of forming the ion-implanted damaged layer is performed at a dosage of 1×1012 atoms/cm2 or more and less than 1×1015 atoms/cm2. As a result, there may be provided a method for producing an SOI wafer having sufficient gettering ability while the suppression of leak failure, degradation of oxide dielectric breakdown voltage or the like is provided.Type: GrantFiled: April 23, 2007Date of Patent: September 18, 2012Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Kazuhiko Yoshida, Masao Matsumine, Hiroshi Takeno
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Publication number: 20120220084Abstract: A method of fabricating a polycrystalline silicon layer includes: forming an amorphous silicon layer on a substrate; crystallizing the amorphous silicon layer into a polycrystalline silicon layer using a crystallization-inducing metal; forming a metal layer pattern or metal silicide layer pattern in contact with an upper or lower region of the polycrystalline silicon layer corresponding to a region excluding a channel region in the polycrystalline silicon layer; and annealing the substrate to getter the crystallization-inducing metal existing in the channel region of the polycrystalline silicon layer to the region in the polycrystalline silicon layer having the metal layer pattern or metal silicide layer pattern. Accordingly, the crystallization-inducing metal existing in the channel region of the polycrystalline silicon layer can be effectively removed, and thus a thin film transistor having an improved leakage current characteristic and an OLED display device including the same can be fabricated.Type: ApplicationFiled: May 4, 2012Publication date: August 30, 2012Applicant: SAMSUNG MOBILE DISPLAY CO., LTD.Inventors: Byoung-Keon PARK, Jin-Wook SEO, Tae-Hoon YANG, Kil-Won LEE, Ki-Yong LEE
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Patent number: 8241941Abstract: The invention relates to a method of purifying a crystalline silicon substrate and to a process for producing a photovoltaic cell. The method of purifying a crystalline silicon substrate according to the invention is of the type that includes a step of extracting impurities by external gettering and which includes, before said step of extracting the impurities by external gettering, at least one step of rapidly annealing the substrate at a temperature of between 750° C. and 1000° C. inclusive for a time of between 1 second and 10 minutes inclusive. The invention is particularly applicable in the photovoltaic cell field.Type: GrantFiled: July 8, 2009Date of Patent: August 14, 2012Assignee: Commissariat a l'Energie AtomiqueInventors: Sébastien Dubois, Nicolas Enjalbert, Rémi Monna
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Patent number: 8227299Abstract: A method for removing impurities from at least one semiconductor device layer during manufacturing of a semiconductor device is disclosed. The semiconductor device layer has a compound semiconductor material and/or germanium. Each heating process performed during the manufacturing of the semiconductor device after provision of the semiconductor device layer has a low thermal budget determined by temperatures equal to or lower than about 900° C. and time periods equal to or lower than about 5 minutes. In one aspect, the method includes providing a germanium gettering layer with a higher solubility for the impurities than the semiconductor device layer. The germanium gettering layer is provided at least partly in direct or indirect contact with the at least one semiconductor device layer, such that impurities can diffuse from the at least one semiconductor device layer to the germanium gettering layer.Type: GrantFiled: May 1, 2009Date of Patent: July 24, 2012Assignees: IMEC, UmicoreInventors: Eddy Simoen, Jan Vanhellemont
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Publication number: 20120178240Abstract: A method of nucleating and growing oxygen precipitates of sufficient concentration and size in lightly doped p-type wafers for effective gettering of heavy metals is deep submicron transistor, integrated circuit manufacturing flows.Type: ApplicationFiled: January 10, 2012Publication date: July 12, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Bradley David Sucher
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Publication number: 20120168911Abstract: Provided is a method of fabricating a semiconductor device. The method includes: receiving a silicon wafer that contains oxygen; forming a zone in the silicon wafer, the zone being substantially depleted of oxygen; causing a nucleation process to take place in the silicon wafer to form oxygen nuclei in a region of the silicon wafer outside the zone; and growing the oxygen nuclei into defects. Also provided is an apparatus that includes a silicon wafer. The silicon wafer includes: a first portion that is substantially free of oxygen, the first portion being disposed near a surface of the silicon wafer; and a second portion that contains oxygen; wherein the second portion is at least partially surrounded by the first portion.Type: ApplicationFiled: December 30, 2010Publication date: July 5, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Ming Chen, Chung-Yi Yu, Chia-Shiung Tsai, Ho-Yung David Hwang, Alexander Kalnitsky
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Patent number: 8207048Abstract: Method for producing nanostructures comprising: a step of providing a substrate (100) having a buried barrier layer (2) and above said barrier layer (2) a crystalline film (5) provided with a network of crystalline defects and/or stress fields (12) in a crystalline zone (13), one or several steps of attacking the substrate (100), of which a preferential attack either of the crystalline defects and/or the stress fields, or the crystalline zone (13) between the crystalline defects and/or the stress fields, said attack steps enabling the barrier layer (2) to be laid bared locally and protrusions (7) to be formed on a nanometric scale, separated from each other by hollows (7.1) having a base located in the barrier layer, the protrusions leading to nanostructures (7, 8).Type: GrantFiled: December 19, 2006Date of Patent: June 26, 2012Assignee: Commissariat a l'Energie AtomiqueInventors: Franck Fournel, Hubert Moriceau, Chrystel Deguet
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Patent number: 8187954Abstract: The present invention provides a method for manufacturing a silicon single crystal wafer, in which a silicon single crystal wafer that is fabricated based on a Czochralski method and has an entire plane in a radial direction formed of an N region is subjected to a rapid thermal annealing in an oxidizing atmosphere, an oxide film formed in the rapid thermal annealing in the oxidizing atmosphere is removed, and then a rapid thermal annealing is carried out in a nitriding atmosphere, an Ar atmosphere, or a mixed atmosphere of these atmospheres. As a result, there can be provided the manufacturing method that can inexpensively manufacture a silicon single crystal wafer both in which a DZ layer is formed in a wafer surface layer to provide excellent device characteristics and in which an oxide precipitate functioning as a gettering site can be sufficiently formed in a bulk region.Type: GrantFiled: January 24, 2008Date of Patent: May 29, 2012Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Yoshinori Hayamizu, Hiroyasu Kikuchi
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Patent number: 8187959Abstract: Method of producing a semiconductor device, comprising: a) providing a semiconductor substrate, b) making a first amorphous layer in a top layer of the semiconductor substrate by a suitable implant, the first amorphous layer having a first depth, c) implanting a first dopant into the semiconductor substrate to provide the first amorphous layer with a first doping profile, d) applying a first solid phase epitaxial regrowth action to partially regrow the first amorphous layer and form a second amorphous layer having a second depth that is less than the first depth and activate the first dopant, e) implanting a second dopant into the semiconductor substrate to provide the second amorphous layer with a second doping profile with a higher doping concentration than the first doping profile, f) applying a second solid phase epitaxial regrowth action to regrow the second amorphous layer and activate the second dopant.Type: GrantFiled: December 2, 2004Date of Patent: May 29, 2012Assignee: IMECInventors: Bartlomiej Jan Pawlak, Raymond James Duffy, Richard Lindsay
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Patent number: 8173523Abstract: To provide a method of removing a heavy metal contained in a thinned semiconductor substrate. A method of removing a heavy metal in a semiconductor substrate of the present invention comprises: attaching, to a rear surface of the semiconductor substrate, a material that lowers a potential barrier of the rear surface of the semiconductor substrate, on a front surface of which a circuit is to be formed or is formed; applying a thermal treatment to the semiconductor substrate under a condition based on a thickness and a resistivity of the semiconductor substrate; and, depositing the heavy metal in the semiconductor substrate on the rear surface.Type: GrantFiled: October 6, 2010Date of Patent: May 8, 2012Assignee: Sumco CorporationInventors: Noritomo Mitsugi, Masataka Hourai, Shuichi Samata, Kiyoshi Nagai, Kei Matsumoto
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Patent number: 8143142Abstract: A method of fabricating an epi-wafer includes providing a wafer including boron by cutting a single crystal silicon ingot, growing an insulating layer on one surface of the wafer, performing thermal treatment of the wafer, removing the insulating layer formed on one surface of the wafer, mirror-surface-grinding one surface of the wafer, and growing an epitaxial layer on one surface of the wafer and forming a high-density boron layer within the wafer that corresponds to the interface between the wafer and the epitaxial layer.Type: GrantFiled: March 15, 2010Date of Patent: March 27, 2012Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Young-Soo Park, Gi-Jung Kim, Won-Je Park, Jae-Sik Bae
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Publication number: 20120068300Abstract: An approach to activating a getter within a sealed vacuum cavity is disclosed. The approach uses inductive coupling from an external coil to a magnetically permeable material deposited in the vacuum cavity. The getter material is formed over this magnetically permeable material, and heated specifically thereby, leaving the rest of the device cavity and microdevice relatively cool. Using this inductive coupling technique, the getter material can be activated after encapsulation, and delicate structures and low temperature wafer bonding mechanisms may be used.Type: ApplicationFiled: September 20, 2011Publication date: March 22, 2012Applicant: Innovative Micro TechnologyInventor: Jeffery F. Summers
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Patent number: 8138066Abstract: A method for generating patterned strained regions in a semiconductor device is provided. The method includes directing a light-emitting beam locally onto a surface portion of a semiconductor body; and manipulating a plurality of dislocations located proximate to the surface portion of the semiconductor body utilizing the light-emitting beam, the light-emitting beam being characterized as having a scan speed, so as to produce the patterned strained regions.Type: GrantFiled: October 1, 2008Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Chung Woh Lai, Xiao Hu Liu, Anita Madan, Klaus W. Schwarz, J. Campbell Scott
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Publication number: 20120049330Abstract: A method of producing a silicon wafer comprises the steps of subjecting a silicon wafer, which has been sliced from a silicon single crystal ingot grown by the Czochralski method, to RTA treatment in a nitriding gas atmosphere; forming an oxide film on a surface of either side of the wafer; then forming a polysilicon layer thereon. The polysilicon layer on the front side of the wafer is removed and a wafer free of crystal defects in the surface part and with improved gettering performance is obtained. The polysilicon layer may be formed not on the surface of either side of the wafer but only on the back side thereof. It is desirable that a wafer composed of only a defect-free region is used as the source material since a defect-free layer can be stably secured in the wafer surface part.Type: ApplicationFiled: April 9, 2010Publication date: March 1, 2012Applicant: SUMCO CORPORATIONInventor: Yasushi Yukimoto
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Patent number: 8124501Abstract: A semiconductor wafer is produced by irradiating a laser beam to either face of a semiconductor wafer so as to fit a focusing position into a given depth position of the semiconductor wafer to generate a multiphoton absorption process only in a specific portion of the semiconductor wafer at the given depth position to thereby form a gettering sink.Type: GrantFiled: May 6, 2009Date of Patent: February 28, 2012Assignee: SUMCO CorporationInventor: Kazunari Kurita
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Patent number: 8124502Abstract: A semiconductor device manufacturing method is provided, including: providing a semiconductor substrate, forming on the semiconductor substrate a layer including a semiconductor compound and a dope additive, and thereafter forming an emitter region and gettering impurities by annealing the semiconductor substrate including the layer.Type: GrantFiled: October 23, 2008Date of Patent: February 28, 2012Assignee: Applied Materials, Inc.Inventor: Rafel Ferre i Tomas
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Patent number: 8119461Abstract: By performing a heat treatment on the basis of a hydrogen ambient, exposed silicon-containing surface portions may be reorganized prior to the formation of gate dielectric materials. Hence, the interface quality and the material characteristics of the gate dielectrics may be improved, thereby reducing negative bias temperature instability effects in highly scaled P-channel transistors.Type: GrantFiled: November 1, 2010Date of Patent: February 21, 2012Assignee: GLOBALFOUNDRIES Inc.Inventors: Martin Trentzsch, Thorsten Kammler, Rolf Stephan
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Patent number: 8110451Abstract: A method for manufacturing a light emitting device, includes: forming a first multilayer body including a first substrate, a first semiconductor layer provided on the first substrate and having a light emitting layer, and a first metal layer provided on the first semiconductor layer; forming a second multilayer body including a second substrate having a thermal expansion coefficient different from a thermal expansion coefficient of the first substrate, and a second metal layer provided on the second substrate; a first bonding step configured to heat the first metal layer and the second metal layer being in contact with each other; removing the first substrate after the first bonding step; and a second bonding step configured to perform, after the removing, heating at a temperature higher than a temperature of the first bonding step.Type: GrantFiled: August 20, 2009Date of Patent: February 7, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yasuhiko Akaike, Ryo Saeki, Yoshinori Natsume
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Patent number: 8101999Abstract: A SOI substrate includes a silicon substrate, a silicon oxide layer arranged on the silicon substrate, a silicon layer arranged on the silicon oxide layer, a gettering layer arranged in the silicon substrate, and a damaged layer formed of an impurity-doped region arranged in the silicon oxide layer.Type: GrantFiled: October 6, 2009Date of Patent: January 24, 2012Assignee: Sony CorporationInventor: Ritsuo Takizawa
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Patent number: 8093089Abstract: Method of manufacturing image sensors having a plurality of gettering regions. In the method, a gate electrode may be formed on a semiconductor substrate. A source/drain region may be formed in the semiconductor substrate to be overlapped with the gate electrode. A gettering region may be formed in the semiconductor substrate to be adjacent to the source/drain region.Type: GrantFiled: April 19, 2010Date of Patent: January 10, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Hyun-Pil Noh
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Patent number: 8093719Abstract: In one embodiment, an integrated circuit device includes an active area encompassed by a seal ring. The seal ring may include a deep moat formed on an outer edge of the seal ring. The deep moat may have a depth that extends substantially to the substrate to prevent cracks from propagating into the active area. Alternatively or in addition, the seal ring may include redundant vias.Type: GrantFiled: November 16, 2005Date of Patent: January 10, 2012Assignee: Cypress Semiconductor CorporationInventor: Farnaz Parhami
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Publication number: 20120001301Abstract: An annealed wafer obtained by performing rapid thermal annealing on a silicon single crystal wafer sliced from a silicon single crystal ingot in which an entire plane is an OSF region, an N region outside an OSF region, or a mixed region thereof, the silicon single crystal ingot being grown by the Czochralski method, in which RIE defects do not exist in a region having at least a depth of 1 ?m from a surface, a good chip yield of a TDDB characteristic is 80% or more, and a depth of a region where an oxygen concentration is decreased due to outward diffusion is within 3 ?m from the surface, and a method for producing an annealed wafer.Type: ApplicationFiled: March 17, 2010Publication date: January 5, 2012Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Koji Ebara, Yoshinori Hayamizu, Hiroyasu Kikuchi
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Patent number: 8084286Abstract: Producing a solid-state imaging device by (1) forming a structure including (a) a substrate having a first impurity with a first concentration, (b) a first conductive type Si layer and (c) a first conductive type impurity layer stacked on one another in that order, the first conductive type Si layer being formed on the substrate, the first conductive type impurity layer being formed in a boundary region including a boundary of the substrate and the Si layer, and a part of the substrate facing the boundary and a part of the first conductive type Si layer facing the boundary having a second impurity; and (2) forming in the Si layer a second conductive type region capable of storing in the Si layer a charge generated by a photoelectric conversion; and forming an interconnection layer on the Si layer.Type: GrantFiled: November 10, 2010Date of Patent: December 27, 2011Assignee: Sony CorporationInventor: Hideo Kanbe
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Patent number: 8080449Abstract: Gate electrodes are formed on a substrate. A gate insulation film is formed so as to cover the gate electrodes. A semiconductor layer is formed in regions on the gate insulation film in a region which overlap with at least the gate electrodes. Plasma treatment is applied to the semiconductor layer using a gas which contains a dopant thus increasing impurity concentration of a surface layer of the semiconductor layer. A conductive film is formed on the surface layer of the semiconductor layer to which the plasma treatment is applied. A source electrode and a drain electrode are formed by etching the conductive film.Type: GrantFiled: April 7, 2010Date of Patent: December 20, 2011Assignees: Hitachi Displays, Ltd., Panasonic Liquid Crystal Display Co., Ltd.Inventors: Hidekazu Nitta, Hidekazu Miyake, Takuo Kaitoh, Daisuke Sonoda
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Patent number: 8030184Abstract: An epitaxial wafer comprises a silicon substrate, a gettering epitaxial film formed thereon and containing silicon and carbon, and a main silicon epitaxial film formed on the gettering epitaxial film, in which the gettering epitaxial film has a given carbon atom concentration and carbon atoms are existent between its silicon lattices.Type: GrantFiled: December 12, 2008Date of Patent: October 4, 2011Assignee: Sumco CorporationInventors: Naoshi Adachi, Tamio Motoyama
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Publication number: 20110227070Abstract: Provided herein are gettering members that include a monitor substrate and a conditioning layer thereon. Also provided herein are methods of forming gettering layers and methods of performing immersion lithography processes using the same.Type: ApplicationFiled: March 18, 2011Publication date: September 22, 2011Inventors: Jin-Young Yoon, Hyun-Woo Kim, Chan Hwang, Yun-Kyeong Jang
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Patent number: 8008107Abstract: Techniques are here disclosed for a solar cell pre-processing method and system for annealing and gettering a solar cell semiconductor wafer having an undesirably high dispersion of transition metals, impurities and other defects. The process forms a surface contaminant layer on the solar cell semiconductor (e.g., silicon) wafer. A surface of the semiconductor wafer receives and holds impurities, as does the surface contaminant layer. The lower-quality semiconductor wafer includes dispersed defects that in an annealing process getter from the semiconductor bulk to form impurity cluster toward the surface contaminant layer. The impurity clusters form within the surface contaminant layer while increasing the purity level in wafer regions from which the dispersed defects gettered. Cooling follows annealing for retaining the impurity clusters and, thereby, maintaining the increased purity level of the semiconductor wafer in regions from which the impurities gettered.Type: GrantFiled: December 30, 2006Date of Patent: August 30, 2011Assignee: Calisolar, Inc.Inventors: Fritz Kirscht, Kamel Ounadjela, Jean Patrice Rakotoniana, Dieter Linke
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Patent number: 8003493Abstract: A process for splitting a semiconductor substrate having an identification notch on its periphery, by creating a weakened zone in the substrate by implanting atomic species into the substrate while the substrate is held in place on a portion of its periphery during the implanting; and splitting the substrate along the weakened zone by placing the held portion of the substrate in a splitting-wave initiation sector while positioning the notch for initiating a splitting wave followed by the propagation of the wave into the substrate. During splitting the notch is positioned so that it is in a quarter of the periphery of the substrate diametrically opposite the sector for initiating the splitting wave or in the quarter of the periphery of the substrate that is centered on the sector.Type: GrantFiled: October 21, 2008Date of Patent: August 23, 2011Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Nadia Ben Mohamed, Sébastien Kerdiles
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Patent number: 7993987Abstract: A method includes providing a substrate including a non-insulative, silicon-including region for silicidation, the substrate including one or more contaminants at a top surface thereof. A getter layer is deposited over the non-insulative, silicon-including region, the getter layer reacting with at least one of the one or more contaminants in the non-insulative, silicon-including region at approximately room temperature. The getter layer is removed, and siliciding of the non-insulative, silicon-including region is performed.Type: GrantFiled: October 14, 2010Date of Patent: August 9, 2011Assignee: International Business Machines CorporationInventors: Randolph F. Knarr, Christian Lavoie, Ahmet S. Ozcan, Filippos Papadatos
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Publication number: 20110183496Abstract: A substrate carrier structure includes a tray and a secondary electron absorbing material. The tray holds a semiconductor substrate having a first surface on which semiconductor device elements are formed. The secondary electron absorbing material is interposed between the tray and this first surface of the semiconductor substrate. When the semiconductor substrate is irradiated with charged particles to form lattice defects, the secondary electron absorbing material prevents unwanted trapping of secondary electrons emitted from the tray, and thereby reduces the variability of electrical characteristics of semiconductor device elements formed on the semiconductor substrate.Type: ApplicationFiled: January 19, 2011Publication date: July 28, 2011Applicant: OKI SEMICONDUCTOR CO., LTD.Inventor: Yuichi KANEKO
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Publication number: 20110171814Abstract: A method for preparing a silicon epitaxial wafer that includes a silicon single crystal wafer sliced from a CZ silicon ingot doped with carbon in a concentration range of not less than 5×1015 atoms/cm3 and not more than 5×1017 atoms/cm3 and an epitaxial layer consisting of a silicon single crystal epitaxially grown on a front surface of the silicon single crystal wafer. A polycrystalline silicon layer having a thickness of not less than 0.5 ?m and not more than 1.5 ?m is formed on a back surface of the silicon single crystal wafer.Type: ApplicationFiled: March 18, 2011Publication date: July 14, 2011Applicant: SUMCO CORPORATIONInventors: Shinsuke Sadamitsu, Masataka Hourai
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Publication number: 20110156215Abstract: A silicon wafer includes BMDs with a diagonal length of from 10 nm to 50 nm, and has a density of BMD which exists at a depth of 50 ?m and deeper from the surface of the silicon wafer which is greater than or equal to 1×1011/cm3, and a ratio of the {111} plane of the BMD to the total planes surrounding the BMD, as an indication of the morphology of the BMD, is less than or equal to 0.3.Type: ApplicationFiled: November 30, 2010Publication date: June 30, 2011Applicant: SILTRONIC AGInventor: Katsuhiko Nakai
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Publication number: 20110127660Abstract: Embodiments of the invention provide an electronic device which may include an interior compartment housing at least one electronic component that may be reactive to target impurities. The electronic component may include at least a cathode and an anode. A purifier material may be interspersed within a conducting polymer layer between the cathode and the anode. The purifier material may decrease target impurities within the interior compartment of the electronic device from a first level to a second level.Type: ApplicationFiled: February 9, 2011Publication date: June 2, 2011Applicant: Matheson Tri-GasInventors: Robert Torres, JR., Tadaharu Watanabe, Joseph V. Vininski
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Patent number: 7943494Abstract: The present invention provides a method for blocking the dislocation propagation of a semiconductor. A semiconductor layer is formed by epitaxial process on a substrate. A plurality of recesses is formed on the semiconductor layer by etching fragile locations of the semiconductor layer where dislocation occurs. Thereafter, a blocking layer is formed on each of the plurality of recesses. The aforesaid semiconductor layer undergoes epitaxial process again on the aforesaid semiconductor layer, and laterally overgrows to redirect the dislocation defects.Type: GrantFiled: October 15, 2009Date of Patent: May 17, 2011Assignee: Advanced Optoelectronic Technology, Inc.Inventors: Peng Yi Wu, Shih Cheng Huang, Po Min Tu, Ying Chao Yeh, Wen Yu Lin, Shih Hsiung Chan
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Publication number: 20110089474Abstract: An active region made of Si or SiGe is formed in a surface part of a substrate. A gate electrode is disposed over the active region. A gate insulating film is disposed between the gate electrode and the substrate. A source and a drain are formed in the surface part of the substrate on sides of the gate electrode. A surface of the active region under the gate electrode includes a slope surface being upward from a border of the active region toward an inner side of the active region. The slope surface has a crystal plane equivalent to (331).Type: ApplicationFiled: December 9, 2010Publication date: April 21, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Hidenobu Fukutome
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Publication number: 20110086494Abstract: To provide a method of removing a heavy metal contained in a thinned semiconductor substrate. A method of removing a heavy metal in a semiconductor substrate of the present invention comprises: attaching, to a rear surface of the semiconductor substrate, a material that lowers a potential barrier of the rear surface of the semiconductor substrate, on a front surface of which a circuit is to be formed or is formed; applying a thermal treatment to the semiconductor substrate under a condition based on a thickness and a resistivity of the semiconductor substrate; and, depositing the heavy metal in the semiconductor substrate on the rear surface.Type: ApplicationFiled: October 6, 2010Publication date: April 14, 2011Applicant: SUMCO CORPORATIONInventors: Noritomo Mitsugi, Masataka Hourai, Shuichi Samata, Kiyoshi Nagai, Kei Matsumoto
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Publication number: 20110073869Abstract: A crystalline material structure with reduced dislocation density and method of producing same is provided. The crystalline material structure is annealed at temperatures above the brittle-to-ductile transition temperature of the crystalline material structure. One or more stress elements are formed on the crystalline material structure so as to annihilate dislocations or to move them into less harmful locations.Type: ApplicationFiled: September 28, 2010Publication date: March 31, 2011Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGYInventors: Anthony Buonassisi, Mariana Bertoni, Ali Argon, Sergio Castellanos, Alexandria Fecych, Douglas Powell, Michelle Vogl
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Publication number: 20110076838Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first insulating layer formed over the semiconductor substrate, and a first semiconductor layer formed over the first insulation layer. At least one gettering region is formed in at least one of the first insulating layer and the first semiconductor layer. The gettering region includes a plurality of gettering sites, and at least one gettering site includes one of a precipitate, a dispersoid, an interface with the dispersoid, a stacking fault and a dislocation.Type: ApplicationFiled: November 29, 2010Publication date: March 31, 2011Inventors: Young-Soo Park, Young-Nam Kim, Young-Sam Lim, Gi-Jung Kim, Pil-Kyu Kang
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Patent number: 7915145Abstract: A silicon substrate is manufactured from single-crystal silicon which is grown to have a carbon concentration equal to or higher than 1.0×1016 atoms/cm3 and equal to or lower than 1.6×1017 atoms/cm3 and an initial oxygen concentration equal to or higher than 1.4×1018 atoms/cm3 and equal to or lower than 1.6×1018 atoms/cm3 by a CZ method. A device is formed on a front, the thickness of the silicon substrate is equal to or more than 5 ?m and equal to or less than 40 ?m, and extrinsic gettering which produces residual stress equal to or more than 5 Mpa and equal to or less than 200 Mpa is applied to a back face of the substrate.Type: GrantFiled: February 24, 2009Date of Patent: March 29, 2011Assignee: Sumco CorporationInventors: Kazunari Kurita, Shuichi Omote
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Publication number: 20110065263Abstract: It is an object of the invention is to provide a method suitable for reprocessing a semiconductor substrate having favorable planarity. Another object of the invention is to manufacture a reprocessed semiconductor substrate by using the method suitable for reprocessing a semiconductor substrate having favorable planarity, and to manufacture an SOI substrate by using the reprocessed semiconductor substrate. A projecting portion of a semiconductor substrate is removed using a method capable of selectively removing a semiconductor region which is damaged by ion irradiation or the like. Further, an oxide film is formed on a surface of the semiconductor substrate when the semiconductor substrate is planarized by a polishing treatment typified by a CMP method, whereby the semiconductor substrate is evenly polished at a uniform rate. Moreover, a reprocessed semiconductor substrate is manufactured using the aforementioned method, and an SOI substrate is manufactured using the reprocessed semiconductor substrate.Type: ApplicationFiled: August 19, 2010Publication date: March 17, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Ryota IMAHAYASHI, Hideto OHNUMA
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Publication number: 20110053305Abstract: Producing a solid-state imaging device by (1) forming a structure including (a) a substrate having a first impurity with a first concentration, (b) a first conductive type Si layer and (c) a first conductive type impurity layer stacked on one another in that order, the first conductive type Si layer being formed on the substrate, the first conductive type impurity layer being formed in a boundary region including a boundary of the substrate and the Si layer, and a part of the substrate facing the boundary and a part of the first conductive type Si layer facing the boundary having a second impurity; and (2) forming in the Si layer a second conductive type region capable of storing in the Si layer a charge generated by a photoelectric conversion; and forming an interconnection layer on the Si layer.Type: ApplicationFiled: November 10, 2010Publication date: March 3, 2011Applicant: SONY CORPORATIONInventor: Hideo Kanbe
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Publication number: 20110053350Abstract: A silicon wafer which has DZ layers formed on both sides thereof by heat treatment in an atmosphere of reducing gas (such as hydrogen) or rare gas (such as argon) with a specific temperature profile for heating, holding, and cooling, and which also has a gettering site of BMD in the bulk inside the DZ layer. A silicon wafer which has a silicon epitaxial layer formed on one side thereof. The DZ layer and the silicon epitaxial layer contain dissolved oxygen introduced into their surface parts, with the concentration and distribution of dissolved oxygen properly controlled. Introduction of oxygen into the surface part is accomplished by heat treatment and ensuing rapid cooling in an atmosphere of oxygen-containing gas.Type: ApplicationFiled: November 5, 2010Publication date: March 3, 2011Inventors: Takashi WATANABE, Ryuji Takeda
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Publication number: 20110049664Abstract: Provided is an epitaxial substrate for a back-illuminated image sensor and a manufacturing method thereof that is capable of suppressing metal contaminations and reducing occurrence of a white spot defect of the image sensor, by maintaining a sufficient gettering performance in a device process. The present invention includes forming a gettering sink immediately below a surface of a high-oxygen silicon substrate, forming a first epitaxial layer on the surface of the high-oxygen silicon substrate, and forming a second epitaxial layer on the first epitaxial layer, in which the step of forming the gettering sink includes forming an oxygen precipitate region by applying a long-time heat treatment at a temperature of 650-1150° C. to the high-oxygen silicon substrate.Type: ApplicationFiled: August 31, 2010Publication date: March 3, 2011Applicant: SUMCO CORPORATIONInventor: Kazunari Kurita
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Publication number: 20110049717Abstract: An IC includes a substrate having a semiconductor top surface and a bottom surface, wherein the semiconductor top surface includes one or more active circuit components and a plurality of through silicon vias (TSVs) extending through the substrate. The plurality of TSVs include an outer dielectric liner. The dielectric liner includes at least one halogen or a Group 15 element metal gettering agent in an average concentration from 1 to 10 atomic %. A metal diffusion barrier layer is on the dielectric liner and a metal filler is on the metal barrier layer. The metal gettering agent getters metal filler that escapes the metal barrier layer.Type: ApplicationFiled: September 3, 2009Publication date: March 3, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: JEFFREY A. WEST
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Publication number: 20110053349Abstract: A method for fabricating semiconductor devices, e.g., strained silicon MOS device, includes providing a semiconductor substrate (e.g., silicon wafer) having a surface region, which has one or more contaminants and an overlying oxide layer. The one or more contaminants is at least a carbon species. The method also includes processing the surface region using at least a wet process to selectively remove the oxide layer and expose the surface region. The method further includes subjecting the surface region to a laser treatment process for a time period of less than 1 second to increase a temperature of the surface region to greater than 1000 degrees Celsius to remove the one or more contaminants provided on the surface region. The method also includes removing the laser treatment process to cause a reduction in temperature to about 300 to about 600 degrees Celsius in a time period of less than 1 second.Type: ApplicationFiled: July 22, 2010Publication date: March 3, 2011Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: DAVID GAO, Fumitake Mieno
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Publication number: 20110042791Abstract: A method for treating an oxygen-containing semiconductor wafer, and semiconductor component. One embodiment provides a first side, a second side opposite the first side. A first semiconductor region adjoins the first side. A second semiconductor region adjoins the second side. The second side of the wafer is irridated such that lattice vacancies arise in the second semiconductor region. A first thermal process is carried out the duration of which is chosen such that oxygen agglomerates form in the second semiconductor region and that lattice vacancies diffuse from the first semiconductor region into the second semiconductor region.Type: ApplicationFiled: January 19, 2007Publication date: February 24, 2011Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Hans-Joachim Schulze, Helmut Strack, Anton Mauder
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Patent number: 7868360Abstract: There are disclosed TFTs that have excellent characteristics and can be fabricated with a high yield. The TFTs are fabricated, using an active layer crystallized by making use of nickel. Gate electrodes are comprising tantalum. Phosphorus is introduced into source/drain regions. Then, a heat treatment is performed to getter nickel element in the active layer and to drive it into the source/drain regions. At the same time, the source/drain regions can be annealed out. The gate electrodes of tantalum can withstand this heat treatment.Type: GrantFiled: May 12, 2008Date of Patent: January 11, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 7867920Abstract: There is provided a method for modifying a high-k dielectric thin film provided on the surface of an object using a metal organic compound material. The method includes a preparation process for providing the object with the high-k dielectric thin film formed on the surface thereof, and a modification process for applying UV rays to the highly dielectric thin film in an inert gas atmosphere while maintaining the object at a predetermined temperature to modify the high-k dielectric thin film. According to the above constitution, the carbon component can be eliminated from the high-k dielectric thin film, and the whole material can be thermally shrunk to improve the density, whereby the occurrence of defects can be prevented and the film density can be improved to enhance the specific permittivity and thus to provide a high level of electric properties.Type: GrantFiled: November 22, 2006Date of Patent: January 11, 2011Assignee: Tokyo Electron LimitedInventors: Kazuyoshi Yamazaki, Shintaro Aoyama, Koji Akiyama
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Publication number: 20100311199Abstract: A method of producing an epitaxial substrate for a solid-state imaging device, comprising: forming a gettering sink by injecting laser beam to a semiconductor substrate through one surface thereof, condensing the laser beam to an arbitrarily selected portion of the semiconductor substrate, thereby causing multi-photon absorption process to occur in the portion, and forming a gettering sink having a modified crystal structure; and epitaxially growing at least two epitaxial layers on the semiconductor substrate in which the gettering sink is formed.Type: ApplicationFiled: May 28, 2010Publication date: December 9, 2010Applicant: SUMCO CORPORATIONInventor: Kazunari KURITA
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Publication number: 20100304552Abstract: A method for manufacturing a semiconductor substrate dedicated to a semiconductor device, in which multi-photon absorption is generated in a micro-region inside the semiconductor substrate by condensing laser beams in any micro-region inside the semiconductor substrate, and a gettering sink is formed by changing the crystal structure of only the micro-region.Type: ApplicationFiled: May 26, 2010Publication date: December 2, 2010Applicant: SUMCO CORPORATIONInventor: Kazunari KURITA