Abstract: A manufacturing method of a semiconductor device, includes the following steps: providing a substrate with an insulated surface; forming an amorphous silicon layer on the insulated surface; imposing a catalytic metal element on the amorphous silicon layer; heating and catalyzing the amorphous silicon layer to form a poly-silicon layer; forming a diffusion layer and a gettering material layer on the poly-silicon layer in order; proceeding an annealing process on the gettering material layer and the poly-silicon layer to move the residual metal catalyst element from the poly-silicon layer toward the gettering material layer due to the concentration gradient; and removing the diffusion layer and the gettering material layer.

Abstract: A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A data wire having source electrodes, drain electrodes and data lines is formed on the gate insulating layer and the semiconductor pattern. A protective layer is formed on the data wire. Pixel electrodes connected to the drain electrode via contact holes are formed on the protective layer. The gate wire and the data wire are made of Ag alloy containing Ag and an additive including at least one selected from Zn, In, Sn and Cr.

Abstract: An exemplary thin film transistor (TFT) array substrate (200) includes: a substrate (210), a gate electrode (220) disposed on the substrate, a gate insulating layer (230) disposed on the substrate having the gate electrode, a lightly doped amorphous silicon (a-Si) layer (241) disposed on the gate insulating layer, a first a-Si layer (242) disposed on the lightly doped a-Si layer, a source electrode (251) and a drain electrode (252) disposed on the gate insulating layer and the a-Si layer. The thin film transistor array substrate has a low leakage current.

Abstract: Provided is a thin film transistor that may be manufactured using Metal Induced Crystallization (MIC) and method for fabricating the same. Also provided is an active matrix flat panel display using the thin film transistor, which may be created by forming a crystallization inducing metal layer below a buffer layer and diffusing the crystallization inducing metal layer. The thin film transistor may include a crystallization inducing metal layer formed on an insulating substrate, a buffer layer formed on the crystallization inducing metal layer, and an active layer formed on the buffer layer and including source/drain regions, and including polycrystalline silicon crystallized by the MIC process.

Abstract: It is an object of the invention that, in semiconductor device, in order to promote the tendency of miniaturization of each display pixel pitch, which will be resulted in with the tendency toward the higher precision (increase of pixel number) and further miniaturizations, a plurality of elements is formed within a limited area and the area occupied by the elements is compacted so as to be integrated. A plurality of semiconductor layers 13, 15 is formed on different layers with insulating film 14 sandwiched therebetween. After carrying out crystallization by means of laser beam, on each semiconductor layer (semiconductor layers 16, 17 having crystal structure respectively), an N-channel type TFT of inversed stagger structure and a P-channel type TFT 30 of top gate structure are formed respectively and integrated so that the size of CMOS circuit is miniaturized.

Abstract: A method for fabricating organic electroluminescent devices is disclosed. The method comprises providing a substrate divided into first and second regions, forming an amorphous silicon layer on the substrate, forming a protection film on the amorphous silicon layer within the second region, performing an excimer laser annealing process on the amorphous silicon layer for converting it to a polysilicon layer, removing the protection film, patterning the polysilicon layer, thus a first patterned polysilicon layer in the first region and a second patterned polysilicon layer in the second region are formed. A resultant organic electroluminescent device is obtained. Specifically, the grain size of the first patterned polysilicon layer is large than that of the second patterned polysilicon layer.

Abstract: A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.

Abstract: A liquid crystal display device including first and second active layers over a substrate, a storage line over the second active layer, a first insulating layer over the storage line, a gate electrode on the first insulating layer and corresponding to the first active layer, a second insulating layer over the gate electrode, source and drain electrodes connected to the first active layer through the first and second insulating layers, a gate line connected to the gate electrode through the second insulating layer, a data line substantially perpendicularly arrange with respect to the gate line to define a pixel region, a pixel electrode connected to the drain electrode through the second insulating layer, and a connection line connected to one of the gate line and the data line through the second insulating layer.

Abstract: Methods for depositing hemispherical grained silicon layers and nanocrystalline grain-sized polysilicon layers are provided. The hemispherical grained silicon layers and nanocrystalline grain-sized polysilicon layers are deposited in single substrate chemical vapor deposition chambers. The hemispherical grained silicon layers and nanocrystalline grain-sized polysilicon layers may be used as electrode layers in semiconductor devices. In one aspect, a two step deposition process is provided to form a nanocrystalline grain-sized polysilicon layer with a reduced roughness.

Abstract: A thin film semiconductor device is provided. The semiconductor device includes a semiconductor thin film configured to have an active region turned into a polycrystalline region through irradiation with an energy beam, and a gate electrode configured to be provided to traverse the active region. Successive crystal grain boundaries extend along the gate electrode in a channel part that is the active region overlapping with the gate electrode, and the crystal grain boundaries traverse the channel part and are provided cyclically in a channel length direction.

Abstract: A semiconductor thin film according to an embodiment of the present invention includes: a polycrystallized semiconductor thin film formed by applying laser light to an amorphous semiconductor thin film; and crystal grains arranged into a lattice shape with a size that is about ½ of an oscillation wavelength of the laser light.

Abstract: The present invention provides a TFT substrate that includes a plurality of TFTs each of which have a gate, a source and a drain. The plurality of the TFTs may be formed by first and second active regions formed on the substrate that each have a source region that corresponds to a source and a drain region that corresponds to a drain. An offset region may be formed between the first and second active regions. A single contact hole may reach both the offset region and the adjacent source/drain regions of the first and second active regions.

Abstract: The present invention obtains a system-in-panel display device using a high-performance thin film transistor by suppressing aggregation of a molten semiconductor at the time of allowing strip-like pseudo-single crystal to grow continuously with a direction control by radiating beams of continuous oscillation laser to a semiconductor film made of silicon while scanning. A display device includes a silicon nitride film formed on the insulation substrate, a silicon oxide film formed on the silicon nitride film, a semiconductor film formed on the silicon oxide film, and a thin film transistor which uses the semiconductor film. Here, the silicon oxide film is constituted of a first silicon oxide film formed using SiH4 and N2O as raw material gases and a second silicon oxide film formed using a TEOS gas as a raw material gas, and the semiconductor film is made of pseudo-single crystal having strip-like grains.

Abstract: A method and structure for fabricating an electronic device using an SOI technique that results in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component of the electronic device, wherein the first component and the second component are on opposite sides of the buried oxide layer, thereby causing the buried oxide layer to perform a function within the electronic device. Entire circuits can be designed around this technique.

Abstract: A semiconductor film serving as an active region of a thin film transistor and an upper oxide film protecting the semiconductor film are dry etched to form the active region. In this case, a fluorine-based gas is used as the etching gas, and the etching gas is switched from the fluorine-based gas to a chlorine-based gas at a point of time when a lower oxide film as an underlying film of the semiconductor film is exposed. As the fluorine-based gas, a mixed gas of CF4 and O2 is used, and suitably, a gas ratio of CF4 and O2 in the mixture gas is set at 1:1, and the dry etching is performed therefor. By this etching, a side face of a two-layer structure of the semiconductor film and upper oxide film is optimally tapered, and a crack or a disconnection is prevented from being occurring in a film crossing over the two-layer structure.

Abstract: It is an object of the present invention to provide a method for manufacturing a semiconductor device, capable of keeping a peeling layer from being peeled from a substrate in the phase before the completion of a semiconductor element and peeling a semiconductor element rapidly. It is considered that a peeling layer tends to be peeled from a substrate because the stress is applied to a peeling layer due to the difference in thermal expansion coefficient between a substrate and a peeling layer, or because the volume of a peeling layer is reduced and thus the stress is applied thereto by crystallization of the peeling layer due to heat treatment. Therefore, according to one feature of the invention, the adhesion of a substrate and a peeling layer is enhanced by forming an insulating film (buffer film) for relieving the stress on the peeling layer between the substrate and the peeling layer before forming the peeling layer over the substrate.

Abstract: It is an object of the invention that, in semiconductor device, in order to promote the tendency of miniaturization of each display pixel pitch, which will be resulted in with the tendency toward the higher precision (increase of pixel number) and further miniaturizations, a plurality of elements is formed within a limited area and the area occupied by the elements is compacted so as to be integrated. A plurality of semiconductor layers 13, 15 is formed on different layers with insulating film 14 sandwiched therebetween. After carrying out crystallization by means of laser beam, on each semiconductor layer (semiconductor layers 16, 17 having crystal structure respectively), an N-channel type TFT of inversed stagger structure and a P-channel type TFT 30 of top gate structure are formed respectively and integrated so that the size of CMOS circuit is miniaturized.

Abstract: A TFT according to an embodiment of the present invention includes an insulative base film formed on a TFT array substrate, and a semiconductor film including a channel region formed on the base film, in which an impurity concentration of a channel region in the semiconductor film becomes substantially uniform in a film thickness direction of the semiconductor film, the impurity concentration of the channel region is discontinuous at a boundary between the semiconductor film and the base film, and an impurity concentration of the base film is lower than an impurity concentration of the semiconductor film and is monotonously decreased toward the TFT array substrate.

Abstract: A field effect transistor is produced on a substrate. A semiconductor material is deposited on a portion of a single crystal temporary material. At least part of the temporary material is removed. A portion of a conducting material is then formed above and beneath the portion of semiconductor material. A layer of an electrically insulating material is located between the portion of temporary material and the substrate.

Abstract: A transistor includes; at least two polycrystalline silicon layers disposed substantially parallel to each other, each polycrystalline silicon layer including a channel region and at least two high conductivity regions disposed at opposing sides of the channel region; a gate which corresponds to the channel region of the two polycrystalline silicon layers and which crosses the two polycrystalline silicon layers, and a gate insulating layer interposed between the gate and the two polycrystalline silicon layers, wherein low conductivity regions are disposed adjacent to one edge of the gate and are formed between the channel region and one high conductivity region of each polycrystalline silicon layer.

Abstract: Array substrates for use in TFT-LCDs and fabrication methods thereof. A transparent conductive layer, a first metal layer, a first insulating layer, a semiconductor layer, a second insulating layer and a sacrificial layer are sequentially formed on a substrate. With a first photomask, a photoresist layer with various thicknesses is formed on part of the sacrificial layer. Using the photoresist layer as an etching mask, a gate line having a gate, a channel layer on the gate, a gate pad at the end portion of the gate line, a pixel electrode and a source pad are defined. An insulating spacer is formed on the sidewalls of the gate and gate line. With a second photomask, a source line, source and drain are formed. The source pad connects the end portion of the source line. An array substrate is thus obtained with only two photomasks.

Abstract: Methods of forming thin film devices with different electrical characteristics on a substrate comprising a driver circuit region and a pixel region. A first and a second polysilicon pattern layers are formed on the driving circuit region and the pixel region of the substrate, respectively. A first ion implantation is performed on the second polysilicon pattern layer using a masking layer covering the first polysilicon pattern layer as an implant mask, such that the first polysilicon pattern layer has an impurity concentration different from the second polysilicon pattern layer. After removal of the masking layer, a gate dielectric layer and a gate are successively formed on each of the first and second polysilicon pattern layers and a source/drain region is subsequently formed in each of the first and second polysilicon pattern layers to define a channel region therein.

Abstract: The average film thickness of an amorphous silicon film formed on a substrate is measured. Then, the amorphous silicon film is irradiated with a laser beam to form a polysilicon film, and the grain size distribution of the polysilicon film is measured. An optimum value of energy density of laser beam irradiation is calculated on the basis of grain size values measured at two points A and B of the polysilicon film. Then, the average film thickness of an amorphous silicon film formed on a subsequent substrate is measured. A value of energy density of laser beam irradiation for the subsequent amorphous silicon film is calculated on the basis of the two average film thicknesses. Accordingly, a uniform polysilicon film of large grain sizes is formed on the whole surface of a large-size substrate to provide polysilicon TFTs in a large area.

Abstract: It is required that a line width of a wiring is prevented from being wider to be miniaturized when the wiring or the like is formed by a dropping method typified by an ink-jetting method. The invention provides a method for narrowing (miniaturizing) a line width according to a method different from a conventional method. One feature of the invention is that a plasma treatment is performed before forming a wiring or the like by a dropping method typified by an ink-jetting method. As the result of the plasma treatment, a surface for forming a conductive film is modified to be liquid-repellent. Consequently, a wiring or the like formed by a dropping method can be miniaturized.

Abstract: A method for controlling silver doping of a chalcogenide glass in a resistance variable memory element is disclosed herein. The method includes forming a thin metal containing layer having a thickness of less than about 250 Angstroms over a second chalcogenide glass layer, formed over a first metal containing layer, formed over a first chalcogenide glass layer. The thin metal containing layer preferably is a silver layer. An electrode may be formed over the thin silver layer. The electrode preferably does not contain silver.

Abstract: A manufacturing method of thin film transistor array substrate is provided. A substrate, whereon first, second, and third poly-silicon islands, a gate insulating layer, a plurality of first, second, and third gates, and a first passivation layer have been formed, is provided. A third patterned photoresist layer is formed on the first passivation layer by using a third half-tone mask. A first ion implantation process is performed with the third patterned photoresist layer as mask to form first sources/drains. A portion of the thickness of the third patterned photoresist layer is removed, and then portions of the first passivation layer and the gate insulating layer are removed with the third patterned photoresist layer as mask to form the first patterned passivation layer. The third patterned photoresist layer is removed. First, second and third source/drain conductive layers, a second patterned passivation layer, and pixel electrodes are formed in sequence.

Abstract: Methods of forming a microelectronic structure are described. Those methods comprise implanting a first concentration of a species into an active area with a first energy, wherein the species pre-damages a portion of the active area, and then implanting a second concentration of the species into the active area with a second energy, wherein the total concentration of the species does not substantially penetrate an underlying channel region.

Abstract: A solid-state imaging device according to the present invention includes a semiconductor substrate; a photoelectric conversion portion formed on the semiconductor substrate; a gate insulating film formed on the semiconductor substrate and covering the photoelectric conversion portion; a vertical transfer portion for transferring a charge generated at the photoelectric conversion portion in a vertical direction; and a multilayer transfer gate electrode for transferring the charge of the vertical transfer portion. At least one layer of the multilayer transfer gate electrode is made of at least two impurity doped amorphous silicon films of different impurity concentration.

Abstract: A method for forming a self-aligned low temperature polysilicon thin film transistor (LTPS TFT). First, active layers of a N type LTPS TFT (NLTPS TFT) and a P type LTPS TFT (PLTPS TFT) are formed on a substrate, and a gate insulating (GI) layer is formed on the substrate. Then, a source electrode, a drain electrode, and lightly doped drains (LDD) of the NLTPS TFT are formed. Further, gate electrodes of the NLTPS TFT and the PLTPS TFT are formed on the gate insulating layer. Finally, the gate electrode of the PLTPS TFT is utilized to form a source electrode and a drain electrode in the active layer of the PLTPS TFT.