Lateral Single Gate Single Channel Transistor With Noninverted Structure, I.e., Channel Layer Is Formed Before Gate (epo) Patents (Class 257/E21.413)
  • Patent number: 10714024
    Abstract: It is an object of the present invention to provide a display device in which problems such as an increase of power consumption and increase of a load of when light is emitted are reduced by using a method for realizing pseudo impulsive driving by inserting an dark image, and a driving method thereof. A display device which displays a gray scale by dividing one frame period into a plurality of subframe periods, where one frame period is divided into at least a first subframe period and a second subframe period; and when luminance in the first subframe period to display the maximum gray scale is Lmax1 and luminance in the second subframe period to display the maximum gray scale is Lmax2, (½)Lmax2<Lmax1<( 9/10)Lmax2 is satisfied in the one frame period, is provided.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: July 14, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasunori Yoshida, Hajime Kimura
  • Patent number: 10658516
    Abstract: Disclosed is a thin film transistor, an array substrate, a method for manufacturing the same, and a display device. The method includes: forming a source and drain on a base substrate and forming a semiconductor layer. Between the step of forming the source and drain and the step of forming the semiconductor layer, the method further includes: forming a diffusion barrier layer. Metal atoms diffused from the source and drain and passing through the diffusion barrier layer react with a part of the semiconductor layer near the source and drain, and a metal transition layer containing metal silicide is formed.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: May 19, 2020
    Assignees: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectronics Technology Co., Ltd.
    Inventors: Junhao Han, Bingkun Yin, Jun Ma, Min Zhang
  • Patent number: 10657880
    Abstract: Disclosed herein is a display including: a pixel array part configured to include pixels that are arranged in a matrix and each have an electro-optical element, a write transistor for writing a video signal, a drive transistor for driving the electro-optical element based on the video signal written by the write transistor, and a holding capacitor connected between gate and source of the drive transistor, wherein the holding capacitor includes a first electrode, a second electrode disposed to face one surface of the first electrode for forming a first capacitor, and a third electrode disposed to face the other surface of the first electrode for forming a second capacitor, and the first capacitor and the second capacitor are connected in parallel to each other electrically.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: May 19, 2020
    Assignee: Sony Corporation
    Inventors: Hiroshi Sagawa, Katsuhide Uchino, Tetsuro Yamamoto
  • Patent number: 10615282
    Abstract: The present disclosure provides a method for manufacturing a thin-film transistor and a thin-film transistor manufactured thereby, an array substrate and a display apparatus. The method comprises: forming a first layer; forming at least one etch stopper over the first layer; forming a second layer over the first layer and the at least one etch stopper; forming at least one contact via in the second layer, such that a bottom opening of each contact via contacts with a top surface of one etch stopper; and forming at least one electrode in the at least one contact via, such that each electrode extends in one contact via respectively, and is in contact with, and electrically coupled with, the one etch stopper. The at least one etch stopper comprises a composition.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: April 7, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Huijuan Zhang, Chienhung Liu
  • Patent number: 10573698
    Abstract: A transistor including a polysilicon layer on a base substrate and including a channel region, a first ion doping region, a second ion doping region, the channel region being between the first and second ion doping regions, an average size of the grains in the channel region being greater than that of the grains in the first and second ion doping regions, a first gate electrode insulated from and overlapping the channel region, a second gate electrode insulated from the first gate electrode and overlapping the channel region, an inter-insulating layer on the second gate electrode, a source electrode on the inter-insulating layer and connected to the first ion doping region, and a drain electrode on the inter-insulating layer and connected to the second ion doping region.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: February 25, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kyoungwon Lee, Yoonho Khang, Myounggeun Cha, Youngki Shin, Woonghee Jeong
  • Patent number: 10516058
    Abstract: The present invention discloses a preparation method of a low temperature polysilicon thin film transistor including: successively forming a polysilicon active layer and a gate insulating layer covering the active layer on a base substrate; implanting nitrogen ions on a surface of the polysilicon active layer facing the gate insulating layer by an ion implantation process to form an ion implantation layer; and recrystallizing the ion implantation layer by a high temperature annealing process to form a silicon nitride spacing layer between the polysilicon active layer and the gate insulating layer.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: December 24, 2019
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Donghui Xiao
  • Patent number: 10490660
    Abstract: A thin film transistor (TFT), a method of manufacturing the TFT, and a display apparatus including the TFT, the TFT including a substrate; a semiconductor layer on the substrate, the semiconductor layer including a channel region, a lightly doped drain (LDD) region, a source region, and a drain region; a gate insulating layer covering the semiconductor layer; a gate electrode overlapping with the channel region such that the gate insulating layer is interposed between the gate electrode and the channel region; and an organic side wall layer on a side surface of the gate electrode, wherein the organic side wall layer includes a silsesquioxane resin.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: November 26, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Gwangmin Cha, Jungsoo Lee, Junhong Park, Hyuneok Shin
  • Patent number: 10276428
    Abstract: A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zi-Jheng Liu, Chen-Cheng Kuo, Hung-Jui Kuo
  • Patent number: 10263059
    Abstract: A light emitting device is provided which can prevent a change in gate voltage due to leakage or other causes and at the same time can prevent the aperture ratio from lowering. A capacitor storage is formed from a connection wiring line, an insulating film, and a capacitance wiring line. The connection wiring line is formed over a gate electrode and an active layer of a TFT of a pixel, and is connected to the active layer. The insulating film is formed on the connection wiring line. The capacitance wiring line is formed on the insulating film This structure enables the capacitor storage to overlap the TFT, thereby increasing the capacity of the capacitor storage while keeping the aperture ratio from lowering. Accordingly, a change in gate voltage due to leakage or other causes can be avoided to prevent a change in luminance of an OLED and flickering of screen in analog driving.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: April 16, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Tatsuya Arao, Munehiro Azami
  • Patent number: 10249734
    Abstract: A poly-silicon thin film transistor and its manufacturing method, an array substrate and its manufacturing method, and a display device are provided. The method for manufacturing a poly-silicon thin film transistor includes forming a poly-silicon layer on a base substrate so that the poly-silicon layer includes a first poly-silicon area, second poly-silicon areas located at the both sides of the first poly-silicon area and third poly-silicon areas located at a side of the second poly-silicon areas away from the first poly-silicon area; forming a barrier layer between a gate electrode and a gate insulation layer by a dry etching method so that the barrier layer corresponds to the first poly-silicon area; and with the barrier layer as a mask doping the second poly-silicon areas to form lightly doped areas. By this method, the lightly doped areas may have the same length, and thus the problem of excessive leakage current is avoided.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: April 2, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xiaohui Jiang, Jiaxiang Zhang
  • Patent number: 10181481
    Abstract: A display device includes a driver circuit including a logic circuit including a first transistor which is a depletion type transistor and a second transistor which is an enhancement type transistor; a signal line which is electrically connected to the driver circuit; a pixel portion including a pixel whose display state is controlled by input of a signal including image data from the driver circuit through the signal line; a reference voltage line to which reference voltage is applied; and a third transistor which is a depletion type transistor and controls electrical connection between the signal line and the reference voltage line. The first to the third transistors each include an oxide semiconductor layer including a channel formation region.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: January 15, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Shunpei Yamazaki
  • Patent number: 10139667
    Abstract: Provided are a color filter substrate provided with an inorganic cover layer and a display panel including the same. The color filter (CF) substrate includes a base substrate; a black matrix and a pixel resin layer both formed on the base substrate; a planarization layer formed on the black matrix and the pixel resin layer; and an inorganic cover layer formed on the planarization layer.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: November 27, 2018
    Assignees: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectronics Technology Co., Ltd.
    Inventors: Haibin Yin, Sang Man Yuk, Bin Li, Wenhao Tang, Tao Zhu, Qun Fang, Huifang Yuan, Anxin Dong, Jian Chen, Guoqiang Zhong, Xinxin Fu
  • Patent number: 10120256
    Abstract: Preparation method for a thin film transistor, preparation method for an array substrate, an array substrate, and a display apparatus are provided. The preparation method for a thin film transistor includes: forming, on a pattern of a semiconductor layer, a first photoresist pattern including a photoresist with two different thicknesses, and performing a heavily-doped ion implantation process on the pattern of the semiconductor layer by using the first photoresist pattern as a barrier mask; ashing the first photoresist pattern to remove the photoresist with a second thickness and to thin the photoresist with a first thickness, so as to form a second photoresist pattern; and performing a lightly-doped ion implantation process on the pattern of the semiconductor layer by using the second photoresist pattern as a barrier mask.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: November 6, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Lulu Ye, Huafeng Liu, Jingping Lv, Lei Yang, Meng Yang, Kai Zhang, Chao Wang, Chaochao Sun, Shengwei Zhao
  • Patent number: 10114259
    Abstract: The disclosure discloses an array substrate, a liquid crystal display panel and a manufacturing method, the array substrate includes designing a data line layer and a light shield layer on a same layer, moreover, a source electrode layer, a drain electrode layer, an oxide semiconductor layer and a common electrode layer are designed on a same layer, the source electrode layer, the drain electrode layer and the common electrode layer are formed by doping the oxide semiconductor material, the source electrode layer, the drain electrode layer and the common electrode layer can be conductive by increasing conductivity thereof. By the method above, the disclosure can reduce the amount of masks in processes and costs in production significantly.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: October 30, 2018
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd
    Inventor: Yingtao Xie
  • Patent number: 10020328
    Abstract: The present disclosure provides a test element unit, an array substrate, a display panel, a display apparatus and a corresponding manufacturing method. The test element unit includes: a plurality of layers of test patterns, each layer of test pattern including at least one test block and at least one capacitor being formed between test blocks located in different layers, and, two electrodes of each of capacitors being two test blocks located in different layers, respectively, so that it can determined whether or not corresponding components and devices formed in the display region meet requirements by detecting the test patterns formed in the test region.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: July 10, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yu-Cheng Chan, Shuai Zhang, Qi Liu
  • Patent number: 10013923
    Abstract: It is an object of the present invention to provide a display device in which problems such as an increase of power consumption and increase of a load of when light is emitted are reduced by using a method for realizing pseudo impulsive driving by inserting an dark image, and a driving method thereof. A display device which displays a gray scale by dividing one frame period into a plurality of subframe periods, where one frame period is divided into at least a first subframe period and a second subframe period; and when luminance in the first subframe period to display the maximum gray scale is Lmax1 and luminance in the second subframe period to display the maximum gray scale is Lmax2, (½) Lmax2<Lmax1<( 9/10) Lmax2 is satisfied in the one frame period, is provided.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: July 3, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasunori Yoshida, Hajime Kimura
  • Patent number: 9916793
    Abstract: To reduce the effect of external light and to improve the accuracy of detecting the location of a touch. In an image-capture period, light emission from a self-light-emitting element is controlled, and imaging data at the time of displaying white on a display screen and imaging data at the time of displaying black on the display screen are output from each sensor pixel. The location of a sensor pixel where a difference between the two pieces of imaging data output from the same sensor pixel is the greatest is detected. Thus, the location of a touch of the object on the display screen is detected with high accuracy. By utilizing a difference between imaging data at the time of reverse display, the effect of external light can be reduced.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: March 13, 2018
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Munehiro Kozuma, Takayuki Ikeda, Yoshiyuki Kurokawa, Hikaru Tamura, Takeshi Aoki
  • Patent number: 9893286
    Abstract: The present invention provides an organic single crystal field effect circuit and method for preparing the same.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: February 13, 2018
    Assignee: Northeast Normal University
    Inventors: Qingxin Tang, Yichun Liu, Yanhong Tong, Xiaoli Zhao
  • Patent number: 9893165
    Abstract: Embodiments of the present invention disclose a manufacturing method for an array substrate and corresponding manufacturing device, which belong to the technical field of metal oxide semiconductor.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: February 13, 2018
    Assignee: Boe Technology Group Co., Ltd.
    Inventors: Jianbang Huang, Yucheng Chan, Chienhung Liu
  • Patent number: 9880431
    Abstract: According to one embodiment, a display device includes a stacked conductive layer. The stacked conductive layer includes a first conductive layer formed of material containing aluminum, and a second conductive layer provided on the first conductive layer, formed of material different from material of which the first conductive layer is formed, and having a higher visible-light absorptivity than that of the first conductive layer. The first conductive layer includes a side wall formed of an oxide film.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: January 30, 2018
    Assignee: Japan Display Inc.
    Inventors: Daisuke Sonoda, Tatsuya Ide, Rintaro Makino
  • Patent number: 9876025
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings are formed through the alternating stack to the substrate. After formation of memory film layers, a sacrificial cover material layer can be employed to protect the tunneling dielectric layer during formation of a bottom opening in the memory film layers. An amorphous semiconductor material layer can be deposited and optionally annealed in an ambient including argon and/or deuterium to form a semiconductor channel layer having a thickness less than 5 nm and surface roughness less than 10% of the thickness. Alternately or additionally, at least one interfacial layer can be employed on either side of the amorphous semiconductor material layer to reduce surface roughness of the semiconductor channel. The ultrathin channel can have enhanced mobility due to quantum confinement effects.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: January 23, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Peter Rabkin, Jayavel Pachamuthu, Masaaki Higashitani, Johann Alsmeier
  • Patent number: 9842935
    Abstract: The present disclosure discloses a LTPS TFT and the manufacturing method thereof. The method includes: forming a semiconductor layer and a LTPS layer on the same surface on a base layer; forming an oxide layer is formed on one side of the semiconductor layer facing away the base layer, and forming the oxide layer on one side of the LTPS layer facing away the base layer; forming a first photoresist layer of a first predetermined thickness on the oxide layer; arranging a corresponding first cobalt layer on each of the photoresist layers, a vertical projection of the first cobalt layer overlaps with the vertical projection of the corresponding first photoresist layer; doping high-concentration doping ions into a first specific area of the semiconductor layer. With such configuration, the number of the masking process is decreased and the manufacturing time is reduced.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: December 12, 2017
    Assignees: Shenzhen China Star Optoelectronics Technology Co., Ltd, WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD
    Inventor: Changming Lu
  • Patent number: 9837551
    Abstract: Provided is a semiconductor device that can be miniaturized in a simple process and that can prevent deterioration of electrical characteristics due to miniaturization. The semiconductor device includes an oxide semiconductor layer, a first conductor in contact with the oxide semiconductor layer, and an insulator in contact with the first conductor. Further, an opening portion is provided in the oxide semiconductor layer, the first conductor, and the insulator. In the opening portion, side surfaces of the oxide semiconductor layer, the first conductor, and the insulator are aligned, and the oxide semiconductor layer and the first conductor are electrically connected to a second conductor by side contact.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: December 5, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Suguru Hondo, Kazuya Hanaoka, Shinya Sasagawa, Naoto Kusumoto
  • Patent number: 9832559
    Abstract: An apparatus includes a first interface for connecting to a personal computer, a second interface for connecting to a communications device, a third interface for connecting to a headset, a fourth interface for connecting to a speaker, and a processor in control of each of the interfaces. The processor is configured to route audio associated with a communications session on one of the personal computer or the communications device to the speaker, and in response to a user putting on the headset, re-route the audio to the headset.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: November 28, 2017
    Assignee: Bose Corporation
    Inventors: Joseph M. Geiger, Muhammad Masood, Daniel M. Gauger, Jr.
  • Patent number: 9812577
    Abstract: A semiconductor structure and a method of fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate; a metal gate structure on the substrate; and a spacer next to the metal gate structure having a skirting part extending into the metal gate structure and contacting the substrate. The metal gate structure includes a high-k dielectric layer and a metal gate electrode on the high-k dielectric layer.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: November 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Tung-Wen Cheng, Chang-Yin Chen, Mu-Tsang Lin
  • Patent number: 9773892
    Abstract: A representative fin field effect transistor (FinFET) includes a substrate having a major surface; a fin structure protruding from the major surface having a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material. A bottom portion of the upper portion comprises a dopant with a first peak concentration. A middle portion is disposed between the lower portion and upper portion, where the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant. An isolation structure surrounds the fin structure, where a portion of the isolation structure adjacent to the bottom portion of the upper portion comprises the dopant with a second peak concentration equal to or greater than the first peak concentration.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: September 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Guan-Lin Chen, Chao-Hsiung Wang, Chi-Wen Liu
  • Patent number: 9768309
    Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: September 19, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yong Su Lee, Yoon Ho Khang, Dong Jo Kim, Hyun Jae Na, Sang Ho Park, Se Hwan Yu, Chong Sup Chang, Dae Ho Kim, Jae Neung Kim, Myoung Geun Cha, Sang Gab Kim, Yu-Gwang Jeong
  • Patent number: 9768203
    Abstract: The present invention provides a TFT arrangement structure, comprising a first thin film transistor (T1) and a second thin film transistor (T2) controlled by the same control signal line; the first active layer (SC1) of the first thin film transistor (T1) and the second active layer (SC2) of the second thin film transistor (T2) are at different layers, and positioned to stack up in space, and the first source (S1) and the first drain (D1) of the first thin film transistor (T1) contact the first active layer (SC1), and the second source (S2) and the second drain (D2) of the second thin film transistor (T2) contact the second active layer (SC2); the bottom gate layer (Bottom Gate) of the first thin film transistor (T1) is positioned under the first active layer (SC1), and the top gate layer (Top Gate) of the second thin film transistor (T2) is above the second active layer (SC2).
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: September 19, 2017
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Baixiang Han, Longqiang Shi
  • Patent number: 9768244
    Abstract: A semiconductor device includes a first electrode layer and a second electrode layer. The first electrode layer extends in a first direction. The second electrode layer extends in the first direction for a different length from the first electrode layer, and is symmetric with respect to a center line of the first electrode layer in a second direction. The second electrode layer defines a capacitor with the first electrode layer.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: September 19, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Ming Chyi Liu
  • Patent number: 9747408
    Abstract: The present disclosure provides an integrated circuit (IC) method in accordance with some embodiments. The method includes receiving an IC design layout; and performing an inverse beam technology (IBT) process to the IC design layout, thereby generating a final mask pattern, wherein the IBT process uses a single IBT model to simulate both a mask making process and a wafer making process.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: August 29, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsu-Ting Huang, Ru-Gun Liu, Shuo-Yen Chou, Tsai-Sheng Gau
  • Patent number: 9704976
    Abstract: An object is to provide a thin film transistor using an oxide semiconductor layer, in which contact resistance between the oxide semiconductor layer and source and drain electrode layers is reduced and electric characteristics are stabilized. The thin film transistor is formed in such a manner that a buffer layer including a high-resistance region and low-resistance regions is formed over an oxide semiconductor layer, and the oxide semiconductor layer and source and drain electrode layers are in contact with each other with the low-resistance region of the buffer layer interposed therebetween.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: July 11, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuji Asano, Junichi Koezuka
  • Patent number: 9680026
    Abstract: A semiconductor device that can operate at high speed or having high strength against stress is provided. One embodiment of the present invention is a semiconductor device including a semiconductor film including a channel formation region and a pair of impurity regions between which the channel formation region is positioned; a gate electrode overlapping side and top portions of the channel formation region with an insulating film positioned between the gate electrode and the side and top portions; and a source electrode and a drain electrode in contact with side and top portions of the pair of impurity regions.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: June 13, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9646999
    Abstract: The present disclosure proposes a TFT. The source and the drain of the TFT are disposed on the same side as the gate. The gate includes a first buffer layer, a first copper layer, a second copper layer and a second buffer layer that are stacked from bottom to top, and the second buffer layer is disposed on the side that is close to the source and drain. The source and drain include a first buffer layer, a first copper layer, a second copper layer and a second buffer layer that are stacked, and the first buffer layer is disposed on the side that is close to the gate. The first copper layer is deposited by a first power, the second copper layer is deposited by a second power lower than the first power. Through the above method, it is prevents photoresist from shedding when etching.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: May 9, 2017
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Zhichao Zhou, Yue Wu
  • Patent number: 9633844
    Abstract: Embodiments of the present invention provide a method for forming a low temperature polysilicon thin film. The method for forming the low temperature polysilicon thin film can include: depositing a buffer layer and an amorphous silicon layer on a substrate in this order; heating the amorphous silicon layer; performing an excimer laser annealing process on the amorphous silicon layer to form a polysilicon layer; oxidizing partially the polysilicon layer so as to form an oxidation portion at an upper portion of the polysilicon layer; and removing the oxidation portion of the polysilicon layer to form a polysilicon thin film.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: April 25, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xueyan Tian, Chunping Long, Jiangfeng Yao
  • Patent number: 9627543
    Abstract: The present disclosure provides a TFT, a method for manufacturing the same, an array substrate and a display device, so as to effectively reduce a TFT edge leakage current IOFF (edge). The TFT includes an active layer and a silicon oxide layer arranged at a lateral side of the active layer.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: April 18, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Zhenyu Xie
  • Patent number: 9620579
    Abstract: An organic light-emitting display apparatus includes a substrate; an active layer; a gate electrode, source and drain electrodes; a first insulating layer disposed between the active layer and the gate electrode; a second insulating layer disposed between the gate electrode and the source and drain electrodes; a third insulating layer disposed over the source and drain electrodes; conductive layers disposed over the third insulating layer and electrically connected to the source and drain electrodes through the third insulating layer; a first line disposed over the second insulating layer and formed of the same material as the source and drain electrodes; a second line overlapping the first line, disposed over the third insulating layer, and formed of the same material as the conductive layer; a fourth insulating layer disposed over the third insulating layer to cover the conductive layer; and an organic light-emitting diode disposed over the fourth insulating layer.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: April 11, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Nayoung Kim, Jungbae Kim
  • Patent number: 9614115
    Abstract: Provided is a semiconductor device that can suppress a leakage current more than has been achieved before. A semiconductor device 22 includes a first carrier holding layer 48, which is arranged on a lower electrode 47, is in contact with a lower electrode 47 via a first interface 49, and includes majority carriers of one type, and a second carrier holding layer 57, which is arranged on the first carrier holding layer 48, defines a second interface 58 constituting a conduction path to the first carrier holding layer 48, and includes majority carriers of the other type. The first interface 49 has its outline within the outline of the first carrier holding layer 48 when seen in a plan view in a direction that is orthogonal to a surface of the substrate, and the second interface 58 has its outline within the outline of the first carrier holding layer 48 when seen in the plan view.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: April 4, 2017
    Assignee: Seiko Epson Corporation
    Inventor: Manabu Kudo
  • Patent number: 9607898
    Abstract: Forming a semiconductor layer on a semiconductor substrate, a top surface of the semiconductor layer above a fin in a second region is higher than a top surface of the semiconductor layer in a first region, etching the semiconductor layer and a mask in the first region to expose a top surface of the semiconductor substrate to form a first stack, and etching the semiconductor layer and the mask in the second region to expose a top surface of the fin to form a second stack, epitaxially growing a semiconductor material on a top surface of the fin not covered by the second stack, recessing the first and second stack to expose a top surface of the semiconductor layer, a portion of the mask remains above the semiconductor layer in the first stack, top surfaces of each of the first and second stacks each are substantially flush with one another.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Charan V. V. S. Surisetty
  • Patent number: 9570593
    Abstract: A variation in electrical characteristics, such as a negative shift of the threshold voltage or an increase in S value, of a fin-type transistor including an oxide semiconductor material is prevented. An oxide semiconductor film is sandwiched between a plurality of gate electrodes with an insulating film provided between the oxide semiconductor film and each of the gate electrodes. Specifically, a first gate insulating film is provided to cover a first gate electrode, an oxide semiconductor film is provided to be in contact with the first gate insulating film and extend beyond the first gate electrode, a second gate insulating film is provided to cover at least the oxide semiconductor film, and a second gate electrode is provided to be in contact with part of the second gate insulating film and extend beyond the first gate electrode.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: February 14, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsuo Isobe
  • Patent number: 9543415
    Abstract: The embodiments of the present invention provide a thin film transistor driving backplane and a manufacturing method thereof, and a display panel. The manufacturing method may comprise: manufacturing a backplane base disposed with a plurality of active device structures; disposing an electrode layer on the backplane base; and manufacturing the electrode layer into a source electrode, a drain electrode and a pixel electrode integrally disposed with the drain electrode by one patterning process.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: January 10, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zuqiang Wang, Chien Hung Liu
  • Patent number: 9528194
    Abstract: Structures, devices and methods are provided for forming nanowires on a substrate. A first protruding structure is formed on a substrate. The first protruding structure is placed in an electrolytic solution. Anodic oxidation is performed using the substrate as part of an anode electrode. One or more nanowires are formed in the protruding structure. The nanowires are surrounded by a first dielectric material formed during the anodic oxidation.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: December 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited & National Taiwan University
    Inventors: Jenn-Gwo Hwu, Wei-Cheng Tian, Po-Hao Tseng
  • Patent number: 9524668
    Abstract: An AMOLED driving circuit, a driving method and a display device, wherein a control unit is connected to a data line and a control line, and is connected to a driving unit via first, second and third nodes; a charging unit is connected to the driving unit via the first node, and is connected to a first power source; the driving unit is connected to one end of a light emitting device, and is connected to the first power source; the other end of the light emitting device is connected to a second power source. The control unit controls a current so as to charge the charging unit through the driving unit, and controls the charging unit so as to supply a voltage to the driving unit through the first node, so that the driving unit is driven by the voltage and drives the light emitting device to emit light.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: December 20, 2016
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Wen Tan, Xiaojing Qi
  • Patent number: 9508620
    Abstract: It is an object of the present invention to provide a peeling method that causes no damage to a layer to be peeled and to allow not only a layer to be peeled with a small surface area but also a layer to be peeled with a large surface area to be peeled entirely. Further, it is also an object of the present invention to bond a layer to be peeled to various base materials to provide a lighter semiconductor device and a manufacturing method thereof. Particularly, it is an object to bond various elements typified by a TFT, (a thin film diode, a photoelectric conversion element comprising a PIN junction of silicon, or a silicon resistance element) to a flexible film to provide a lighter semiconductor device and a manufacturing method thereof.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: November 29, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Junya Maruyama, Yumiko Ohno
  • Patent number: 9496412
    Abstract: The transistor includes a gate electrode, a gate insulating film over the gate electrode, an oxide semiconductor film over the gate insulating film, a source electrode and a drain electrode electrically connected to the oxide semiconductor film. The oxide semiconductor film includes a first oxide semiconductor film on the gate electrode side and a second oxide semiconductor film over the first oxide semiconductor film. The first oxide semiconductor film includes a first region in which an atomic proportion of In is larger than that of M (M is Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf). The second oxide semiconductor film includes a second region in which an atomic proportion of In is smaller than that of the first oxide semiconductor film. The second region includes a portion thinner than the first region.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: November 15, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Kenichi Okazaki, Daisuke Kurosaki, Yukinori Shima, Yasuharu Hosaka
  • Patent number: 9484430
    Abstract: A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: November 1, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wilfried E. Haensch, Bahman Hekmatshoar-Tabari, Ali Khakifirooz, Tak H. Ning, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 9472649
    Abstract: A method of fabricating a multi-zone, short gate length thin film transistor is provided. Gate metal and a plurality of layers are deposited on a substrate. The layers include a gate insulator, a first semiconductor, a second semiconductor, and source contact metal. An insulator is deposited on the plurality of layers partially overlapping the gate electrode and masking part of the plurality of layers. Portions of the source contact metal not masked by the insulator are removed and the first and second semiconductors are diffused with dopants via a plasma. Sidewalls of the insulator and source metal contact are covered with an insulating layer. Portions of the second semiconductor not masked are removed by etching for a length of time to create undercuts below the insulator and extending under the source contact metal. The undercuts are filled with an insulating material and an external metal contact layer is deposited.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: October 18, 2016
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Burhan Bayraktaroglu, Kevin D Leedy
  • Patent number: 9461161
    Abstract: Integrated circuits with memory circuitry are provided. The memory circuitry may include memory cell transistors and associated pass transistors. The memory cell transistors and the pass transistors may be formed using multiple strips of oxide definition (OD) regions coupled in parallel. The multiple OD strips may have reduced widths. The ratio of the distance from adjacent OD strips to a given OD strip to the width of the given OD strip may be at least 0.5. Forming memory circuitry transistors using this multi-strip arrangement may provide increased levels of stress that improve transistor performance. Each OD strip may have a reduced width that still satisfies fabrication design rules. Forming OD regions having reduced width allows the pass transistors to be overdriven at higher voltage levels to further improve transistor performance.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: October 4, 2016
    Assignee: Altera Corporation
    Inventors: Jun Liu, Qi Xiang
  • Patent number: 9356153
    Abstract: A thin film transistor includes a bottom gate electrode, a top gate electrode and an active pattern. The top gate electrode includes a transparent conductive material and overlaps with the bottom gate electrode. A boundary of the bottom gate electrode and a boundary of the top gate electrode are coincident with each other in a cross-sectional view. The active pattern includes a source portion, a drain portion and a channel portion disposed between the source portion and the drain portion. The channel portion overlaps with the bottom gate electrode and the top gate electrode.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: May 31, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yoon-Ho Khang, Dong-Jo Kim, Su-Hyoung Kang, Yong-Su Lee
  • Patent number: 9263537
    Abstract: One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned above the substrate and around the spacer structure, a gate cap layer positioned above the gate structure and the spacer structure, and a gate cap protection material that encapsulates the gate cap layer, wherein portions of the gate cap protection material are positioned between the gate cap layer and the gate structure, the spacer structure and the layer of insulating material.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: February 16, 2016
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Daniel Pham, Xiuyu Cai, Balasubramanian Pranatharthiharan, Pranita Kulkarni
  • Patent number: RE45989
    Abstract: A semiconductor device includes a semiconductor layer stack 13 formed on a substrate 11 and having a channel region, a first electrode 16A and a second electrode 16B formed spaced apart from each other on the semiconductor layer stack 13, a first gate electrode 18A formed between the first electrode 16A and the second electrode 16B, and a second gate electrode 18B formed between the first gate electrode 18A and the second electrode 16B. A first control layer 19A having a p-type conductivity is formed between the semiconductor layer stack 13 and the first gate electrode 18A.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: April 26, 2016
    Assignee: PANASONIC CORPORATION
    Inventors: Tatsuo Morita, Manabu Yanagihara, Hidetoshi Ishida, Yasuhiro Uemoto, Hiroaki Ueno, Tsuyoshi Tanaka, Daisuke Ueda