Abstract: A method of manufacturing a display device, including: providing an object to be processed; forming a linear portion of the object to be processed by performing a first laser processing for the object to be processed; and forming a curved portion of the object to be processed by performing a second laser processing different from the first laser processing for the object to be processed. A laser processing apparatus, is also provided, including: an irradiation unit applying a laser onto an object to be processed; and a controller controlling an operation of the irradiation unit. The controller controls the irradiation unit to form a linear portion of the object to be processed by applying the laser onto the object according to a first condition and forming a curved portion of the object by applying the laser onto the object according to a second condition different from the first condition.

Abstract: The disclosure provides a displaying substrate, a manufacturing method thereof, and a display panel, and relates to the technical field of display. The displaying substrate comprises a first supporting base (1), plurality of vibrating element modules (2), and a display module (3). The display module (3) comprises display units (31), connecting units (32) and hollowed-out units (33). Each connecting unit (32) is located between two adjacent display units (31). Each hollowed-out unit (33) is located between two adjacent display units (31) except an area where the corresponding connecting unit (32) is located. The hollowed-out units (33) are provided with cavities (40) corresponding to the vibrating element modules (2). Orthographic projections of the hollowed-out units (33) on a reference plane cover orthographic projections of the vibrating element modules (2) on the reference plane. The vibrating element modules (2) and the cavities (40) form a transducer.

Abstract: Methods for forming a nickel silicide material on a substrate are disclosed. The methods include depositing a first nickel silicide seed layer atop a substrate at a temperature of about 15° C. to about 27° C., annealing the first nickel silicide seed layer at a temperature of 400° C. or less such as over 350° C.; and depositing a second nickel silicide layer atop the first nickel silicide seed layer at a temperature of about 15° C. to about 27° C. to form the nickel silicide material.

Abstract: According to one embodiment, a display device includes a display panel including a display area for displaying an image, and the display panel includes an insulating substrate, a first electrode, a first organic insulating layer, an inorganic insulating layer, a pixel electrode, a second organic insulating layer, and a pad portion. The inorganic insulating layer includes a first opening for electrically connecting the first electrode to the pixel electrode. The second organic insulating layer includes a second opening for electrically connecting the pixel electrode to the pad portion. The pixel electrode is formed of a transparent conductive material.

Abstract: A semiconductor device includes a substrate having an insulating surface; a light-transmitting first electrode provided over the substrate; a light-transmitting second electrode provided over the substrate; a light-transmitting semiconductor layer provided so as to be electrically connected to the first electrode and the second electrode; a first wiring electrically connected to the first electrode; an insulating layer provided so as to cover at least the semiconductor layer; a light-transmitting third electrode provided over the insulating layer in a region overlapping with the semiconductor layer; and a second wiring electrically connected to the third electrode.

Abstract: A display panel is provided including a substrate including a display area comprising first pixels and a sensor area including second pixels and a transmission portion. A display element layer is disposed on the substrate, the display element layer comprising the first pixels electrically connected to a first thin film transistor and the second pixels electrically connected to a second thin film transistor. A conductive layer is disposed between the second thin film transistor and the substrate, the conductive layer having two or more steps at an edge thereof.

Abstract: Provided are a thin film transistor, a display device, and a thin film transistor manufacturing method, in which variation in characteristics is small. The present invention is provided with: a gate electrode formed on a substrate; a gate insulation film formed so as to cover the gate electrode; a semiconductor layer which is formed on the upper side of the gate insulation film and which includes a polysilicon layer disposed, in a plan view, inside a region defined by the gate electrode; an etching stopper layer disposed on the upper side of the polysilicon layer; and a source electrode and a drain electrode provided on the semiconductor layer so as to be separated from each other, wherein the polysilicon layer has first and second regions which are not covered with the etching stopper layer, and a part of the source electrode exists above the first region and a part of the drain electrode exists above the second region.

Abstract: Apparatus and methods for improving film uniformity in a physical vapor deposition (PVD) process are provided herein. In some embodiments, a PVD chamber includes a pedestal disposed within a processing region of the PVD chamber, the pedestal having an upper surface configured to support a substrate thereon, a first motor coupled to the pedestal, a lid assembly comprising a first target, a first magnetron disposed over a portion of the first target, and in a region of the lid assembly that is maintained at atmospheric pressure, a first actuator configured to translate the first magnetron in a first direction, a second actuator configured to translate the first magnetron in a second direction, and a system controller that is configured to cause the first magnetron to translate along at least a portion of a first path by causing the first actuator and second actuator to simultaneously translate the first magnetron.

Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.

Abstract: An electroluminescent display including pixels arranged in a matrix is disclosed. Each pixel includes a pixel circuit configured to sample a threshold voltage of a driving element for driving a light emitting element and compensate for a data voltage. The pixel circuit includes a first switch element connected to a data voltage path supplied with the data voltage, a second switch element connected to a reference voltage path supplied with a predetermined reference voltage, a third switch element connected between a gate of the driving element and the first and second switch elements, a fourth switch element connected to an initialization voltage path supplied with a predetermined initialization voltage, and a fifth switch element connected to a power path supplied with a predetermined pixel driving voltage higher than the reference voltage and the initialization voltage.

Abstract: The present invention provides a photosensitive element, and a preparation method and a display device thereof. The photosensitive element includes a substrate; a first electrode arranged on the substrate; an N-type doped silicon layer arranged on the first electrode; an undoped silicon layer arranged on the N-type doped silicon layer; a molybdenum oxide layer arranged on the undoped silicon layer; an insulating layer arranged on the molybdenum oxide layer and the substrate, wherein a first opening is arranged on the insulating layer to expose the molybdenum oxide layer; and a second electrode arranged on the insulating layer and the molybdenum oxide layer, wherein the second electrode contacts the molybdenum oxide layer through the first opening.

Abstract: A display apparatus includes a first substrate, a second substrate, and a transistor. The first transistor includes a polymer resin. The second substrate is arranged between the first substrate and the transistor and includes a glass material. A liquidus temperature of the glass material is less than 1000° C. The transistor overlaps at least one of the first substrate and the second substrate and includes a semiconductor layer.

Abstract: Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.

Abstract: The present invention provides a highly integrated memory cell and a semiconductor device including the same. According to an embodiment of the present invention, the semiconductor device comprises: a plurality of active layers vertically stacked over a substrate; a plurality of bit lines connected to first ends of the active layers, respectively, and extended parallel to the substrate; line-shape air gaps disposed between the bit lines; a plurality of capacitors connected to second ends of the active layers, respectively; and a word line and a back gate facing each other with each of the active layers interposed therebetween, wherein the word line and the back gate are vertically oriented from the substrate.

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer, a carrier transit layer, a carrier supply layer, a gate, a source electrode and a drain electrode. The buffer layer is on a substrate. The carrier transit layer is on the buffer layer. The carrier supply layer is on the carrier transit layer. The gate is on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the gate, wherein each of the source electrode and the drain electrode includes a conductive layer and a conductive oxide layer stacked from bottom to top.

Abstract: A thin film transistor includes a gate, a gate insulating layer, an active layer, an ionized amorphous silicon layer, a source and a drain. The gate insulating layer covers the gate. The active layer is disposed on a side of the gate insulating layer away from the gate. The ionized amorphous silicon layer is disposed on a side of the active layer away from the gate, and the ionized amorphous silicon layer is in contact with the gate insulating layer. The source and the drain are disposed on a side of the ionized amorphous silicon layer away from the gate insulating layer, and the source and the drain are coupled to the active layer through the ionized amorphous silicon layer.

Abstract: A semiconductor device including a contact structure is provided. The semiconductor device includes an isolation region defining a lower active region. First and second source/drain regions and first and second gate electrodes are on the lower active region. The first and second source/drain regions are adjacent to each other. First and second gate capping patterns are on the first and second gate electrodes, respectively. First and second contact structures are on the first and second source/drain regions, respectively. A lower insulating pattern is between the first and second source/drain regions. An upper insulating pattern is between the first and second contact structures. Silicon oxide has etching selectivity with respect to an insulating material which the upper insulating pattern, the first gate capping pattern, and the second gate capping pattern are formed of.

Abstract: A body layer formed of a semiconductor layer, the body layer comprising, a first region, a second region, and a channel region positioned therebetween; a channel stopper formed on the channel region; source and drain electrodes electrically connected to the first and second regions via first and second contact layers respectively are provided. Each of the first and second contact layers comprises an impurities-containing first amorphous silicon layer; a thickness of each of the first and second regions is less than a thickness of the channel region; and the first and second regions comprise a second amorphous silicon layer containing impurities in a concentration being less than a concentration of impurities contained in the first amorphous silicon layer. This makes it possible to suppress a photoexcited current and improve the aperture ratio in a case that a display apparatus is configured.

Abstract: A method of forming a structure having a coating layer includes the following steps: providing a substrate; coating a fluid on the surface of the substrate, where the fluid includes a carrier and a plurality of silicon-containing nanoparticles; and performing a heating process to remove the carrier and convert the silicon-containing nanoparticles into a silicon-containing layer, a silicide layer, or a stack layer including the silicide layer and the silicon-containing layer.

Abstract: A manufacturing method of a display device includes: forming a transistor on a substrate; forming an organic insulating layer on the transistor; and performing a plasma treatment on the organic insulating layer. The organic insulating layer includes an acryl-based polymer, and the plasma treatment is performed by using helium gas or argon gas.

Abstract: A method of manufacturing a semiconductor device according to the present disclosure includes forming a stack by alternately stacking insulating films and sacrificial films on a substrate; forming, in the stack, a through-hole extending in a thickness direction of the stack; forming a block insulating film, a charge trapping film, a tunnel insulating film, and a channel film on an inner surface of the through-hole in this order; forming, in the stack, a slit extending in the thickness direction of the stack separately from the through-hole; removing the sacrificial films through the slit so as to form a recess between adjacent insulating films; forming a first metal oxide film on an inner surface of the recess; forming, on the first metal oxide film, a second metal oxide film having a crystallization temperature lower than that of the first metal oxide film; and filling the recess with an electrode layer.

Abstract: An electronic device and a manufacturing method thereof are provided. The electronic device includes an array substrate, which includes a substrate, a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer. The substrate has a substrate surface. The first conductive layer is located on the substrate surface. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer and includes a first sputtering layer, a second sputtering layer, and a third sputtering layer. The second insulating layer is located on the second conductive layer. The second sputtering layer is located between the first and third sputtering layers, and includes a first metal element. The first sputtering layer includes the first metal element and a second metal element. The third sputtering layer includes the first metal element and a third metal element.

Abstract: A thin film transistor (TFT) substrate includes a TFT on the substrate. The TFT includes an active patterned layer which is made of a polycrystalline silicon, which includes a channel portion, a source portion and a drain portion, and in which protrusions are formed at boundaries between grains and recess spaces are formed between the protrusions. A barrier pattern film fills the recess spaces and forms a flat surface with the protrusions. A gate electrode is on a gate insulating layer located on the barrier pattern film and the protrusions and overlays or corresponds to the channel portion. A source electrode and a drain electrode are on the gate electrode and respectively contact the source portion and the drain portion.

Abstract: Provided is a display panel including a main display area, a component area having a transmissive area, a peripheral area outside the main display area, a substrate, a bottom metal layer on the substrate, and defining an opening corresponding to the transmissive area, a valley portion adjacent to a boundary between the bottom metal layer and the transmissive area, and a thin-film encapsulation layer on the valley portion, and including an inorganic layer and an organic layer.

Abstract: A panel comprises a substrate; a transistor disposed on the substrate and including: a source electrode, a drain electrode, a gate electrode, a gate insulation layer, an active layer, an auxiliary source electrode configured to electrically connect one end of the active layer to the source electrode, and an auxiliary drain electrode configured to electrically connect an other end of the active layer to the drain electrode; and a capacitor disposed on the substrate and including a first plate and a second plate. The first plate of the capacitor is made of a same material as the auxiliary source electrode and the auxiliary drain electrode.

Abstract: A vertical nanowire semiconductor device manufactured by a method of manufacturing a vertical nanowire semiconductor device is provided. The vertical nanowire semiconductor device includes a substrate, a first conductive layer in a source or drain area formed above the substrate, a semiconductor nanowire of a channel area vertically upright with respect to the substrate on the first conductive layer, wherein a crystal structure thereof is grown in <111> orientation, a second conductive layer of a drain or source area provided on the top of the semiconductor nanowire, a metal layer on the second conductive layer, a NiSi2 contact layer between the second conductive layer and the metal layer, a gate surrounding the channel area of the vertical nanowire, and a gate insulating layer located between the channel area and the gate.

Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, and a channel region vertically between the top and bottom source/drain regions. A gate is operatively laterally-adjacent the channel region. The top source/drain region, the bottom source/drain region, and the channel region respectively have crystal grains and grain boundaries between immediately-adjacent of the crystal grains. At least one of the bottom source/drain region and the channel region has an internal interface there-within between the crystal grains that are above the internal interface and the crystal grains that are below the internal interface. At least some of the crystal grains that are immediately-above the internal interface physically contact at least some of the crystal grains that are immediately-below the internal interface.

Abstract: Disclosed herein is a composite transistor which includes a first transistor TR1 including a control electrode, a first active region, a first A extending part, and a first B extending part, and a second transistor TR2 including a control electrode, a second active region, a second A extending part, and a second B extending part. The first active region, the second active region, and the control electrode overlap one another. Both the first A extending part and the first B extending part extend from the first active region and both the second A extending part and the second B extending part extend from the second active region. The first electrode is connected to the first A extending part, the second electrode is connected to the second A extending part, and the third electrode is connected to the first B extending part and the second B extending part.

Abstract: A panel comprises a substrate; a transistor disposed on the substrate and including: a source electrode, a drain electrode, a gate electrode, a gate insulation layer, an active layer, an auxiliary source electrode configured to electrically connect one end of the active layer to the source electrode, and an auxiliary drain electrode configured to electrically connect an other end of the active layer to the drain electrode; and a capacitor disposed on the substrate and including a first plate and a second plate. The first plate of the capacitor is made of a same material as the auxiliary source electrode and the auxiliary drain electrode.

Abstract: A method of manufacturing a display substrate may include the following steps: forming a drain electrode on a pixel area of a substrate; forming a pad electrode on a pad area of the substrate; forming an inorganic insulation layer that covers the drain electrode and the pad electrode; forming an organic insulation member that has a first thickness at the pixel area of the substrate, has a second thickness less than the first thickness at the pad area of the substrate, exposes a first portion of the inorganic insulation layer on the drain electrode, and exposes a second portion of the inorganic insulation layer on the pad electrode; removing the first portion of the inorganic insulation layer and the second portion of the inorganic insulation layer; and partially removing the organic insulation member.

Abstract: A display device includes a display panel including pixels, each including first, second, and third color pixels; a gate driver and a data driver connected to the pixel through a scan line and a data line, respectively. Each of the first, second, and third color pixels includes a color pixel electrode and a first transistor having a first electrode connected to the data line, a second electrode connected to the color pixel electrode, and a gate electrode connected to the scan line. A voltage distribution line is disposed to overlap the color pixel electrode of the third color pixel in a thickness direction extending in the second direction. A width of the second electrode of the first transistor of the third color pixel is greater than a width of that of each of the first and second color pixels in the first direction.

Abstract: An electro-optical device includes a wiring substrate including a wiring line, a common electrode, a conduction member that is electrically conductive, the conduction member being configured to electrically couple the wiring line and the common electrode, a pixel electrode disposed between the wiring substrate and the common electrode, and an electro-optical layer disposed between the pixel electrode and the common electrode. The wiring substrate includes: an insulating layer disposed between the wiring line and the common electrode, a conduction electrode between the insulating layer and the common electrode and in contact with the insulating layer, the conduction member being disposed at the conduction electrode, and a contact portion composed of a material different from the conduction electrode and penetrating the insulating layer, the contact portion being configured to electrically couple the conduction electrode and the wiring line.

Abstract: An organic light-emitting diode (OLED) display panel and a method for manufacturing the same are provided. The OLED display panel at least includes a thin film transistor (TFT) array substrate, a passivation layer, a planarization layer, and planarization-compensating layer. The planarization layer has a first planarization part corresponding to a light-emitting area, and a second planarization part corresponding to a defining area and a part of the light-emitting area. Height of a surface of the planarization-compensating layer from the surface of the TFT array substrate and height of a surface of the second planarization part from the surface of the TFT array substrate are level.

Abstract: A display panel includes: a base substrate; a circuit layer on the base substrate; and a display element layer on the circuit layer, wherein the circuit layer includes an active layer on the base substrate and containing boron and fluorine; a control electrode on the active layer; and a control electrode insulation layer between the active layer and the control electrode, wherein the active layer includes: a core layer in which a concentration of the boron is greater than a concentration of the fluorine; and a surface layer on the core layer and in which a concentration of the fluorine is greater than a concentration of the boron.

Abstract: A display device includes a substrate having an active area and a non-active area; a plurality of first subpixels arranged in the active area; and a plurality of second subpixels arranged adjacent to a boundary area between the active area and the non-active area, wherein the first and second subpixels have storage capacitors that have different capacitance values from each other, so that visibility of the stepped shape generated in the boundary area can be eliminated.

Abstract: A display device including a substrate, a plurality of pixel electrodes arranged in a form of a matrix in a plane parallel with the substrate, a display functional layer exerting an image display function on a basis of an image signal supplied to the plurality of pixel electrodes, a driving electrode opposed to the plurality of pixel electrodes, and a plurality of detecting electrodes arranged in a form of a plane opposed to the driving electrode, separated and arranged at a pitch of a natural number multiple of an arrangement pitch of the pixel electrodes in one direction in the arrangement plane, and each capacitively coupled with the driving electrode.

Abstract: A semiconductor device includes a gate electrode on a substrate, a gate insulating film on the gate electrode, an oxide semiconductor film via the gate insulating film on the gate electrode, a source electrode and a drain electrode on the oxide semiconductor film, a protective film provided on the source electrode and the drain electrode; and a conductive layer provided on the protective film and overlapped on the oxide semiconductor layer. The protective film includes a first silicon oxide film and a first silicon nitride film. The first oxide film is in contact with the oxide semiconductor layer. The gate insulating film includes a second silicon nitride film and a second silicon oxide film. The second silicon oxide film is in contact with the oxide semiconductor layer. The oxide semiconductor layer has a first region located between the source electrode and the drain electrode in a plan view.

Abstract: A transistor with small parasitic capacitance can be provided. A transistor with high frequency characteristics can be provided. A semiconductor device including the transistor can be provided. Provided is a transistor including an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor has a first region where the first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween; a second region where the first conductor overlaps with the second conductor with the first and second insulators positioned therebetween; and a third region where the first conductor overlaps with the third conductor with the first and second insulators positioned therebetween. The oxide semiconductor including a fourth region where the oxide semiconductor is in contact with the second conductor; and a fifth region where the oxide semiconductor is in contact with the third conductor.

Abstract: In a described example, a method for forming a capacitor includes: forming a capacitor first plate over a non-conductive substrate; flowing ammonia and nitrogen gas into a plasma enhanced chemical vapor deposition (PECVD) chamber containing the non-conductive substrate; stabilizing a pressure and a temperature in the PECVD chamber; turning on radio frequency high frequency (RF-HF) power to the PECVD chamber; pretreating the capacitor first plate for at least 60 seconds; depositing a capacitor dielectric on the capacitor first plate; and depositing a capacitor second plate on the capacitor dielectric.

Abstract: A memory chip includes at least two memory blocks. In a method for controlling power supply for the memory blocks of the memory chip, each memory block receives a command for switching to standby mode. The commands are issued, for example by a processor, separately for each memory block in order to be able to individually place the memory block in standby mode.

Abstract: A transistor includes a first gate electrode, a composite channel layer, a first gate dielectric layer, and source/drain contacts. The composite channel layer is over the first gate electrode and includes a first capping layer, a crystalline semiconductor oxide layer, and a second capping layer stacked in sequential order. The first gate dielectric layer is located between the first gate electrode and the composite channel layer. The source/drain contacts are disposed on the composite channel layer.

Abstract: A layer stack is formed over a conductive material portion located on a substrate. The layer stack contains a first silicon oxide layer, a silicon nitride layer formed by chemical vapor deposition, and a second silicon oxide layer. A patterned etch mask layer including an opening is formed over the layer stack. A via cavity extending through the layer stack and down to the conductive material portion is formed by isotropically etching portions of the layer stack underlying the opening in the patterned etch mask layer using an isotropic etch process. A buffered oxide etch process may be used, in which the etch rate of the silicon nitride layer is less than, but is significant enough, compared to the etch rate of the first silicon oxide layer to provide tapered straight sidewalls on the silicon nitride layer. An optical device including a patterned layer stack can be provided.

Abstract: The application discloses a method adapted to manufacture an array substrate and a display panel. The method includes: form a photoresist layer, a source and a drain; post-baking the photoresist layer, so that the photoresist layer flows to the position of a channel; etching a semiconductor layer to obtain a preset pattern; and peeling off the photoresist layer.

Abstract: A technique, comprising: forming in situ on a support substrate: a first metal layer; a light-absorbing layer after the first metal layer; a conductor pattern after the light-absorbing layer; and a semiconductor layer after the conductor pattern; patterning the semiconductor layer using a resist mask to form a semiconductor pattern defining one or more semiconductor channels of one or more semiconductor devices; and patterning the light-absorbing layer using the resist mask and the conductor pattern, so as to selectively retain the light-absorbing layer in regions that are occupied by at least one of the resist mask and the conductor pattern.

Abstract: The present application discloses an array substrate and a liquid crystal display panel. The array substrate includes an underlay substrate, a first electrode layer, a protection layer, and a second electrode layer that are disposed sequentially. The second electrode layer includes a pixel electrode, and the pixel electrode includes a pixel electrode main body and a conductive portion connected to each other. A rough surface is disposed on the conductive portion for draining redundant alignment liquid on the conductive portion such that a thickness of an alignment layer formed by curing the alignment liquid is even.

Abstract: An electronic substrate, a manufacturing method thereof and a display panel are provided. The electronic substrate includes a base substrate as well as a photosensitive unit and a touch structure which are provided on the base substrate. The photosensitive unit includes a first electrode layer, and the touch structure includes a first touch electrode layer. The first electrode layer and the first touch electrode layer are in a same first conductive layer and made of a same material, and the first electrode layer and the first touch electrode layer insulated from each other.

Abstract: Disclosed are a thin film transistor, a display apparatus comprising the thin film transistor, and a method for manufacturing the thin film transistor. The thin film transistor comprises an active layer, and a gate electrode spaced apart from the active layer and configured to have at least a portion overlapped with the active layer, wherein the active layer includes a silicon semiconductor layer, and an oxide semiconductor layer which contacts the silicon semiconductor layer, wherein at least a portion of the silicon semiconductor layer and at least a portion of the oxide semiconductor layer are overlapped with the gate electrode.

Abstract: A laser irradiation apparatus includes: a laser generation apparatus configured to generate first laser light for performing heat treatment of an object to be processed; a measurement-laser emission unit configured to emit linearly-polarized second laser light toward an irradiation area on the object to be processed to which the first laser light is applied; a first polarizing plate configured to let, of the whole reflected light of the second laser light reflected by the object to be processed, a part of the reflected light that has a first polarization direction pass therethrough; and a measurement-laser detection unit configured to detect the reflected light that has passed through the first polarizing plate.

Abstract: A display apparatus includes a substrate having a first transmissive area, a second transmissive area, a pixel area between the first transmissive area and the second transmissive area, a first pixel electrode in the pixel area, a first intermediate layer disposed on the first pixel electrode to emit light of a first color and an insulating layer covering edges of the first pixel electrode and defining a first emission area through a first opening exposing a portion of the first pixel electrode. A first partition wall is disposed on the insulating layer between the first emission area and the first transmissive area. A second partition wall is disposed on the insulating layer between the first emission area and the second transmissive area. An opposite electrode is disposed on the first intermediate layer in the pixel area and partially contacts the first partition wall and the second partition wall.

Abstract: A transistor is described. The transistor includes a substrate, a first semiconductor structure above the substrate, a second semiconductor structure above the substrate, a source contact that includes a first metal structure that contacts a plurality of surfaces of the first semiconductor structure and a drain contact that includes a second metal structure that contacts a plurality of surfaces of the second semiconductor structure. The transistor also includes a gate below a back side of the substrate.