Abstract: A display apparatus includes a first substrate, a second substrate, and a transistor. The first transistor includes a polymer resin. The second substrate is arranged between the first substrate and the transistor and includes a glass material. A liquidus temperature of the glass material is less than 1000° C. The transistor overlaps at least one of the first substrate and the second substrate and includes a semiconductor layer.

Abstract: A display device includes a drive transistor and a switching transistor formed by layering an inorganic insulating film, an oxide semiconductor layer, an upper gate insulating layer, an upper gate electrode, and an interlayer insulating film. The drive transistor and the switching transistor include an oxide semiconductor film formed of the oxide semiconductor layer and provided in an island shape corresponding to the drive transistor and an island shape corresponding to the switching transistor, and the oxide semiconductor film includes a channel region overlapping with the upper gate electrode corresponding to the oxide semiconductor film, and a source region and a drain region. The drive transistor is provided with a lower gate electrode and a lower gate insulating layer between the inorganic insulating film and the oxide semiconductor layer. The length of lower gate electrode is less than or equal to the length of upper gate electrode.

Abstract: A display device includes a display region and a periphery region surrounding the display region. The display device includes an driving circuit substrate, a TFT array substrate, a front plane laminate, and multiple conductive wires. The driving circuit substrate includes multiple first conductive pads. The TFT array substrate includes multiple second conductive pads. The TFT array substrate is located on the driving circuit substrate. The TFT array substrate is located between the driving circuit substrate and the front plane laminate. The conductive wires are electrically connected with the first conductive pads and the second conductive pads, respectively. The first conductive pads and the second conductive pads are located in the periphery region.

Abstract: A thin film transistor may be manufactured by forming a gate electrode in an insulating layer over a substrate, forming a gate dielectric over the gate electrode and the insulating layer, forming an active layer over the gate electrode, and forming a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. A surface oxygen concentration may be increased in at least one of the gate dielectric and the active layer by introducing oxygen atoms into a surface region of a respective one of the gate dielectric and the active layer.

Abstract: In order to provide a display apparatus with improved durability and improved impact resistance and a method of manufacturing the same, the disclosure provides a display apparatus and a method of manufacturing the same, the display apparatus including a substrate, a semiconductor layer disposed on the substrate, an insulating layer covering the semiconductor layer and including a first hole exposing a portion of the semiconductor layer, a first conductive layer disposed on the insulating layer and including a second hole overlapping the first hole, and a second conductive layer in contact with the portion of the semiconductor layer via the first hole and the second hole.

Abstract: An object of an embodiment of the present invention is to manufacture a semiconductor device with high display quality and high reliability, which includes a pixel portion and a driver circuit portion capable of high-speed operation over one substrate, using transistors having favorable electric characteristics and high reliability as switching elements. Two kinds of transistors, in each of which an oxide semiconductor layer including a crystalline region on one surface side is used as an active layer, are formed in a driver circuit portion and a pixel portion. Electric characteristics of the transistors can be selected by choosing the position of the gate electrode layer which determines the position of the channel. Thus, a semiconductor device including a driver circuit portion capable of high-speed operation and a pixel portion over one substrate can be manufactured.

Abstract: A screen sounding device and a display device are disclosed. The screen sounding device includes a sounding structure. The sounding structure includes a first electrode, an insulating layer, and a second electrode stacked in sequence. A sounding cavity is formed between a vibrating portion of the second electrode and the insulating layer. The first electrode and the second electrode receive different driving signals, and the vibrating portion can drive the air in the sounding cavity to vibrate and sound. The screen sounding device of the present disclosure has a desirable sounding effect, various setting positions, and low manufacturing costs.

Abstract: A manufacturing method of a display substrate, a display substrate, and a display device. The manufacturing method includes: forming an active layer; forming a gate insulation film layer, a gate film layer and a photoresist film layer; exposing the photoresist film layer to a light and developing the exposed photoresist film layer until the developed photoresist film layer has a thickness of 1.8-2.2 ?m and a slope angle not less than 70°; over-etching the gate film layer to form a gate electrode, an orthographic projection of the gate electrode being located within a region of an orthographic projection of the developed photoresist film layer; over-etching the gate insulation film layer by a gaseous corrosion method to form a gate insulation layer; peeling off the photoresist film layer remaining on a surface of the gate electrode; and performing a conductive treatment to the active layer.

Abstract: A display panel includes a first metal layer; a first insulating layer covering the first metal layer; a semiconductor layer disposed on the first insulating layer; a second insulating layer disposed on the first insulating layer to cover the semiconductor layer; and a second metal layer disposed on the second insulating layer, wherein the first metal layer comprises a bottom gate electrode of a driving element, wherein the second metal layer comprises a top gate electrode of the driving element connected to the bottom gate electrode through a first contact hole penetrating the second insulating layer and the first insulating layer, wherein the semiconductor layer comprises a semiconductor channel of the driving element overlapping with the top gate electrode and the bottom gate electrode.

Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes an oxide semiconductor, a first insulator in contact with the oxide semiconductor, and a second insulator in contact with the first insulator. The first insulator includes excess oxygen. The second insulator has a function of trapping or fixing hydrogen. Hydrogen in the oxide semiconductor is bonded to the excess oxygen. The hydrogen bonded to the excess oxygen passes through the first insulator and is trapped or fixed in the second insulator. The excess oxygen bonded to the hydrogen remains in the first insulator as the excess oxygen.

Abstract: A semiconductor device includes a semiconductor substrate having a semiconductor substrate having a main surface including a first portion; a redistribution layer provided over the first portion of the main surface of the semiconductor substrate; an insulating layer covering the first portion of the main surface of the semiconductor substrate and the redistribution layer; and a first polyimide film covering the insulating layer; wherein the polyimide film has a substantially flat upper surface.

Abstract: A method includes forming a gate dielectric layer and a dummy gate layer; forming a mask over the dummy gate layer; patterning the gate dielectric layer and the dummy gate layer to form a dummy gate structure, the dummy gate structure including a remaining portion of the gate dielectric layer and a remaining portion of the dummy gate layer; epitaxially growing a first spacer layer on the dummy gate structure and the substrate, in which the first spacer layer has a higher growth rate on the exposed surfaces of the dummy gate structure and the substrate than on exposed surfaces of the mask; doping the first spacer layer to form a doped spacer layer having a different lattice constant than the substrate; depositing a second spacer layer over the doped spacer layer; and etching the second spacer layer and the doped spacer layer to form a gate spacer.

Abstract: According to an aspect of the present disclosure, a liquid crystal display device includes a lower substrate including a black matrix and a color filter; an upper substrate disposed to be opposite to the lower substrate; a thin film transistor which on the upper substrate to be opposite to the color filter, and including a gate electrode, an active layer, a source electrode, and a drain electrode; at least one insulting layer disposed on the thin film transistor; a pixel electrode disposed on the insulating layer and electrically connected to the drain electrode; and a common electrode spaced apart from the pixel electrode, and the gate electrode includes a first gate conductive layer including a transparent conductive material, a second gate conductive layer including a first transition metal oxide and a second transition metal oxide, and a third gate conductive layer formed of an opaque conductive layer.

Abstract: A display device includes a base substrate; an oxide semiconductor layer disposed on the base substrate; a first gate insulating layer disposed on a first channel region of the oxide semiconductor layer and that overlaps the first channel region thereof; a first upper gate electrode disposed on the first gate insulating layer; and an upper interlayer insulating layer disposed on the first upper gate electrode, the first upper gate electrode, and the oxide semiconductor layer, wherein the upper interlayer insulating layer includes a first upper interlayer insulating layer, a second upper interlayer insulating layer, and a third upper interlayer insulating layer, the first upper interlayer insulating layer includes silicon oxide, each of the second and third upper interlayer insulating layers include silicon nitride, and a hydrogen concentration in the second upper interlayer insulating layer is less than a hydrogen concentration in the third upper interlayer insulating layer.

Abstract: A display panel and a method of manufacturing the display panel are provided. The display panel includes a substrate and a transistor layer. The transistor array layer includes a first metal layer disposed above the substrate. The first metal layer includes a gate, a second metal layer disposed above the first metal layer. The second metal layer includes a source, a drain, and a metal trace, and at least one repair part disposed on both sides of the metal trace. The repair part and the metal trace are configured to form a signal trace.

Abstract: The stability of steps of processing a wiring formed using copper or the like is increased. The concentration of impurities in a semiconductor film is reduced. Electrical characteristics of a semiconductor device are improved. A semiconductor device includes a semiconductor film, a pair of first protective films in contact with the semiconductor film, a pair of conductive films containing copper or the like in contact with the pair of first protective films, a pair of second protective films in contact with the pair of conductive films on the side opposite the pair of first protective films, a gate insulating film in contact with the semiconductor film, and a gate electrode overlapping with the semiconductor film with the gate insulating film therebetween. In a cross section, side surfaces of the pair of second protective films are located on the outer side of side surfaces of the pair of conductive films.

Abstract: A method of manufacturing a display device, including: providing an object to be processed; forming a linear portion of the object to be processed by performing a first laser processing for the object to be processed; and forming a curved portion of the object to be processed by performing a second laser processing different from the first laser processing for the object to be processed. A laser processing apparatus, is also provided, including: an irradiation unit applying a laser onto an object to be processed; and a controller controlling an operation of the irradiation unit. The controller controls the irradiation unit to form a linear portion of the object to be processed by applying the laser onto the object according to a first condition and forming a curved portion of the object by applying the laser onto the object according to a second condition different from the first condition.

Abstract: Methods for forming a nickel silicide material on a substrate are disclosed. The methods include depositing a first nickel silicide seed layer atop a substrate at a temperature of about 15° C. to about 27° C., annealing the first nickel silicide seed layer at a temperature of 400° C. or less such as over 350° C.; and depositing a second nickel silicide layer atop the first nickel silicide seed layer at a temperature of about 15° C. to about 27° C. to form the nickel silicide material.

Abstract: The disclosure provides a displaying substrate, a manufacturing method thereof, and a display panel, and relates to the technical field of display. The displaying substrate comprises a first supporting base (1), plurality of vibrating element modules (2), and a display module (3). The display module (3) comprises display units (31), connecting units (32) and hollowed-out units (33). Each connecting unit (32) is located between two adjacent display units (31). Each hollowed-out unit (33) is located between two adjacent display units (31) except an area where the corresponding connecting unit (32) is located. The hollowed-out units (33) are provided with cavities (40) corresponding to the vibrating element modules (2). Orthographic projections of the hollowed-out units (33) on a reference plane cover orthographic projections of the vibrating element modules (2) on the reference plane. The vibrating element modules (2) and the cavities (40) form a transducer.

Abstract: According to one embodiment, a display device includes a display panel including a display area for displaying an image, and the display panel includes an insulating substrate, a first electrode, a first organic insulating layer, an inorganic insulating layer, a pixel electrode, a second organic insulating layer, and a pad portion. The inorganic insulating layer includes a first opening for electrically connecting the first electrode to the pixel electrode. The second organic insulating layer includes a second opening for electrically connecting the pixel electrode to the pad portion. The pixel electrode is formed of a transparent conductive material.

Abstract: A display panel is provided including a substrate including a display area comprising first pixels and a sensor area including second pixels and a transmission portion. A display element layer is disposed on the substrate, the display element layer comprising the first pixels electrically connected to a first thin film transistor and the second pixels electrically connected to a second thin film transistor. A conductive layer is disposed between the second thin film transistor and the substrate, the conductive layer having two or more steps at an edge thereof.

Abstract: A semiconductor device includes a substrate having an insulating surface; a light-transmitting first electrode provided over the substrate; a light-transmitting second electrode provided over the substrate; a light-transmitting semiconductor layer provided so as to be electrically connected to the first electrode and the second electrode; a first wiring electrically connected to the first electrode; an insulating layer provided so as to cover at least the semiconductor layer; a light-transmitting third electrode provided over the insulating layer in a region overlapping with the semiconductor layer; and a second wiring electrically connected to the third electrode.

Abstract: Provided are a thin film transistor, a display device, and a thin film transistor manufacturing method, in which variation in characteristics is small. The present invention is provided with: a gate electrode formed on a substrate; a gate insulation film formed so as to cover the gate electrode; a semiconductor layer which is formed on the upper side of the gate insulation film and which includes a polysilicon layer disposed, in a plan view, inside a region defined by the gate electrode; an etching stopper layer disposed on the upper side of the polysilicon layer; and a source electrode and a drain electrode provided on the semiconductor layer so as to be separated from each other, wherein the polysilicon layer has first and second regions which are not covered with the etching stopper layer, and a part of the source electrode exists above the first region and a part of the drain electrode exists above the second region.

Abstract: Apparatus and methods for improving film uniformity in a physical vapor deposition (PVD) process are provided herein. In some embodiments, a PVD chamber includes a pedestal disposed within a processing region of the PVD chamber, the pedestal having an upper surface configured to support a substrate thereon, a first motor coupled to the pedestal, a lid assembly comprising a first target, a first magnetron disposed over a portion of the first target, and in a region of the lid assembly that is maintained at atmospheric pressure, a first actuator configured to translate the first magnetron in a first direction, a second actuator configured to translate the first magnetron in a second direction, and a system controller that is configured to cause the first magnetron to translate along at least a portion of a first path by causing the first actuator and second actuator to simultaneously translate the first magnetron.

Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.

Abstract: An electroluminescent display including pixels arranged in a matrix is disclosed. Each pixel includes a pixel circuit configured to sample a threshold voltage of a driving element for driving a light emitting element and compensate for a data voltage. The pixel circuit includes a first switch element connected to a data voltage path supplied with the data voltage, a second switch element connected to a reference voltage path supplied with a predetermined reference voltage, a third switch element connected between a gate of the driving element and the first and second switch elements, a fourth switch element connected to an initialization voltage path supplied with a predetermined initialization voltage, and a fifth switch element connected to a power path supplied with a predetermined pixel driving voltage higher than the reference voltage and the initialization voltage.

Abstract: The present invention provides a photosensitive element, and a preparation method and a display device thereof. The photosensitive element includes a substrate; a first electrode arranged on the substrate; an N-type doped silicon layer arranged on the first electrode; an undoped silicon layer arranged on the N-type doped silicon layer; a molybdenum oxide layer arranged on the undoped silicon layer; an insulating layer arranged on the molybdenum oxide layer and the substrate, wherein a first opening is arranged on the insulating layer to expose the molybdenum oxide layer; and a second electrode arranged on the insulating layer and the molybdenum oxide layer, wherein the second electrode contacts the molybdenum oxide layer through the first opening.

Abstract: A display apparatus includes a first substrate, a second substrate, and a transistor. The first transistor includes a polymer resin. The second substrate is arranged between the first substrate and the transistor and includes a glass material. A liquidus temperature of the glass material is less than 1000° C. The transistor overlaps at least one of the first substrate and the second substrate and includes a semiconductor layer.

Abstract: Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer, a carrier transit layer, a carrier supply layer, a gate, a source electrode and a drain electrode. The buffer layer is on a substrate. The carrier transit layer is on the buffer layer. The carrier supply layer is on the carrier transit layer. The gate is on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the gate, wherein each of the source electrode and the drain electrode includes a conductive layer and a conductive oxide layer stacked from bottom to top.

Abstract: The present invention provides a highly integrated memory cell and a semiconductor device including the same. According to an embodiment of the present invention, the semiconductor device comprises: a plurality of active layers vertically stacked over a substrate; a plurality of bit lines connected to first ends of the active layers, respectively, and extended parallel to the substrate; line-shape air gaps disposed between the bit lines; a plurality of capacitors connected to second ends of the active layers, respectively; and a word line and a back gate facing each other with each of the active layers interposed therebetween, wherein the word line and the back gate are vertically oriented from the substrate.

Abstract: A thin film transistor includes a gate, a gate insulating layer, an active layer, an ionized amorphous silicon layer, a source and a drain. The gate insulating layer covers the gate. The active layer is disposed on a side of the gate insulating layer away from the gate. The ionized amorphous silicon layer is disposed on a side of the active layer away from the gate, and the ionized amorphous silicon layer is in contact with the gate insulating layer. The source and the drain are disposed on a side of the ionized amorphous silicon layer away from the gate insulating layer, and the source and the drain are coupled to the active layer through the ionized amorphous silicon layer.

Abstract: A semiconductor device including a contact structure is provided. The semiconductor device includes an isolation region defining a lower active region. First and second source/drain regions and first and second gate electrodes are on the lower active region. The first and second source/drain regions are adjacent to each other. First and second gate capping patterns are on the first and second gate electrodes, respectively. First and second contact structures are on the first and second source/drain regions, respectively. A lower insulating pattern is between the first and second source/drain regions. An upper insulating pattern is between the first and second contact structures. Silicon oxide has etching selectivity with respect to an insulating material which the upper insulating pattern, the first gate capping pattern, and the second gate capping pattern are formed of.

Abstract: A body layer formed of a semiconductor layer, the body layer comprising, a first region, a second region, and a channel region positioned therebetween; a channel stopper formed on the channel region; source and drain electrodes electrically connected to the first and second regions via first and second contact layers respectively are provided. Each of the first and second contact layers comprises an impurities-containing first amorphous silicon layer; a thickness of each of the first and second regions is less than a thickness of the channel region; and the first and second regions comprise a second amorphous silicon layer containing impurities in a concentration being less than a concentration of impurities contained in the first amorphous silicon layer. This makes it possible to suppress a photoexcited current and improve the aperture ratio in a case that a display apparatus is configured.

Abstract: A method of forming a structure having a coating layer includes the following steps: providing a substrate; coating a fluid on the surface of the substrate, where the fluid includes a carrier and a plurality of silicon-containing nanoparticles; and performing a heating process to remove the carrier and convert the silicon-containing nanoparticles into a silicon-containing layer, a silicide layer, or a stack layer including the silicide layer and the silicon-containing layer.

Abstract: A manufacturing method of a display device includes: forming a transistor on a substrate; forming an organic insulating layer on the transistor; and performing a plasma treatment on the organic insulating layer. The organic insulating layer includes an acryl-based polymer, and the plasma treatment is performed by using helium gas or argon gas.

Abstract: A method of manufacturing a semiconductor device according to the present disclosure includes forming a stack by alternately stacking insulating films and sacrificial films on a substrate; forming, in the stack, a through-hole extending in a thickness direction of the stack; forming a block insulating film, a charge trapping film, a tunnel insulating film, and a channel film on an inner surface of the through-hole in this order; forming, in the stack, a slit extending in the thickness direction of the stack separately from the through-hole; removing the sacrificial films through the slit so as to form a recess between adjacent insulating films; forming a first metal oxide film on an inner surface of the recess; forming, on the first metal oxide film, a second metal oxide film having a crystallization temperature lower than that of the first metal oxide film; and filling the recess with an electrode layer.

Abstract: An electronic device and a manufacturing method thereof are provided. The electronic device includes an array substrate, which includes a substrate, a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer. The substrate has a substrate surface. The first conductive layer is located on the substrate surface. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer and includes a first sputtering layer, a second sputtering layer, and a third sputtering layer. The second insulating layer is located on the second conductive layer. The second sputtering layer is located between the first and third sputtering layers, and includes a first metal element. The first sputtering layer includes the first metal element and a second metal element. The third sputtering layer includes the first metal element and a third metal element.

Abstract: A thin film transistor (TFT) substrate includes a TFT on the substrate. The TFT includes an active patterned layer which is made of a polycrystalline silicon, which includes a channel portion, a source portion and a drain portion, and in which protrusions are formed at boundaries between grains and recess spaces are formed between the protrusions. A barrier pattern film fills the recess spaces and forms a flat surface with the protrusions. A gate electrode is on a gate insulating layer located on the barrier pattern film and the protrusions and overlays or corresponds to the channel portion. A source electrode and a drain electrode are on the gate electrode and respectively contact the source portion and the drain portion.

Abstract: Provided is a display panel including a main display area, a component area having a transmissive area, a peripheral area outside the main display area, a substrate, a bottom metal layer on the substrate, and defining an opening corresponding to the transmissive area, a valley portion adjacent to a boundary between the bottom metal layer and the transmissive area, and a thin-film encapsulation layer on the valley portion, and including an inorganic layer and an organic layer.

Abstract: A panel comprises a substrate; a transistor disposed on the substrate and including: a source electrode, a drain electrode, a gate electrode, a gate insulation layer, an active layer, an auxiliary source electrode configured to electrically connect one end of the active layer to the source electrode, and an auxiliary drain electrode configured to electrically connect an other end of the active layer to the drain electrode; and a capacitor disposed on the substrate and including a first plate and a second plate. The first plate of the capacitor is made of a same material as the auxiliary source electrode and the auxiliary drain electrode.

Abstract: A vertical nanowire semiconductor device manufactured by a method of manufacturing a vertical nanowire semiconductor device is provided. The vertical nanowire semiconductor device includes a substrate, a first conductive layer in a source or drain area formed above the substrate, a semiconductor nanowire of a channel area vertically upright with respect to the substrate on the first conductive layer, wherein a crystal structure thereof is grown in <111> orientation, a second conductive layer of a drain or source area provided on the top of the semiconductor nanowire, a metal layer on the second conductive layer, a NiSi2 contact layer between the second conductive layer and the metal layer, a gate surrounding the channel area of the vertical nanowire, and a gate insulating layer located between the channel area and the gate.

Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, and a channel region vertically between the top and bottom source/drain regions. A gate is operatively laterally-adjacent the channel region. The top source/drain region, the bottom source/drain region, and the channel region respectively have crystal grains and grain boundaries between immediately-adjacent of the crystal grains. At least one of the bottom source/drain region and the channel region has an internal interface there-within between the crystal grains that are above the internal interface and the crystal grains that are below the internal interface. At least some of the crystal grains that are immediately-above the internal interface physically contact at least some of the crystal grains that are immediately-below the internal interface.

Abstract: Disclosed herein is a composite transistor which includes a first transistor TR1 including a control electrode, a first active region, a first A extending part, and a first B extending part, and a second transistor TR2 including a control electrode, a second active region, a second A extending part, and a second B extending part. The first active region, the second active region, and the control electrode overlap one another. Both the first A extending part and the first B extending part extend from the first active region and both the second A extending part and the second B extending part extend from the second active region. The first electrode is connected to the first A extending part, the second electrode is connected to the second A extending part, and the third electrode is connected to the first B extending part and the second B extending part.

Abstract: A method of manufacturing a display substrate may include the following steps: forming a drain electrode on a pixel area of a substrate; forming a pad electrode on a pad area of the substrate; forming an inorganic insulation layer that covers the drain electrode and the pad electrode; forming an organic insulation member that has a first thickness at the pixel area of the substrate, has a second thickness less than the first thickness at the pad area of the substrate, exposes a first portion of the inorganic insulation layer on the drain electrode, and exposes a second portion of the inorganic insulation layer on the pad electrode; removing the first portion of the inorganic insulation layer and the second portion of the inorganic insulation layer; and partially removing the organic insulation member.

Abstract: A panel comprises a substrate; a transistor disposed on the substrate and including: a source electrode, a drain electrode, a gate electrode, a gate insulation layer, an active layer, an auxiliary source electrode configured to electrically connect one end of the active layer to the source electrode, and an auxiliary drain electrode configured to electrically connect an other end of the active layer to the drain electrode; and a capacitor disposed on the substrate and including a first plate and a second plate. The first plate of the capacitor is made of a same material as the auxiliary source electrode and the auxiliary drain electrode.

Abstract: A display panel includes: a base substrate; a circuit layer on the base substrate; and a display element layer on the circuit layer, wherein the circuit layer includes an active layer on the base substrate and containing boron and fluorine; a control electrode on the active layer; and a control electrode insulation layer between the active layer and the control electrode, wherein the active layer includes: a core layer in which a concentration of the boron is greater than a concentration of the fluorine; and a surface layer on the core layer and in which a concentration of the fluorine is greater than a concentration of the boron.

Abstract: A display device includes a display panel including pixels, each including first, second, and third color pixels; a gate driver and a data driver connected to the pixel through a scan line and a data line, respectively. Each of the first, second, and third color pixels includes a color pixel electrode and a first transistor having a first electrode connected to the data line, a second electrode connected to the color pixel electrode, and a gate electrode connected to the scan line. A voltage distribution line is disposed to overlap the color pixel electrode of the third color pixel in a thickness direction extending in the second direction. A width of the second electrode of the first transistor of the third color pixel is greater than a width of that of each of the first and second color pixels in the first direction.

Abstract: An electro-optical device includes a wiring substrate including a wiring line, a common electrode, a conduction member that is electrically conductive, the conduction member being configured to electrically couple the wiring line and the common electrode, a pixel electrode disposed between the wiring substrate and the common electrode, and an electro-optical layer disposed between the pixel electrode and the common electrode. The wiring substrate includes: an insulating layer disposed between the wiring line and the common electrode, a conduction electrode between the insulating layer and the common electrode and in contact with the insulating layer, the conduction member being disposed at the conduction electrode, and a contact portion composed of a material different from the conduction electrode and penetrating the insulating layer, the contact portion being configured to electrically couple the conduction electrode and the wiring line.

Abstract: An organic light-emitting diode (OLED) display panel and a method for manufacturing the same are provided. The OLED display panel at least includes a thin film transistor (TFT) array substrate, a passivation layer, a planarization layer, and planarization-compensating layer. The planarization layer has a first planarization part corresponding to a light-emitting area, and a second planarization part corresponding to a defining area and a part of the light-emitting area. Height of a surface of the planarization-compensating layer from the surface of the TFT array substrate and height of a surface of the second planarization part from the surface of the TFT array substrate are level.