Lateral Single Gate Single Channel Transistor With Inverted Structure, I.e., Channel Layer Is Formed After Gate (epo) Patents (Class 257/E21.414)
  • Patent number: 11462598
    Abstract: An organic light emitting diode (OLED) display panel is provided, which includes a thin film transistor (TFT) array, a second metal layer, and an insulating layer disposed on the TFT array, a light blocking layer disposed on the insulating layer, a planarization layer disposed on the light blocking layer, an anode metal layer disposed on the planarization layer, and the light blocking layer provided with a plurality of holes; wherein the second metal layer includes a source-drain metal layer, and an interconnect hole is disposed in an interlayer structure between the source-drain metal layer and the anode metal layer and is electrically connected to the source-drain metal layer and the anode metal layer.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: October 4, 2022
    Inventor: Wenqi Li
  • Patent number: 11430666
    Abstract: A method of fabricating a semiconductor device includes applying a plasma to a portion of a metal dichalcogenide film. The metal dichalcogenide film includes a first metal and a chalcogen selected from the group consisting of S, Se, Te, and combinations thereof. A metal layer including a second metal is formed over the portion of the metal dichalcogenide film after applying the plasma.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Piao Chuu, Ming-Yang Li, Lain-Jong Li
  • Patent number: 11424337
    Abstract: The present invention provides an array substrate, a manufacturing method thereof, and a display panel. The array substrate includes a substrate, a buffer layer, an active layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, a source drain layer, and a planarization layer. The gate insulating layer is formed on the active layer and the buffer layer. The interlayer dielectric layer is formed on the gate layer and the gate insulating layer. The source drain layer is patterned to form a source and a drain, and is connected to the active layer through via holes. The planarization layer in the present invention is easier to fill in.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: August 23, 2022
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Wenjuan Jiang
  • Patent number: 11411122
    Abstract: A display device including: a first thin film transistor (TFT) including a first semiconductor layer and a first gate electrode, the first semiconductor layer including a first channel region, a first source region, and a first drain region; a third TFT including a third semiconductor layer and a third gate electrode, the third semiconductor layer including a third channel region, a third source region, and a third drain region, wherein a leakage current of the third TFT in an off-state is less than a leakage current of the first TFT in an off-state; and a pixel electrode connected to one of the first source region and the first drain region, wherein the one of the first source region and the first drain region is connected to the third TFT.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: August 9, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jaeseob Lee, Meejae Kang, Yoonho Khang, Keunwoo Kim, Hanbit Kim, Thanhtien Nguyen
  • Patent number: 11404405
    Abstract: A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include polycrystalline silicon. The upper metal routing layer M3 or higher may include cobalt.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: August 2, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wei-E Wang, Titash Rakshit, Borna J. Obradovic, Chris Bowen, Mark S. Rodder
  • Patent number: 11398509
    Abstract: Provided is an electro-optical device including a plurality of pixel electrodes arranged in a display region, a first transistor that captures a pulse supplied to a source node by using a clock signal supplied to a gate node and outputs the pulse from the drain node, a second transistor to which the pulse output from the drain node is input, and a capacitance element having one end coupled to the drain node and another end held at a predetermined potential. In the capacitance element, an interlayer insulating film is sandwiched between a first peripheral electrode formed of a same layer as the plurality of pixel electrodes and a wiring formed of a predetermined electrode layer, and the wiring includes a portion overlapping the second transistor in plan view.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: July 26, 2022
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Shinsuke Fujikawa
  • Patent number: 11398560
    Abstract: Embodiments herein describe techniques for a transistor above the substrate. The transistor includes a first gate dielectric layer with a first gate dielectric material above a gate electrode, and a second dielectric layer with a second dielectric material above a portion of the first gate dielectric layer. A first portion of a channel layer overlaps with only the first gate dielectric layer, while a second portion of the channel layer overlaps with the first gate dielectric layer and the second dielectric layer. A first portion of a contact electrode overlaps with the first portion of the channel layer, and overlaps with only the first gate dielectric layer, while a second portion of the contact electrode overlaps with the second portion of the channel layer, and overlaps with the first gate dielectric layer and the second dielectric layer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: July 26, 2022
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Van H. Le, Abhishek Sharma, Jack T. Kavalieros, Sean Ma, Seung Hoon Sung, Nazila Haratipour, Tahir Ghani, Justin Weber, Shriram Shivaraman
  • Patent number: 11387370
    Abstract: The present invention provides an amorphous silicon thin film transistor and a manufacturing method of the amorphous silicon thin film transistor, which comprise: a substrate, a gate electrode layer, a gate insulating layer, an active layer, a source/drain electrode layer, an N+-doped layer, a protective insulating layer, and a passivation layer. The N+-doped layer is disposed between the active layer and the source/drain electrode layer. The protective insulating layer is disposed on the source/drain electrode layer. A channel is formed in the source/drain electrode layer and penetrates the N+-doped layer and the protective insulating layer. The passivation layer covers the channel and the protective insulating layer. The protective insulating layer and the source/drain electrode layer are flush with each other in the channel.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: July 12, 2022
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Jiaxin Li
  • Patent number: 11380753
    Abstract: A display device includes a base substrate; an organic layer disposed on the base substrate; and a first conductive layer disposed on the organic layer, wherein the first conductive layer includes a plurality of stacked films, the plurality of stacked films include a first conductive film disposed directly on the organic layer and a second conductive film disposed on the first conductive film, and the first conductive film has an oxygen concentration higher than an oxygen concentration of the second conductive film.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: July 5, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sang Gab Kim, Tae Sung Kim, Joon Geol Lee, Hyun Min Cho, Dae Won Choi, Yun Jong Yeo
  • Patent number: 11239263
    Abstract: A thin film transistor, a method for manufacturing the same and a display device are disclosed. The thin film transistor includes source-drain electrodes and a passivation layer; an isolation layer is disposed between the source-drain electrodes and the passivation layer, and the isolation layer overlays the source-drain electrodes.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: February 1, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Tianmin Zhou, Wei Yang, Lizhong Wang, Xiaming Zhu, Jipeng Song
  • Patent number: 11224937
    Abstract: A line beam irradiation apparatus (1000) includes a work stage (200), a line beam source (100) for irradiating a work (300) placed on the work stage (200) with a line beam; and a transporting device (250) for moving at least one of the work stage (200) and the line beam source (100) such that an irradiation position of the line beam on the work moves in a direction transverse to the line beam. The line beam source includes a plurality of semiconductor laser devices and a support for supporting the plurality of semiconductor laser devices. The plurality of semiconductor laser devices are arranged along a same line extending in a fast axis direction, and the laser light emitted from emission regions of respective ones of the semiconductor laser devices diverge parallel to the same line to form the line beam.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: January 18, 2022
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Katsuhiko Kishimoto
  • Patent number: 11205729
    Abstract: A semiconductor device includes a thin film transistor, wherein: a semiconductor layer of the thin film transistor has a layered structure including a lower oxide semiconductor layer including In, Ga, Zn and Sn and an upper oxide semiconductor layer arranged on the lower oxide semiconductor layer and including In, Ga and Zn; a thickness of the lower oxide semiconductor layer is 20 nm or less; an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer is 5% or more; the upper oxide semiconductor layer includes no Sn, or an atomic ratio of Sn with respect to all metal elements of the upper oxide semiconductor layer is smaller than an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer; and a first angle ?1 between a side surface and a lower surface of the lower oxide semiconductor layer is smaller than a second angle ?2 between a side surface and a lower surface of the upper oxide semiconductor layer.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: December 21, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tetsuo Kikuchi, Masahiko Suzuki, Setsuji Nishimiya, Teruyuki Ueda, Masamitsu Yamanaka, Tohru Daitoh, Hajime Imai, Kengo Hara
  • Patent number: 10989964
    Abstract: The present invention provides a liquid crystal display device that can retain a favorable VHR and a low residual DC voltage and minimize display unevenness such as stains and image sticking, in long-term use at high temperatures.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: April 27, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masanobu Mizusaki, Hiroshi Tsuchiya, Katsuya Ogawa, Toshiaki Fujihara
  • Patent number: 10991809
    Abstract: A removal composition and process for selectively removing p-doped polysilicon (e.g., boron-doped polysilicon) relative to silicon nitride from a microelectronic device having said material thereon. The substrate preferably comprises a high-k/metal gate integration scheme.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: April 27, 2021
    Assignee: ENTEGRIS, INC.
    Inventors: Steven Bilodeau, Emanuel I Cooper
  • Patent number: 10937897
    Abstract: It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: March 2, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 10930680
    Abstract: A display apparatus includes a substrate, a display unit, a pad portion, and a connection wire. The display unit is on the substrate. The display unit includes a pixel circuit and a display device electrically connected to the pixel circuit. The pad portion is at one side of a peripheral area outside the display unit. The pad portion includes a first conductive layer, a second conductive layer arranged on and electrically connected to the first conductive layer, and a third conductive layer arranged on and electrically connected to the second conductive layer. The connection wire connects the pad portion and the display unit to each other to transmit a signal input to the pad portion to the display device. The connection wire includes a same material as that of the first conductive layer.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: February 23, 2021
    Assignee: Samsung Disploy Co., Ltd.
    Inventors: Jaewook Kang, Daewoo Lee, Takyoung Lee
  • Patent number: 10916738
    Abstract: The present disclosure provides a display panel, a manufacturing method of the display panel, and a display device. The manufacturing method includes: forming an auxiliary cathode layer; forming at least one tip structure on the auxiliary cathode layer; forming a main cathode layer, wherein the at least one tip structure is between the auxiliary cathode layer and the main cathode layer; and forming at least one connection between the main cathode layer and the auxiliary cathode layer by discharging at the at least one tip structure, wherein the at least one connection is electrically connected to the main cathode layer and the auxiliary cathode layer respectively.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: February 9, 2021
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Shi Sun, Xuewu Xie, Hao Liu, Ameng Zhang, Yu Ai, Bowen Liu, Yubao Kong
  • Patent number: 10777683
    Abstract: A thin film transistor, a method of manufacturing the same, an array substrate and a display panel are disclosed. The thin film transistor includes a light blocking layer, an electrode layer, and a combination layer, which are sequentially stacked. The electrode layer includes a gate electrode, a source electrode and a drain electrode which are separated from one another, and the gate electrode is located between the source electrode and the drain electrode. The light blocking layer includes a first portion of which an orthogonal projection is located between an orthogonal projection of the gate electrode and an orthogonal projection of the source electrode; and a second portion of which an orthogonal projection is located between the orthogonal projection of the gate and an orthogonal projection of the drain. The combination layer includes an active layer.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: September 15, 2020
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yang Zhang, Luke Ding, Bin Zhou, Haitao Wang, Ning Liu, Jingang Fang, Yongchao Huang, Liangchen Yan
  • Patent number: 10727256
    Abstract: A method for fabricating an array substrate, after the wet etching process of the source-drain metal layer (17), performs first ashing for the island-like photoresist pattern (19), such that the edge of the island-like photoresist pattern (19) is aligned with the edge of the source-drain metal segment (171).
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: July 28, 2020
    Assignee: HKC CORPORATION LIMITED
    Inventors: Bangtong Ge, Tingting Fu
  • Patent number: 10644162
    Abstract: A method for manufacturing an array substrate, a display panel and a display device are provided. The method includes forming a semiconductor layer, a gate insulating layer, a gate and an inter-layer insulator successively on a base substrate; forming via holes in the inter-layer insulator so as to expose portions of the semiconductor layer; performing plasma bombardment to the portions of the semiconductor layer exposed in the via holes; forming a source electrode and a drain electrode coupled with the semiconductor layer through the via holes respectively on the inter-layer insulator.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: May 5, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jiangbo Chen, Jianhua Du, Guoying Wang, Wei Liu
  • Patent number: 10586714
    Abstract: A thin film transistor substrate includes a gate electrode arranged on a substrate, a gate insulation layer arranged on the gate electrode, an active pattern arranged on the gate insulation layer, a source electrode overlapping a first end portion of the active pattern, and a drain electrode overlapping a second and opposite end portion of the active pattern. A fluorocarbon-like material is arranged on one or more of surfaces of at least one of the active pattern, the source electrode and the drain electrode, and on a photoresist pattern used in the formation process of the thin film substrate. The fluorocarbon-like material on the photoresist pattern serves to maintain a shape and size of the photoresist pattern during subsequent patterning processes.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: March 10, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyun-Min Cho, Dong-Il Kim
  • Patent number: 10566461
    Abstract: A thin film transistor and a method for manufacturing the same, an array substrate, and a display device are provided in embodiments of the disclosure. The method for manufacturing a thin film transistor in embodiments of the disclosure forms a plurality of strip-shaped protrusions on a substrate by a patterning process before forming structures of various layers of the thin film transistor, and then forms sequentially a gate electrode, a gate insulating layer, an active layer, a source-drain electrode on the plurality of strip-shaped protrusions; in other words, the thin film transistor is prepared, whose channels are aligned with and shaped to be similar to the plurality of strip-shaped protrusions, in a widthwise direction thereof.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: February 18, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Hui An, Dezhi Xu, Xianxue Duan
  • Patent number: 10566455
    Abstract: The stability of steps of processing a wiring formed using copper or the like is increased. The concentration of impurities in a semiconductor film is reduced. Electrical characteristics of a semiconductor device are improved. A semiconductor device includes a semiconductor film, a pair of first protective films in contact with the semiconductor film, a pair of conductive films containing copper or the like in contact with the pair of first protective films, a pair of second protective films in contact with the pair of conductive films on the side opposite the pair of first protective films, a gate insulating film in contact with the semiconductor film, and a gate electrode overlapping with the semiconductor film with the gate insulating film therebetween. In a cross section, side surfaces of the pair of second protective films are located on the outer side of side surfaces of the pair of conductive films.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: February 18, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masami Jintyou, Yasutaka Nakazawa, Yukinori Shima
  • Patent number: 10473991
    Abstract: The present invention provides a manufacturing method of a liquid crystal display panel, the color filter layer is formed on the TFT array substrate, at least a portion of the first color resist layer disposed on the gate line of the first substrate is used as a color resist protrusion, the spacer material and the black matrix material are integrated into same material, and the spacer and the black matrix are formed on the TFT array substrate through utilizing a multi-tone mask and only one lithography process.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: November 12, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Zhuming Deng
  • Patent number: 10431686
    Abstract: An integrated circuit (IC) employs a channel structure layout having an active semiconductor channel structure(s) and an isolated neighboring dummy semiconductor channel structure(s) for increased uniformity. A semiconductor channel structure(s) in an IC is a fin structure(s) or a gate-all-around (GAA) structure(s) employed in a Field-Effect Transistor (FET), such as a FinFET or a three-dimensional (3D) FET. The channel structures in the IC are fabricated according to a circuit cell architecture, such as a standard circuit cell (“standard cell”). The IC includes an active (e.g., diffusion) region in which a semiconductor channel structure array (e.g., semiconductor fin array) is formed according to a pattern. The IC includes a device employing a channel structure array in the active region. The channel structure array may include one active channel structure (e.g., fin) for reduced power consumption in the FinFET, and may include at least one dummy fin for increased uniformity.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: October 1, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Haining Yang, Xiangdong Chen
  • Patent number: 10416510
    Abstract: A liquid crystal display (“LCD”) device provides enhanced display quality. An insulating layer is formed on a first substrate. The insulating layer covers the contact portion of a switching device in which the switching device is electrically connected to a transparent electrode and has an opening for exposing a portion of the transparent electrode. A reflection electrode is electrically connected to the transparent electrode through the opening. The insulation layer covers a first portion of a driving circuit formed on the first substrate. A sealant is interposed between the first and second substrate to engage the first and second substrate and to cover a second portion of the driving circuit. Therefore, the driver circuit may operate normally, and the distortion of the signal outputted from the driver circuit may be prevented.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: September 17, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Dong-Ho Lee
  • Patent number: 10396101
    Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; a semiconductor member including a channel region overlapping the gate electrode with the gate insulating layer interposed therebetween, and a source region and a drain region that face each other with the channel region interposed therebetween; an interlayer insulating layer on the semiconductor member; a data conductor on the interlayer insulating layer; and a passivation layer on the data conductor, wherein the interlayer insulating layer has a first hole on the channel region.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: August 27, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ji Hun Lim, Joon Seok Park
  • Patent number: 10310340
    Abstract: A Liquid crystal display device and manufacturing method thereof are provided. According to an exemplary embodiment of the present disclosure, an LCD device includes: a first substrate including a display area and a non-display area disposed outside of the display area; a gate electrode disposed on the first substrate and including a first-layer gate electrode and a second-layer gate electrode disposed on the first-layer gate electrode; a pixel electrode disposed on the same layer as the first-layer gate electrode; a source electrode and a drain electrode disposed on the gate electrode to be spaced from each other; and a contact connecting the drain electrode and the pixel electrode and including a first-layer contact, which is disposed on the same layer as the pixel electrode, and a second-layer contact, which is disposed on the first-layer contact.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: June 4, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Keum Hee Lee, Man Jin Kim, Yu Jun Kim, Chang Yeol Lee, Su Jung Jung, Ji Young Jeong
  • Patent number: 10128281
    Abstract: A fabrication method includes preparing a base substrate, the base substrate including a pixel region and a region of gate on array (GOA); forming a pattern including a gate electrode and a pattern of an active layer on the base substrate, and forming a gate lead on the region of GOA, by a first patterning process; forming a pattern of a gate insulating layer by a second patterning process; forming a pattern including a source/drain electrode by a third patterning process; forming a pattern of a planarization layer by a fourth patterning layer; and forming a pattern including a pixel electrode by a fifth patterning layer. Here, the pattern including the gate electrode and the pattern including the active layer are formed by one patterning process, which can reduce the number of masks in the fabrication process of the array substrate, improve production efficiency and save the cost.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: November 13, 2018
    Assignees: BOE Technology Group Co., Ltd., Beijing BOE Optoelectronics Technology Co., Ltd.
    Inventors: Xiaohui Jiang, Jian Guo, Tiansheng Li
  • Patent number: 10084000
    Abstract: An array substrate and manufacturing method thereof, a display panel and a display device are provided. The array substrate includes a display area and a peripheral circuit area. The method includes forming an amorphous silicon thin film on the base substrate, forming a first amorphous silicon layer in the display area and a second amorphous silicon layer in the peripheral circuit area by a patterning process, so that a thickness of the first amorphous silicon layer is less than a thickness of the second amorphous silicon layer; and processing the first amorphous silicon layer and the second amorphous silicon layer simultaneously by an excimer laser annealing to form a first poly-silicon layer in the display area and a second poly-silicon layer in the peripheral circuit area, a grain size of the first poly-silicon layer being less than a grain size of the second poly-silicon layer.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: September 25, 2018
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Xueyan Tian
  • Patent number: 10054825
    Abstract: A light control device and a transparent display device including the same are discussed. In the light control device, a sealant uniformly spreads in a bonding process. The light control device includes a first substrate and a second substrate facing each other, a first electrode over one surface of the first substrate facing the second substrate, a second electrode over one surface of the second substrate facing the first substrate, a liquid crystal layer between the first electrode and the second electrode, a sealant sealing a plurality of liquid crystal cells between the first substrate and the second substrate, a first dam structure in a boundary between the sealant and the liquid crystal, and a second dam structure surrounding an outer side of the sealant. The liquid crystal layer transmits or blocks light, and the first dam structure surrounds an inner side of the sealant contacting the liquid crystal cells.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: August 21, 2018
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Sunyoung Park, JiYoung Ahn, Moonsun Lee, Pureum Kim
  • Patent number: 10056475
    Abstract: A first source electrode is formed in contact with a semiconductor layer; a first drain electrode is formed in contact with the semiconductor layer; a second source electrode which extends beyond an end portion of the first source electrode to be in contact with the semiconductor layer is formed; a second drain electrode which extends beyond an end portion of the first drain electrode to be in contact with the semiconductor layer is formed; a first sidewall is formed in contact with a side surface of the second source electrode and the semiconductor layer; a second sidewall is formed in contact with a side surface of the second drain electrode and the semiconductor layer; and a gate electrode is formed to overlap the first sidewall, the second sidewall, and the semiconductor layer with a gate insulating layer provided therebetween.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: August 21, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Matsubayashi
  • Patent number: 10031386
    Abstract: An LCD device provides enhanced display quality. An insulating layer is formed on a first substrate. The insulating layer covers the contact portion of a switching device in which the switching device is electrically connected to a transparent electrode and has an opening for exposing a portion of the transparent electrode. A reflection electrode is electrically connected to the transparent electrode through the opening. The insulation layer covers a first portion of a driving circuit formed on the first substrate. A sealant is interposed between the first and second substrate to engage the first and second substrate and to cover a second portion of the driving circuit. Therefore, the driver circuit may operate normally, and the distortion of the signal outputted from the driver circuit may be prevented.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: July 24, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Dong-Ho Lee
  • Patent number: 9921441
    Abstract: An array substrate, including a substrate, a multi-layer electrode and a switch element, is provided. The multi-layer electrode is disposed on the substrate and comprises an electric conductive layer and a first etch-stop layer. The electric conductive layer covers the first etch-stop layer. The switch element is disposed on the substrate and electrically connected to the multi-layer electrode, and has a second etch-stop layer.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: March 20, 2018
    Assignee: INNOLUX CORPORATION
    Inventor: Chien-Hung Chen
  • Patent number: 9832886
    Abstract: A method for forming a wiring according to the present invention includes: applying an ink (6) that exhibits electrical conductivity upon light absorption to a contact hole formation portion of an upper face of an insulating resin layer (3) formed on a lower wiring element (2); and irradiating the ink (6) with light to render the ink (6) conductive and also to remove a part of the insulating resin layer (3) by heat emitted from the ink (6) so as to form a contact hole (5), the part of the insulating resin layer (3) lying under the portion of the face to which the ink (6) is applied. A step of forming an upper wiring element (4) on the upper face of the insulating resin layer (3) may further be carried out, the upper wiring element (4) being electrically continuous with the lower wiring element (2) through the contact hole (5).
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: November 28, 2017
    Assignee: NATIONAL UNIVERSITY CORPORATION YAMAGATA UNIVERSITY
    Inventors: Daisuke Kumaki, Shizuo Tokito, Yu Kobayashi, Shohei Norita
  • Patent number: 9831178
    Abstract: A display substrate comprises a base substrate and a first metal layer, a second metal layer, a first electrode pattern, a second electrode pattern, a first insulating layer and a second insulating layer formed above the base substrate. The first insulating layer is located over the first metal layer, the second insulating layer is located above the first insulating layer, the first electrode pattern and the second metal layer are located between the first insulating layer and the second insulating layer; a via hole is arranged at a position directly above the first metal layer to which the first insulating layer and the second insulating layer correspond, one end of the first electrode pattern is connected with the second metal layer, the other end extends into the via hole, the second electrode pattern is in the via hole and connected with the first electrode pattern and the first metal layer.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: November 28, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Bin Feng
  • Patent number: 9812452
    Abstract: An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: November 7, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kwan-Yong Lim, James Walter Blatchford, Shashank S. Ekbote, Younsung Choi
  • Patent number: 9785024
    Abstract: An LCD device provides enhanced display quality. An insulating layer is formed on a first substrate. The insulating layer covers the contact portion of a switching device in which the switching device is electrically connected to a transparent electrode and has an opening for exposing a portion of the transparent electrode. A reflection electrode is electrically connected to the transparent electrode through the opening. The insulation layer covers a first portion of a driving circuit formed on the first substrate. A sealant is interposed between the first and second substrate to engage the first and second substrate and to cover a second portion of the driving circuit. Therefore, the driver circuit may operate normally, and the distortion of the signal outputted from the driver circuit may be prevented.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: October 10, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Dong-Ho Lee
  • Patent number: 9786633
    Abstract: A semiconductor structure includes a substrate having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The semiconductor structure also includes one or more interconnect pads having first and second opposing surfaces and one or more sides. The first surface of each one of the interconnect pads is disposed over or beneath select portions of at least the second surface of the substrate and is electrically coupled to select ones of the plurality of electrical connections. The semiconductor structure additionally includes an isolating layer having first and second opposing surfaces and openings formed in select portions of the isolating layer extending between the second surface of the isolating layer and the second surfaces of the interconnect pads. A corresponding method for fabricating a semiconductor structure is also provided.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: October 10, 2017
    Assignee: Massachusetts Institute of Technology
    Inventors: Rabindra N. Das, Peter G. Murphy, Karen E. Magoon, Noyan Kinayman, Michael J. Barbieri, Timothy M. Hancock, Mark A. Gouker
  • Patent number: 9769401
    Abstract: A solid-state imaging apparatus is provided. The apparatus comprises a pixel region where a photoelectric conversion element is arranged, a first insulating film having a first opening portion which is over the photoelectric conversion element, a first insulator comprising a first portion arranged in the first opening portion, and a second portion covering an upper surface of the first portion and an upper surface of the first insulating film, a second insulating film having a second opening portion which is over the first opening portion, and a third portion arranged in the second opening portion. A hydrogen concentration of the second portion is higher than a hydrogen concentration of the first insulating film. An upper surface area of the first portion is larger than a lower surface area of the third portion which is over the first portion.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: September 19, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takumi Ogino, Hiroshi Ikakura, Yukihiro Hayakawa
  • Patent number: 9748280
    Abstract: The present invention provides a thin film transistor and a method of fabricating the same, an array substrate and a method of fabricating the same, and a display device. The thin film transistor comprises a gate, a source, a drain, a gate insulation layer, an active layer, a passivation layer, a first electrode connection line and a second electrode connection line. The gate, the source and the drain are provided in the same layer and comprise the same material. The gate insulation layer is provided above the gate, the active layer is provided above the gate insulation layer, and a pattern of the gate insulation layer, a pattern of the gate and a pattern of the active layer coincide with each other.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: August 29, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Chunping Long, Zuqiang Wang
  • Patent number: 9740055
    Abstract: A pixel structure is provided. The pixel structure includes an active device, a first pixel electrode, a second pixel electrode, and a conductive line. The first pixel electrode is electrically connected to the active device. The second pixel electrode and the first pixel electrode are electrically insulated. The conductive line is located below the first pixel electrode and the second pixel electrode. The active device is electrically connected to the first pixel electrode through the conductive line. The conductive line is coupled to the second pixel electrode to form a coupling capacitance.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: August 22, 2017
    Assignee: Au Optronics Corporation
    Inventors: Kun-Cheng Tien, Shin-Mei Gong, Chih-Chang Shih, Chien-Huang Liao
  • Patent number: 9711580
    Abstract: A thin film transistor, an array substrate and manufacturing method thereof, and a display device are provided. The thin film transistor includes an active layer, a source electrode, a drain electrode, and a first gate electrode, the first gate electrode is shaped in a ring. The active layer includes a first portion, a second portion and a third portion for connecting the first portion and the second portion. The first portion and the second portion are disposed horizontally, and connected to the source electrode and the drain electrode, respectively. The third portion is disposed obliquely, and has a channel provided thereon. At least one part of the channel is located on an inner side of the first gate electrode. The thin film transistor can be used in a display device.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: July 18, 2017
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Li Zhang
  • Patent number: 9704759
    Abstract: Disclosed herein is a method of forming a CMOS integrated circuit product (comprised of first and second opposite type transistors) that includes forming a first spacer proximate both the first and second gate structures, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, and forming first raised epi semiconductor material source/drain regions for the first transistor. Thereafter, performing a first surface oxidation process so as to selectively form a hydrophilic material on exposed surfaces of the first raised epi semiconductor material and performing an etching process on both the transistors so as to remove the initial second spacer and the layer of second spacer material.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: July 11, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Wen Pin Peng, Min-hwa Chi, Garo Jacques Derderian
  • Patent number: 9691982
    Abstract: A method of manufacturing a thin film transistor is disclosed. In one aspect, the method includes forming an active layer over a substrate and forming a gate insulating layer containing a dopant over the active layer. The method also includes irradiating laser light onto the gate insulating layer such that the dopant of the gate insulating layer diffuses into the active layer.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: June 27, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sang-Jin Park, Myung-Ho Kim, Jun-Hwan Moon, Keun-Chang Lee, Yoon-Jong Cho
  • Patent number: 9673228
    Abstract: A display panel is provided, which includes a substrate and a first metal layer on the substrate. The first metal layer includes a gate electrode and a gate line connecting to the gate electrode. A first insulation layer is disposed on the first metal layer. A planarization layer is disposed on the first insulation layer. An opening, overlapping the gate electrode, is defined by sidewalls of the planarization layer and a surface of the first insulation layer. An active layer is disposed on the opening and the planarization layer. A second metal layer is disposed on the semiconductor layer, and includes a source electrode contacting the active layer and a data line connecting to the source electrode. The planarization layer and the first insulation layer are disposed between the data line and the gate line.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: June 6, 2017
    Assignee: INNOLUX CORPORATION
    Inventor: Kuan-Feng Lee
  • Patent number: 9634045
    Abstract: The present disclosure provides a method for forming a thin film pattern. The method includes steps of: forming a mask pattern on a thin film in such a manner that the mask pattern includes a reserved portion corresponding to a region where the thin film pattern to be formed is located, and a partially-reserved portion neighboring the reserved portion; performing a wet-etching process to etch off a portion of the thin film which is not covered by the mask pattern; performing a dry etching process to remove the partially-reserved portion and thin the reserved portion; and performing a dry etching process to etch off a portion of the thin film which is not covered by the remaining mask pattern, so as to form the thin film pattern.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: April 25, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhilian Xiao, Haisheng Zhao, Xiaoguang Pei
  • Patent number: 9634032
    Abstract: The present invention provides a manufacture method of an oxide semiconductor TFT substrate and a structure thereof.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: April 25, 2017
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Shimin Ge, Hejing Zhang, Chihyuan Tseng, Chihyu Su, Wenhui Li, Longqiang Shi, Xiaowen Lv
  • Patent number: 9627421
    Abstract: An array substrate and manufacturing method thereof and a display device. The display device includes a pixel electrode (8), including a first portion (b) in a non-display region and a second portion (a) in a display region; a first electrode (6) formed on the first portion (b) of the pixel electrode (8); a passivation layer (9) formed on the pixel electrode (8) and the first electrode (6), the passivation layer (9) includes a via hole (11) located over the first electrode (6); an active layer (4) and a second electrode (7) that are formed on the passivation layer (9), the active layer (4) being connected to the first electrode (6) through the via hole (11) of the passivation layer (9). With the array substrate and the manufacturing method thereof, the manufacturing cost is reduced, materials of the electrodes are less subjected to corrosion, and quality of the array substrate is enhanced.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: April 18, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Shuang Sun, Seungjin Choi, Jing Niu, Fangzhen Zhang
  • Patent number: 9553170
    Abstract: A manufacturing method of a thin film transistor and a thin film transistor are provided. In the manufacturing method, formation of pattern of a source electrode (7), a drain electrode (8) and an active layer (6) comprises: forming a semiconductor layer (10) and a conductive layer (11) that cover the whole substrate on the substrate in sequence; forming a first photoresist layer (4) at a region where the source electrode is to be formed and at a region where the drain electrode is to be formed on the conductive layer (11), respectively; forming a second photoresist layer (5) at least at a gap between the source electrode and the drain electrode that are to be formed on the conductive layer (11); conducting an etching process on the substrate with the first photoresist layer (4), the second photoresist layer (5), the semiconductor layer (10) and the conductive layer (11) formed thereon, so as to form pattern of the active layer (6), the source electrode (7) and the drain electrode (8).
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: January 24, 2017
    Assignees: BOE Technology Group Co., Ltd., Beijing BOE Optoelectronics Technology Co., Ltd.
    Inventors: Xuecheng Hou, Tao Wu, Jian Guo