Lateral Single Gate Single Channel Transistor With Inverted Structure, I.e., Channel Layer Is Formed After Gate (epo) Patents (Class 257/E21.414)
  • Patent number: 10937897
    Abstract: It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: March 2, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 10930680
    Abstract: A display apparatus includes a substrate, a display unit, a pad portion, and a connection wire. The display unit is on the substrate. The display unit includes a pixel circuit and a display device electrically connected to the pixel circuit. The pad portion is at one side of a peripheral area outside the display unit. The pad portion includes a first conductive layer, a second conductive layer arranged on and electrically connected to the first conductive layer, and a third conductive layer arranged on and electrically connected to the second conductive layer. The connection wire connects the pad portion and the display unit to each other to transmit a signal input to the pad portion to the display device. The connection wire includes a same material as that of the first conductive layer.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: February 23, 2021
    Assignee: Samsung Disploy Co., Ltd.
    Inventors: Jaewook Kang, Daewoo Lee, Takyoung Lee
  • Patent number: 10916738
    Abstract: The present disclosure provides a display panel, a manufacturing method of the display panel, and a display device. The manufacturing method includes: forming an auxiliary cathode layer; forming at least one tip structure on the auxiliary cathode layer; forming a main cathode layer, wherein the at least one tip structure is between the auxiliary cathode layer and the main cathode layer; and forming at least one connection between the main cathode layer and the auxiliary cathode layer by discharging at the at least one tip structure, wherein the at least one connection is electrically connected to the main cathode layer and the auxiliary cathode layer respectively.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: February 9, 2021
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Shi Sun, Xuewu Xie, Hao Liu, Ameng Zhang, Yu Ai, Bowen Liu, Yubao Kong
  • Patent number: 10777683
    Abstract: A thin film transistor, a method of manufacturing the same, an array substrate and a display panel are disclosed. The thin film transistor includes a light blocking layer, an electrode layer, and a combination layer, which are sequentially stacked. The electrode layer includes a gate electrode, a source electrode and a drain electrode which are separated from one another, and the gate electrode is located between the source electrode and the drain electrode. The light blocking layer includes a first portion of which an orthogonal projection is located between an orthogonal projection of the gate electrode and an orthogonal projection of the source electrode; and a second portion of which an orthogonal projection is located between the orthogonal projection of the gate and an orthogonal projection of the drain. The combination layer includes an active layer.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: September 15, 2020
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yang Zhang, Luke Ding, Bin Zhou, Haitao Wang, Ning Liu, Jingang Fang, Yongchao Huang, Liangchen Yan
  • Patent number: 10727256
    Abstract: A method for fabricating an array substrate, after the wet etching process of the source-drain metal layer (17), performs first ashing for the island-like photoresist pattern (19), such that the edge of the island-like photoresist pattern (19) is aligned with the edge of the source-drain metal segment (171).
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: July 28, 2020
    Assignee: HKC CORPORATION LIMITED
    Inventors: Bangtong Ge, Tingting Fu
  • Patent number: 10644162
    Abstract: A method for manufacturing an array substrate, a display panel and a display device are provided. The method includes forming a semiconductor layer, a gate insulating layer, a gate and an inter-layer insulator successively on a base substrate; forming via holes in the inter-layer insulator so as to expose portions of the semiconductor layer; performing plasma bombardment to the portions of the semiconductor layer exposed in the via holes; forming a source electrode and a drain electrode coupled with the semiconductor layer through the via holes respectively on the inter-layer insulator.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: May 5, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jiangbo Chen, Jianhua Du, Guoying Wang, Wei Liu
  • Patent number: 10586714
    Abstract: A thin film transistor substrate includes a gate electrode arranged on a substrate, a gate insulation layer arranged on the gate electrode, an active pattern arranged on the gate insulation layer, a source electrode overlapping a first end portion of the active pattern, and a drain electrode overlapping a second and opposite end portion of the active pattern. A fluorocarbon-like material is arranged on one or more of surfaces of at least one of the active pattern, the source electrode and the drain electrode, and on a photoresist pattern used in the formation process of the thin film substrate. The fluorocarbon-like material on the photoresist pattern serves to maintain a shape and size of the photoresist pattern during subsequent patterning processes.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: March 10, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyun-Min Cho, Dong-Il Kim
  • Patent number: 10566455
    Abstract: The stability of steps of processing a wiring formed using copper or the like is increased. The concentration of impurities in a semiconductor film is reduced. Electrical characteristics of a semiconductor device are improved. A semiconductor device includes a semiconductor film, a pair of first protective films in contact with the semiconductor film, a pair of conductive films containing copper or the like in contact with the pair of first protective films, a pair of second protective films in contact with the pair of conductive films on the side opposite the pair of first protective films, a gate insulating film in contact with the semiconductor film, and a gate electrode overlapping with the semiconductor film with the gate insulating film therebetween. In a cross section, side surfaces of the pair of second protective films are located on the outer side of side surfaces of the pair of conductive films.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: February 18, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masami Jintyou, Yasutaka Nakazawa, Yukinori Shima
  • Patent number: 10566461
    Abstract: A thin film transistor and a method for manufacturing the same, an array substrate, and a display device are provided in embodiments of the disclosure. The method for manufacturing a thin film transistor in embodiments of the disclosure forms a plurality of strip-shaped protrusions on a substrate by a patterning process before forming structures of various layers of the thin film transistor, and then forms sequentially a gate electrode, a gate insulating layer, an active layer, a source-drain electrode on the plurality of strip-shaped protrusions; in other words, the thin film transistor is prepared, whose channels are aligned with and shaped to be similar to the plurality of strip-shaped protrusions, in a widthwise direction thereof.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: February 18, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Hui An, Dezhi Xu, Xianxue Duan
  • Patent number: 10473991
    Abstract: The present invention provides a manufacturing method of a liquid crystal display panel, the color filter layer is formed on the TFT array substrate, at least a portion of the first color resist layer disposed on the gate line of the first substrate is used as a color resist protrusion, the spacer material and the black matrix material are integrated into same material, and the spacer and the black matrix are formed on the TFT array substrate through utilizing a multi-tone mask and only one lithography process.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: November 12, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Zhuming Deng
  • Patent number: 10431686
    Abstract: An integrated circuit (IC) employs a channel structure layout having an active semiconductor channel structure(s) and an isolated neighboring dummy semiconductor channel structure(s) for increased uniformity. A semiconductor channel structure(s) in an IC is a fin structure(s) or a gate-all-around (GAA) structure(s) employed in a Field-Effect Transistor (FET), such as a FinFET or a three-dimensional (3D) FET. The channel structures in the IC are fabricated according to a circuit cell architecture, such as a standard circuit cell (“standard cell”). The IC includes an active (e.g., diffusion) region in which a semiconductor channel structure array (e.g., semiconductor fin array) is formed according to a pattern. The IC includes a device employing a channel structure array in the active region. The channel structure array may include one active channel structure (e.g., fin) for reduced power consumption in the FinFET, and may include at least one dummy fin for increased uniformity.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: October 1, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Haining Yang, Xiangdong Chen
  • Patent number: 10416510
    Abstract: A liquid crystal display (“LCD”) device provides enhanced display quality. An insulating layer is formed on a first substrate. The insulating layer covers the contact portion of a switching device in which the switching device is electrically connected to a transparent electrode and has an opening for exposing a portion of the transparent electrode. A reflection electrode is electrically connected to the transparent electrode through the opening. The insulation layer covers a first portion of a driving circuit formed on the first substrate. A sealant is interposed between the first and second substrate to engage the first and second substrate and to cover a second portion of the driving circuit. Therefore, the driver circuit may operate normally, and the distortion of the signal outputted from the driver circuit may be prevented.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: September 17, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Dong-Ho Lee
  • Patent number: 10396101
    Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; a semiconductor member including a channel region overlapping the gate electrode with the gate insulating layer interposed therebetween, and a source region and a drain region that face each other with the channel region interposed therebetween; an interlayer insulating layer on the semiconductor member; a data conductor on the interlayer insulating layer; and a passivation layer on the data conductor, wherein the interlayer insulating layer has a first hole on the channel region.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: August 27, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ji Hun Lim, Joon Seok Park
  • Patent number: 10310340
    Abstract: A Liquid crystal display device and manufacturing method thereof are provided. According to an exemplary embodiment of the present disclosure, an LCD device includes: a first substrate including a display area and a non-display area disposed outside of the display area; a gate electrode disposed on the first substrate and including a first-layer gate electrode and a second-layer gate electrode disposed on the first-layer gate electrode; a pixel electrode disposed on the same layer as the first-layer gate electrode; a source electrode and a drain electrode disposed on the gate electrode to be spaced from each other; and a contact connecting the drain electrode and the pixel electrode and including a first-layer contact, which is disposed on the same layer as the pixel electrode, and a second-layer contact, which is disposed on the first-layer contact.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: June 4, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Keum Hee Lee, Man Jin Kim, Yu Jun Kim, Chang Yeol Lee, Su Jung Jung, Ji Young Jeong
  • Patent number: 10128281
    Abstract: A fabrication method includes preparing a base substrate, the base substrate including a pixel region and a region of gate on array (GOA); forming a pattern including a gate electrode and a pattern of an active layer on the base substrate, and forming a gate lead on the region of GOA, by a first patterning process; forming a pattern of a gate insulating layer by a second patterning process; forming a pattern including a source/drain electrode by a third patterning process; forming a pattern of a planarization layer by a fourth patterning layer; and forming a pattern including a pixel electrode by a fifth patterning layer. Here, the pattern including the gate electrode and the pattern including the active layer are formed by one patterning process, which can reduce the number of masks in the fabrication process of the array substrate, improve production efficiency and save the cost.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: November 13, 2018
    Assignees: BOE Technology Group Co., Ltd., Beijing BOE Optoelectronics Technology Co., Ltd.
    Inventors: Xiaohui Jiang, Jian Guo, Tiansheng Li
  • Patent number: 10084000
    Abstract: An array substrate and manufacturing method thereof, a display panel and a display device are provided. The array substrate includes a display area and a peripheral circuit area. The method includes forming an amorphous silicon thin film on the base substrate, forming a first amorphous silicon layer in the display area and a second amorphous silicon layer in the peripheral circuit area by a patterning process, so that a thickness of the first amorphous silicon layer is less than a thickness of the second amorphous silicon layer; and processing the first amorphous silicon layer and the second amorphous silicon layer simultaneously by an excimer laser annealing to form a first poly-silicon layer in the display area and a second poly-silicon layer in the peripheral circuit area, a grain size of the first poly-silicon layer being less than a grain size of the second poly-silicon layer.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: September 25, 2018
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Xueyan Tian
  • Patent number: 10054825
    Abstract: A light control device and a transparent display device including the same are discussed. In the light control device, a sealant uniformly spreads in a bonding process. The light control device includes a first substrate and a second substrate facing each other, a first electrode over one surface of the first substrate facing the second substrate, a second electrode over one surface of the second substrate facing the first substrate, a liquid crystal layer between the first electrode and the second electrode, a sealant sealing a plurality of liquid crystal cells between the first substrate and the second substrate, a first dam structure in a boundary between the sealant and the liquid crystal, and a second dam structure surrounding an outer side of the sealant. The liquid crystal layer transmits or blocks light, and the first dam structure surrounds an inner side of the sealant contacting the liquid crystal cells.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: August 21, 2018
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Sunyoung Park, JiYoung Ahn, Moonsun Lee, Pureum Kim
  • Patent number: 10056475
    Abstract: A first source electrode is formed in contact with a semiconductor layer; a first drain electrode is formed in contact with the semiconductor layer; a second source electrode which extends beyond an end portion of the first source electrode to be in contact with the semiconductor layer is formed; a second drain electrode which extends beyond an end portion of the first drain electrode to be in contact with the semiconductor layer is formed; a first sidewall is formed in contact with a side surface of the second source electrode and the semiconductor layer; a second sidewall is formed in contact with a side surface of the second drain electrode and the semiconductor layer; and a gate electrode is formed to overlap the first sidewall, the second sidewall, and the semiconductor layer with a gate insulating layer provided therebetween.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: August 21, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Matsubayashi
  • Patent number: 10031386
    Abstract: An LCD device provides enhanced display quality. An insulating layer is formed on a first substrate. The insulating layer covers the contact portion of a switching device in which the switching device is electrically connected to a transparent electrode and has an opening for exposing a portion of the transparent electrode. A reflection electrode is electrically connected to the transparent electrode through the opening. The insulation layer covers a first portion of a driving circuit formed on the first substrate. A sealant is interposed between the first and second substrate to engage the first and second substrate and to cover a second portion of the driving circuit. Therefore, the driver circuit may operate normally, and the distortion of the signal outputted from the driver circuit may be prevented.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: July 24, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Dong-Ho Lee
  • Patent number: 9921441
    Abstract: An array substrate, including a substrate, a multi-layer electrode and a switch element, is provided. The multi-layer electrode is disposed on the substrate and comprises an electric conductive layer and a first etch-stop layer. The electric conductive layer covers the first etch-stop layer. The switch element is disposed on the substrate and electrically connected to the multi-layer electrode, and has a second etch-stop layer.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: March 20, 2018
    Assignee: INNOLUX CORPORATION
    Inventor: Chien-Hung Chen
  • Patent number: 9831178
    Abstract: A display substrate comprises a base substrate and a first metal layer, a second metal layer, a first electrode pattern, a second electrode pattern, a first insulating layer and a second insulating layer formed above the base substrate. The first insulating layer is located over the first metal layer, the second insulating layer is located above the first insulating layer, the first electrode pattern and the second metal layer are located between the first insulating layer and the second insulating layer; a via hole is arranged at a position directly above the first metal layer to which the first insulating layer and the second insulating layer correspond, one end of the first electrode pattern is connected with the second metal layer, the other end extends into the via hole, the second electrode pattern is in the via hole and connected with the first electrode pattern and the first metal layer.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: November 28, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Bin Feng
  • Patent number: 9832886
    Abstract: A method for forming a wiring according to the present invention includes: applying an ink (6) that exhibits electrical conductivity upon light absorption to a contact hole formation portion of an upper face of an insulating resin layer (3) formed on a lower wiring element (2); and irradiating the ink (6) with light to render the ink (6) conductive and also to remove a part of the insulating resin layer (3) by heat emitted from the ink (6) so as to form a contact hole (5), the part of the insulating resin layer (3) lying under the portion of the face to which the ink (6) is applied. A step of forming an upper wiring element (4) on the upper face of the insulating resin layer (3) may further be carried out, the upper wiring element (4) being electrically continuous with the lower wiring element (2) through the contact hole (5).
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: November 28, 2017
    Assignee: NATIONAL UNIVERSITY CORPORATION YAMAGATA UNIVERSITY
    Inventors: Daisuke Kumaki, Shizuo Tokito, Yu Kobayashi, Shohei Norita
  • Patent number: 9812452
    Abstract: An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: November 7, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kwan-Yong Lim, James Walter Blatchford, Shashank S. Ekbote, Younsung Choi
  • Patent number: 9786633
    Abstract: A semiconductor structure includes a substrate having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The semiconductor structure also includes one or more interconnect pads having first and second opposing surfaces and one or more sides. The first surface of each one of the interconnect pads is disposed over or beneath select portions of at least the second surface of the substrate and is electrically coupled to select ones of the plurality of electrical connections. The semiconductor structure additionally includes an isolating layer having first and second opposing surfaces and openings formed in select portions of the isolating layer extending between the second surface of the isolating layer and the second surfaces of the interconnect pads. A corresponding method for fabricating a semiconductor structure is also provided.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: October 10, 2017
    Assignee: Massachusetts Institute of Technology
    Inventors: Rabindra N. Das, Peter G. Murphy, Karen E. Magoon, Noyan Kinayman, Michael J. Barbieri, Timothy M. Hancock, Mark A. Gouker
  • Patent number: 9785024
    Abstract: An LCD device provides enhanced display quality. An insulating layer is formed on a first substrate. The insulating layer covers the contact portion of a switching device in which the switching device is electrically connected to a transparent electrode and has an opening for exposing a portion of the transparent electrode. A reflection electrode is electrically connected to the transparent electrode through the opening. The insulation layer covers a first portion of a driving circuit formed on the first substrate. A sealant is interposed between the first and second substrate to engage the first and second substrate and to cover a second portion of the driving circuit. Therefore, the driver circuit may operate normally, and the distortion of the signal outputted from the driver circuit may be prevented.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: October 10, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Dong-Ho Lee
  • Patent number: 9769401
    Abstract: A solid-state imaging apparatus is provided. The apparatus comprises a pixel region where a photoelectric conversion element is arranged, a first insulating film having a first opening portion which is over the photoelectric conversion element, a first insulator comprising a first portion arranged in the first opening portion, and a second portion covering an upper surface of the first portion and an upper surface of the first insulating film, a second insulating film having a second opening portion which is over the first opening portion, and a third portion arranged in the second opening portion. A hydrogen concentration of the second portion is higher than a hydrogen concentration of the first insulating film. An upper surface area of the first portion is larger than a lower surface area of the third portion which is over the first portion.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: September 19, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takumi Ogino, Hiroshi Ikakura, Yukihiro Hayakawa
  • Patent number: 9748280
    Abstract: The present invention provides a thin film transistor and a method of fabricating the same, an array substrate and a method of fabricating the same, and a display device. The thin film transistor comprises a gate, a source, a drain, a gate insulation layer, an active layer, a passivation layer, a first electrode connection line and a second electrode connection line. The gate, the source and the drain are provided in the same layer and comprise the same material. The gate insulation layer is provided above the gate, the active layer is provided above the gate insulation layer, and a pattern of the gate insulation layer, a pattern of the gate and a pattern of the active layer coincide with each other.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: August 29, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Chunping Long, Zuqiang Wang
  • Patent number: 9740055
    Abstract: A pixel structure is provided. The pixel structure includes an active device, a first pixel electrode, a second pixel electrode, and a conductive line. The first pixel electrode is electrically connected to the active device. The second pixel electrode and the first pixel electrode are electrically insulated. The conductive line is located below the first pixel electrode and the second pixel electrode. The active device is electrically connected to the first pixel electrode through the conductive line. The conductive line is coupled to the second pixel electrode to form a coupling capacitance.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: August 22, 2017
    Assignee: Au Optronics Corporation
    Inventors: Kun-Cheng Tien, Shin-Mei Gong, Chih-Chang Shih, Chien-Huang Liao
  • Patent number: 9711580
    Abstract: A thin film transistor, an array substrate and manufacturing method thereof, and a display device are provided. The thin film transistor includes an active layer, a source electrode, a drain electrode, and a first gate electrode, the first gate electrode is shaped in a ring. The active layer includes a first portion, a second portion and a third portion for connecting the first portion and the second portion. The first portion and the second portion are disposed horizontally, and connected to the source electrode and the drain electrode, respectively. The third portion is disposed obliquely, and has a channel provided thereon. At least one part of the channel is located on an inner side of the first gate electrode. The thin film transistor can be used in a display device.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: July 18, 2017
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Li Zhang
  • Patent number: 9704759
    Abstract: Disclosed herein is a method of forming a CMOS integrated circuit product (comprised of first and second opposite type transistors) that includes forming a first spacer proximate both the first and second gate structures, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, and forming first raised epi semiconductor material source/drain regions for the first transistor. Thereafter, performing a first surface oxidation process so as to selectively form a hydrophilic material on exposed surfaces of the first raised epi semiconductor material and performing an etching process on both the transistors so as to remove the initial second spacer and the layer of second spacer material.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: July 11, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Wen Pin Peng, Min-hwa Chi, Garo Jacques Derderian
  • Patent number: 9691982
    Abstract: A method of manufacturing a thin film transistor is disclosed. In one aspect, the method includes forming an active layer over a substrate and forming a gate insulating layer containing a dopant over the active layer. The method also includes irradiating laser light onto the gate insulating layer such that the dopant of the gate insulating layer diffuses into the active layer.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: June 27, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sang-Jin Park, Myung-Ho Kim, Jun-Hwan Moon, Keun-Chang Lee, Yoon-Jong Cho
  • Patent number: 9673228
    Abstract: A display panel is provided, which includes a substrate and a first metal layer on the substrate. The first metal layer includes a gate electrode and a gate line connecting to the gate electrode. A first insulation layer is disposed on the first metal layer. A planarization layer is disposed on the first insulation layer. An opening, overlapping the gate electrode, is defined by sidewalls of the planarization layer and a surface of the first insulation layer. An active layer is disposed on the opening and the planarization layer. A second metal layer is disposed on the semiconductor layer, and includes a source electrode contacting the active layer and a data line connecting to the source electrode. The planarization layer and the first insulation layer are disposed between the data line and the gate line.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: June 6, 2017
    Assignee: INNOLUX CORPORATION
    Inventor: Kuan-Feng Lee
  • Patent number: 9634045
    Abstract: The present disclosure provides a method for forming a thin film pattern. The method includes steps of: forming a mask pattern on a thin film in such a manner that the mask pattern includes a reserved portion corresponding to a region where the thin film pattern to be formed is located, and a partially-reserved portion neighboring the reserved portion; performing a wet-etching process to etch off a portion of the thin film which is not covered by the mask pattern; performing a dry etching process to remove the partially-reserved portion and thin the reserved portion; and performing a dry etching process to etch off a portion of the thin film which is not covered by the remaining mask pattern, so as to form the thin film pattern.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: April 25, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhilian Xiao, Haisheng Zhao, Xiaoguang Pei
  • Patent number: 9634032
    Abstract: The present invention provides a manufacture method of an oxide semiconductor TFT substrate and a structure thereof.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: April 25, 2017
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Shimin Ge, Hejing Zhang, Chihyuan Tseng, Chihyu Su, Wenhui Li, Longqiang Shi, Xiaowen Lv
  • Patent number: 9627421
    Abstract: An array substrate and manufacturing method thereof and a display device. The display device includes a pixel electrode (8), including a first portion (b) in a non-display region and a second portion (a) in a display region; a first electrode (6) formed on the first portion (b) of the pixel electrode (8); a passivation layer (9) formed on the pixel electrode (8) and the first electrode (6), the passivation layer (9) includes a via hole (11) located over the first electrode (6); an active layer (4) and a second electrode (7) that are formed on the passivation layer (9), the active layer (4) being connected to the first electrode (6) through the via hole (11) of the passivation layer (9). With the array substrate and the manufacturing method thereof, the manufacturing cost is reduced, materials of the electrodes are less subjected to corrosion, and quality of the array substrate is enhanced.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: April 18, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Shuang Sun, Seungjin Choi, Jing Niu, Fangzhen Zhang
  • Patent number: 9553170
    Abstract: A manufacturing method of a thin film transistor and a thin film transistor are provided. In the manufacturing method, formation of pattern of a source electrode (7), a drain electrode (8) and an active layer (6) comprises: forming a semiconductor layer (10) and a conductive layer (11) that cover the whole substrate on the substrate in sequence; forming a first photoresist layer (4) at a region where the source electrode is to be formed and at a region where the drain electrode is to be formed on the conductive layer (11), respectively; forming a second photoresist layer (5) at least at a gap between the source electrode and the drain electrode that are to be formed on the conductive layer (11); conducting an etching process on the substrate with the first photoresist layer (4), the second photoresist layer (5), the semiconductor layer (10) and the conductive layer (11) formed thereon, so as to form pattern of the active layer (6), the source electrode (7) and the drain electrode (8).
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: January 24, 2017
    Assignees: BOE Technology Group Co., Ltd., Beijing BOE Optoelectronics Technology Co., Ltd.
    Inventors: Xuecheng Hou, Tao Wu, Jian Guo
  • Patent number: 9525035
    Abstract: A vertical, high-voltage MOS transistor, which has a source region, a body contact region, and a number of trenches structures with field plates, and a method of forming the MOS transistor increase the on-state resistance of the MOS transistor by reducing the trench pitch. Trench pitch can be reduced with metal contacts that simultaneously touch the source regions, the body contact regions, and the field plates. Trench pitch can also be reduced with a gate that increases the size of the LDD region.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: December 20, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Christopher Boguslaw Kocon, Simon John Molloy, John Manning Savidge Neilson, Hideaki Kawahara
  • Patent number: 9508592
    Abstract: To improve the reliability of a semiconductor device including a low-resistance material such as copper, aluminum, gold, or silver as a wiring. Provided is a semiconductor device including a pair of electrodes electrically connected to a semiconductor layer which has a stacked-layer structure including a first protective layer in contact with the semiconductor layer and a conductive layer containing the low-resistance material and being over and in contact with the first protective layer. The top surface of the conductive layer is covered with a second protective layer functioning as a mask for processing the conductive layer. The side surface of the conductive layer is covered with a third protective layer. With this structure, entry or diffusion of the constituent element of the pair of conductive layers containing the low-resistance material into the semiconductor layer is suppressed.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: November 29, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Masami Jintyou, Yukinori Shima, Takahiro Iguchi
  • Patent number: 9502536
    Abstract: Provided is a manufacturing method of a thin film transistor array panel including: formation of a gate line including a gate electrode on a substrate; formation of sequentially a gate insulating layer, an active layer, a data metal layer, and a photoresist etching mask pattern on the gate line; etching the data metal layer with the same shape as the photoresist etching mask pattern; etching the active layer by using the photoresist etching mask pattern; formation of a data line including a source electrode and a drain electrode for completing a channel region on the active layer; and formation of a pixel electrode exposing the drain electrode and electrically connected with the drain electrode, in which in the etching of the active layer, a dry-etch process is performed by using gas including at least one of NF3 and H2.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: November 22, 2016
    Assignee: Samsund Display Co., Ltd.
    Inventors: Dong Il Kim, Joo Hyung Lee, Jae Woo Jeong
  • Patent number: 9450211
    Abstract: A method of manufacturing an organic light-emitting display device is provided. The method includes forming a pixel electrode, forming a hydrophobic material layer on the pixel electrode, wherein the hydrophobic material layer includes a hydrophobic material, forming a pixel-defining layer by patterning the hydrophobic material layer, so as to expose at least a portion of the pixel electrode, and removing the hydrophobic material on the exposed portion of the pixel electrode using surface treatment.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: September 20, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ki-Wan Ahn, Jae-Hyuck Jang
  • Patent number: 9450077
    Abstract: A method of manufacturing a thin film transistor substrate is provided, including a first photoresist pattern covers a channel during a process of etching a second photoresist pattern and protects the channel. Thus, an etching stop layer is not required.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: September 20, 2016
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Kuo-Lung Fang, Yi-Chun Kao, Po-Li Shih, Chih-Lung Lee, Hsin-Hua Lin
  • Patent number: 9412623
    Abstract: A method including providing a substrate with a gate, a layer of gate insulator material adjacent the gate, and a layer of metal oxide semiconductor material positioned on the gate insulator opposite the gate, forming a selectively patterned etch stop passivation layer and heating at elevated temperature in an oxygen-containing or nitrogen-containing or inert ambience to selectively increase the carrier concentration in regions of the metal oxide semiconductor not covered by the etch stop layer, on which overlying and spaced apart source/drain metals are formed. Subsequently heating the transistor in an oxygen-containing or nitrogen-containing or inert ambience to further improve the source/drain contacts and adjust the threshold voltage to a desired level. Providing additional passivation layer(s) on top of the transistor with electric insulation and barrier property to moisture and chemicals in the surrounding environment.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: August 9, 2016
    Assignee: CBRITE INC.
    Inventors: Gang Yu, Chan-Long Shieh, Tian Xiao, Fatt Foong
  • Patent number: 9389477
    Abstract: A semiconductor device includes TFTs designed in accordance with characteristics of circuits. In a first structure of the invention, the TFT is formed by using a crystalline silicon film made of a unique crystal structure body. The crystal structure body has a structure in which rod-like or flattened rod-like crystals grow in a direction parallel to each other. In a second structure of the invention, growth distances of lateral growth regions are made different from each other in accordance with channel lengths, of the TFTs. By this, characteristics of TFTs formed in one lateral growth region can be made as uniform as possible.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: July 12, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani
  • Patent number: 9373525
    Abstract: An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: June 21, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Shinya Sasagawa, Taiga Muraoka
  • Patent number: 9245978
    Abstract: Disclosed are a self-aligned thin film transistor controlling a diffusion length of a doping material using a doping barrier in a thin film transistor having a self-aligned structure and a method of manufacturing the same. The self-aligned thin film transistor with a doping barrier includes: an active layer formed on a substrate and having a first doping region, a second doping region, and a channel region; a gate insulating film formed on the channel region; a gate electrode formed on the gate insulating film; a doping source film formed on the first doping region and the second doping region; and a doping barrier formed between the doping source film and the first doping region and between the doping source film and the second doping region.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: January 26, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Chi Sun Hwang, Sang Hee Park, Him Chan Oh
  • Patent number: 9018109
    Abstract: A thin film transistor in which deterioration at initial operation is not likely to be caused and a manufacturing method thereof. A transistor which includes a gate insulating layer at least whose uppermost surface is a silicon nitride layer, a semiconductor layer over the gate insulating layer, and a buffer layer over the semiconductor layer and in which the concentration of nitrogen in the vicinity of an interface between the semiconductor layer and the gate insulating layer, which is in the semiconductor layer is lower than that of the buffer layer and other parts of the semiconductor layer. Such a thin film transistor can be manufactured by exposing the gate insulating layer to an air atmosphere and performing plasma treatment on the gate insulating layer before the semiconductor layer is formed.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: April 28, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Erika Kato, Kunihiko Suzuki
  • Patent number: 9012275
    Abstract: A method of forming TFT is provided. The TFT includes a gate electrode, a gate insulating layer, a first protective pattern, a second protective pattern, a source electrode, a drain electrode, a semiconductor channel layer, and a passivation layer. The first protective pattern and the second protective pattern are disposed on the gate insulating layer above the gate electrode. The source electrode is disposed on the gate insulating layer and the first protective pattern. The drain electrode is disposed on the gate insulating layer and the second protective pattern. The semiconductor channel layer is disposed on the gate insulating layer, the source electrode, and the drain electrode. In an extending direction from the source electrode to the drain electrode, a length of the first protective pattern is shorter than that of the source electrode, and a length of the second protective pattern is shorter than that of the drain electrode.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: April 21, 2015
    Assignee: AU Optronics Corp.
    Inventors: Chung-Tao Chen, Wu-Hsiung Lin, Po-Hsueh Chen
  • Patent number: 8993386
    Abstract: An object is to provide a semiconductor device including a semiconductor element which has favorable characteristics. A manufacturing method of the present invention includes the steps of: forming a first conductive layer which functions as a gate electrode over a substrate; forming a first insulating layer to cover the first conductive layer; forming a semiconductor layer over the first insulating layer so that part of the semiconductor layer overlaps with the first conductive layer; forming a second conductive layer to be electrically connected to the semiconductor layer; forming a second insulating layer to cover the semiconductor layer and the second conductive layer; forming a third conductive layer to be electrically connected to the second conductive layer; performing first heat treatment after forming the semiconductor layer and before forming the second insulating layer; and performing second heat treatment after forming the second insulating layer.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Ohara, Toshinari Sasaki
  • Patent number: 8969163
    Abstract: A method of forming a semiconductor structure may include preparing a continuous active layer in a region of the substrate and forming a plurality of adjacent gates on the continuous active layer. A first raised epitaxial layer may be deposited on a recessed region of the continuous active layer between a first and a second one of the plurality of gates, whereby the first and second gates are adjacent. A second raised epitaxial layer may be deposited on another recessed region of the continuous active layer between the second and a third one of the plurality of gates, whereby the second and third gates are adjacent. Using a cut mask, a trench structure is etched into the second gate structure and a region underneath the second gate in the continuous active layer. The trench is filled with isolation material for electrically isolating the first and second raised epitaxial layers.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael V. Aquilino, Byeong Yeol Kim, Ying Li, Carl John Radens
  • Patent number: 8962377
    Abstract: A method of fabricating a pixelated imager includes providing a substrate with bottom contact layer and sensing element blanket layers on the contact layer. The blanket layers are separated into an array of sensing elements by trenches isolating adjacent sensing elements. A sensing element electrode is formed adjacent each sensing element overlying a trench and defining a TFT. A layer of metal oxide semiconductor (MOS) material is formed on a dielectric layer overlying the electrodes and on an exposed upper surface of the blanket layers defining the sensing element adjacent each TFT. A layer of metal is deposited on each TFT and separated into source/drain electrodes on opposite sides of the sensing element electrode. The metal forming one of the S/D electrodes contacts the MOS material overlying the exposed surface of the semiconductor layer, whereby each sensing element in the array is electrically connected to the adjacent TFT by the MOS material.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: February 24, 2015
    Assignee: Cbrite Inc.
    Inventors: Chan-Long Shieh, Gang Yu