Lateral Single Gate Single Channel Transistor With Inverted Structure, I.e., Channel Layer Is Formed After Gate (epo) Patents (Class 257/E21.414)
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Patent number: 12242161Abstract: The present application provides an array substrate and a display panel. The array substrate includes a gate of a thin film transistor; a first electrode of the transistor, including a first body and a first end; a second electrode of the transistor, including a second body and a second end; orthographic projections of the first body and the second body being located in an orthographic projection of the gate, orthographic projections of at least partial area of the first end and at least partial area of the second end not overlapping with the orthographic projection of the gate, an orthographic projections of the first end and the second end being both located on the same side of the orthographic projection of the gate; in a first direction, an average distance from the first end to the second end is greater than that from the first body to the second body.Type: GrantFiled: April 27, 2022Date of Patent: March 4, 2025Assignees: CHENGDU BOE DISPLAY SCI-TECH CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Feng Xiao, Liangjun Liu, Wei Zhu
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Patent number: 12244344Abstract: In a multi-cell wireless communication system (100) with at least one optical access point (120) and at least one radio frequency access point (120), more flexibility is provided to an end device (110) in selecting an access point (120) for establishing a data link. Because of the line-of-sight characteristic of an optical link and the limited field of view of an optical receiver, optical cells are typically deployed with a relatively high density and adjacent optical cells may have an overlapping area. This invention discloses a method of an end device (110) for selecting a favorable access point (120) with reduced overhead, even when the end device is located in the overlapping area of two adjacent optical cells.Type: GrantFiled: May 18, 2021Date of Patent: March 4, 2025Assignee: SIGNIFY HOLDING B.V.Inventors: Michel Germe, Haimin Tao, Andreas Felix Alfred Bluschke, Christian Jordan
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Patent number: 12230745Abstract: A display device and a manufacturing method thereof are disclosed. The display device may include a pixel circuit layer including a plurality of transistors, a first partition wall and a second partition wall on the pixel circuit layer, and each protruding in a thickness direction, a first electrode and a second electrode formed on the same layer, and on the first partition wall and the second partition wall, respectively; a light emitting element between the first electrode and the second electrode; and a first organic pattern directly on the light emitting element.Type: GrantFiled: July 19, 2023Date of Patent: February 18, 2025Assignee: Samsung Display Co., Ltd.Inventors: Jun Hong Park, Tae Gyun Kim, Jun Chun, Eui Suk Jung, Hyun Young Jung
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Patent number: 12228831Abstract: An array substrate and a display device are provided. The array substrate includes a base substrate, gate lines and a metal layer on the base substrate. The metal layer is located on a side of the gate lines away from the base substrate, and includes data lines, a first connecting portion and a first electrode and a second electrode of a thin film transistor. The first electrode is electrically connected to a pixel electrode by the first connecting portion. A gate line includes a gate line pad which includes a protrusion protruding towards a pixel region relative to the portion of the gate line other than the gate line pad. The metal layer located in the pixel region includes a plurality of traces extending along at least part of a contour of the pixel region and including first traces surrounding the protrusion.Type: GrantFiled: June 15, 2022Date of Patent: February 18, 2025Assignee: CHENGDU BOE DISPLAY SCI-TECH CO., LTD.Inventors: Chunping Long, Yongda Ma
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Patent number: 12225783Abstract: An organic light-emitting diode display panel includes a display area, a transparent area, and a wire exchange area. The display area is used for displaying an image; the transparent area is used for placing a device, and the wire exchange area is positioned at a wire connecting site between the display area and the transparent area, wherein a metal wire from the display area is electrically connected to a high light-transmissive metal wire through a via-hole at the wire exchange area, and the high light-transmissive metal wire extends to the transparent area.Type: GrantFiled: July 18, 2019Date of Patent: February 11, 2025Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.Inventor: Yexi Sun
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Patent number: 12225727Abstract: A 3D memory device including: a first structure including a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel, where the memory cell includes at least one charge trap structure, and where the at least one memory transistor is self-aligned to an overlaying another the at least one memory transistor, both being processed following a same lithography step; and a control level including a memory controller circuit, where the control level includes a plurality of latch sense amplifiers, where the control level is bonded to the first structure, and where the bonded includes hybrid bonding.Type: GrantFiled: June 10, 2024Date of Patent: February 11, 2025Assignee: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Jin-Woo Han, Eli Lusky
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Patent number: 12225776Abstract: A display panel includes: a substrate on which pixels are disposed; a bank which defines a light emitting area of the pixels; a light emitting layer formed in the light emitting area, the bank includes: a hydrophilic bank which extends in a row direction and separates pixel rows; a first hydrophobic bank which is formed on the hydrophilic bank; and a second hydrophobic bank which extends in a column direction and separates pixel columns, and the first hydrophobic bank has a lower hydrophobic property than that of the second hydrophobic bank.Type: GrantFiled: December 10, 2021Date of Patent: February 11, 2025Assignee: LG Display Co., Ltd.Inventor: Kanghyun Kim
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Patent number: 12224332Abstract: The purpose of the present invention is to suppress a change in characteristics of a TFT using an oxide semiconductor film caused by that oxygen in the oxide semiconductor film is extracted by metal electrode. The main structure of the present invention is as follows. A semiconductor device having a TFT, in which a gate insulating film is formed on a gate electrode, and an oxide semiconductor film is formed on the gate insulating film; the oxide semiconductor film including a channel region, a drain region, and a source region; in which a metal nitride film is formed on a top surface of the gate electrode in an opposing portion to the channel region in a plan view; and the metal nitride film is not formed at a part of the top surface of the gate electrode.Type: GrantFiled: March 30, 2022Date of Patent: February 11, 2025Assignee: Japan Display Inc.Inventors: Akihiro Hanada, Takuo Kaitoh, Hajime Watakabe
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Patent number: 12210256Abstract: A control switch of a drive circuit, an array substrate, and a display panel are disclosed. The control switch includes a thin film transistor. In the thin film transistor, each source branch directly connected to a source lead is a first source branch, and each source branch not directly connected to the source lead is a second source branch. A channel width between the first source branch and the adjacent drain branch is greater than that between the second source branch and the adjacent drain branch.Type: GrantFiled: December 31, 2021Date of Patent: January 28, 2025Assignees: MIANYANG HKC OPTOELECTRONICS TECHNOLOGY CO., LTD, HKC CORPORATION LIMITEDInventors: Zhenghang He, Baohong Kang
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Patent number: 12183830Abstract: A display device includes a metal layer composed of multiple layers including a lowermost layer lower in an ionization tendency than a middle layer, the lowermost layer being in contact with and on the oxide semiconductor layer. Each channel region is interposed between a corresponding one of the first electrodes and a corresponding one of the second electrodes, constituting a corresponding one of the thin film transistors. The oxide semiconductor layer is continuous between a pair of channel regions included in an adjacent pair of thin film transistors. The metal layer is continuous between a pair of first electrodes included in the adjacent pair of thin film transistors.Type: GrantFiled: January 26, 2022Date of Patent: December 31, 2024Assignee: Japan Display Inc.Inventor: Yohei Yamaguchi
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Patent number: 12174500Abstract: According to an aspect, a display device includes: an array substrate comprising reflective electrodes arrayed in a matrix having a row-column configuration in a first direction and a second direction and a light-transmitting conductive layer at least partially overlapping any one of the reflective electrodes when viewed in a third direction orthogonal to the first direction and the second direction; a counter substrate comprising a common electrode overlapping the reflective electrodes when viewed in the third direction and a color filter including a plurality of colors; and a backlight. The array substrate is disposed between the counter substrate and the backlight. Part of the light-transmitting conductive layer protrudes between two reflective electrodes adjacently disposed in the first direction among the reflective electrodes.Type: GrantFiled: November 30, 2022Date of Patent: December 24, 2024Assignee: Japan Display Inc.Inventors: Takayuki Nakao, Takehiro Shima
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Patent number: 12154915Abstract: A display device includes: a first gate insulating film; a first interlayer insulating film; a lower metal layer; an oxide semiconductor layer; a second gate insulating film; a second gate electrode; a second interlayer insulating film; and an upper metal layer being sequentially provided on a substrate, wherein the oxide semiconductor layer includes a second channel region and a second conductor region, the second gate insulating film is disposed in alignment with the second gate electrode, a first contact hole is provided in the first gate insulating film and the first interlayer insulating film, the lower metal layer includes a second conductor connection wiring line, a protection layer having an island shape is provided between the second conductor region and the second interlayer insulating film, a second contact hole exposing the second conductor connection wiring line is provided in the protection layer and the second interlayer insulating film.Type: GrantFiled: April 17, 2019Date of Patent: November 26, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Kazuatsu Ito, Hirohide Mimura, Masahito Sano
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Patent number: 12142610Abstract: A method of manufacturing a thin film transistor and a display device are disclosed. The method includes: forming a gate metal layer, a gate insulating layer, an active layer, an ohmic contact layer sequentially on a substrate; producing a photoresist layer on the metal layer where the portion of the photoresist layer at the channel region has a smaller thickness than other portions; a first wet etching in which the metal layer corresponding to the photoresist layer is obtained; a first drying etching in which the active layer and ohmic contact layer corresponding to the photoresist layer are Obtained; a second wet etching in which the portion of the metal layer corresponding to the channel region removed; and a second dry etching in which the portion of the active layer corresponding to the channel region is made to have a smaller thickness than other portions of the active layer.Type: GrantFiled: June 24, 2020Date of Patent: November 12, 2024Assignees: HKC CORPORATION LIMITED, CHUZHOU HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Yuming Xia, En-Tsung Cho, Wanfei Yong
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Patent number: 12133414Abstract: A display apparatus includes a first substrate, a second substrate, and a transistor. The first transistor includes a polymer resin. The second substrate is arranged between the first substrate and the transistor and includes a glass material. A liquidus temperature of the glass material is less than 1000° C. The transistor overlaps at least one of the first substrate and the second substrate and includes a semiconductor layer.Type: GrantFiled: December 5, 2023Date of Patent: October 29, 2024Assignee: Samsung Display Co., Ltd.Inventor: Hun Kim
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Patent number: 12120915Abstract: A display device includes a drive transistor and a switching transistor formed by layering an inorganic insulating film, an oxide semiconductor layer, an upper gate insulating layer, an upper gate electrode, and an interlayer insulating film. The drive transistor and the switching transistor include an oxide semiconductor film formed of the oxide semiconductor layer and provided in an island shape corresponding to the drive transistor and an island shape corresponding to the switching transistor, and the oxide semiconductor film includes a channel region overlapping with the upper gate electrode corresponding to the oxide semiconductor film, and a source region and a drain region. The drive transistor is provided with a lower gate electrode and a lower gate insulating layer between the inorganic insulating film and the oxide semiconductor layer. The length of lower gate electrode is less than or equal to the length of upper gate electrode.Type: GrantFiled: September 18, 2018Date of Patent: October 15, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Tadayoshi Miyamoto, Yoshinobu Nakamura, Kayo Haruguchi
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Patent number: 12112669Abstract: A display device includes a display region and a periphery region surrounding the display region. The display device includes an driving circuit substrate, a TFT array substrate, a front plane laminate, and multiple conductive wires. The driving circuit substrate includes multiple first conductive pads. The TFT array substrate includes multiple second conductive pads. The TFT array substrate is located on the driving circuit substrate. The TFT array substrate is located between the driving circuit substrate and the front plane laminate. The conductive wires are electrically connected with the first conductive pads and the second conductive pads, respectively. The first conductive pads and the second conductive pads are located in the periphery region.Type: GrantFiled: April 7, 2023Date of Patent: October 8, 2024Assignee: E Ink Holdings Inc.Inventors: Shu-Fen Tsai, Chen-Yun Ma, Puru Howard Shieh, Chih-Ching Wang
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Patent number: 12113115Abstract: A thin film transistor may be manufactured by forming a gate electrode in an insulating layer over a substrate, forming a gate dielectric over the gate electrode and the insulating layer, forming an active layer over the gate electrode, and forming a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. A surface oxygen concentration may be increased in at least one of the gate dielectric and the active layer by introducing oxygen atoms into a surface region of a respective one of the gate dielectric and the active layer.Type: GrantFiled: September 7, 2021Date of Patent: October 8, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Wu-Wei Tsai, Chun-Chieh Lu, Hai-Ching Chen, Yu-Ming Lin, Sai-Hooi Yeong
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Patent number: 12080720Abstract: An object of an embodiment of the present invention is to manufacture a semiconductor device with high display quality and high reliability, which includes a pixel portion and a driver circuit portion capable of high-speed operation over one substrate, using transistors having favorable electric characteristics and high reliability as switching elements. Two kinds of transistors, in each of which an oxide semiconductor layer including a crystalline region on one surface side is used as an active layer, are formed in a driver circuit portion and a pixel portion. Electric characteristics of the transistors can be selected by choosing the position of the gate electrode layer which determines the position of the channel. Thus, a semiconductor device including a driver circuit portion capable of high-speed operation and a pixel portion over one substrate can be manufactured.Type: GrantFiled: June 8, 2023Date of Patent: September 3, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Hiroyuki Miyake
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Patent number: 12082448Abstract: In order to provide a display apparatus with improved durability and improved impact resistance and a method of manufacturing the same, the disclosure provides a display apparatus and a method of manufacturing the same, the display apparatus including a substrate, a semiconductor layer disposed on the substrate, an insulating layer covering the semiconductor layer and including a first hole exposing a portion of the semiconductor layer, a first conductive layer disposed on the insulating layer and including a second hole overlapping the first hole, and a second conductive layer in contact with the portion of the semiconductor layer via the first hole and the second hole.Type: GrantFiled: August 24, 2021Date of Patent: September 3, 2024Assignee: Samsung Display Co., Ltd.Inventors: Changwoo Shim, Hyuntae Kim
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Patent number: 12069416Abstract: A screen sounding device and a display device are disclosed. The screen sounding device includes a sounding structure. The sounding structure includes a first electrode, an insulating layer, and a second electrode stacked in sequence. A sounding cavity is formed between a vibrating portion of the second electrode and the insulating layer. The first electrode and the second electrode receive different driving signals, and the vibrating portion can drive the air in the sounding cavity to vibrate and sound. The screen sounding device of the present disclosure has a desirable sounding effect, various setting positions, and low manufacturing costs.Type: GrantFiled: December 14, 2021Date of Patent: August 20, 2024Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.Inventor: Xiaobo Hu
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Patent number: 12062711Abstract: A manufacturing method of a display substrate, a display substrate, and a display device. The manufacturing method includes: forming an active layer; forming a gate insulation film layer, a gate film layer and a photoresist film layer; exposing the photoresist film layer to a light and developing the exposed photoresist film layer until the developed photoresist film layer has a thickness of 1.8-2.2 ?m and a slope angle not less than 70°; over-etching the gate film layer to form a gate electrode, an orthographic projection of the gate electrode being located within a region of an orthographic projection of the developed photoresist film layer; over-etching the gate insulation film layer by a gaseous corrosion method to form a gate insulation layer; peeling off the photoresist film layer remaining on a surface of the gate electrode; and performing a conductive treatment to the active layer.Type: GrantFiled: September 30, 2021Date of Patent: August 13, 2024Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Jun Liu, Luke Ding, Jingang Fang, Bin Zhou, Leilei Cheng, Wei Li
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Patent number: 12050398Abstract: A semiconductor device includes a semiconductor substrate having a semiconductor substrate having a main surface including a first portion; a redistribution layer provided over the first portion of the main surface of the semiconductor substrate; an insulating layer covering the first portion of the main surface of the semiconductor substrate and the redistribution layer; and a first polyimide film covering the insulating layer; wherein the polyimide film has a substantially flat upper surface.Type: GrantFiled: May 19, 2020Date of Patent: July 30, 2024Assignee: MICRON TECHNOLOGY, INC.Inventors: Hidenori Yamaguchi, Keizo Kawakita, Shigeru Sugioka
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Patent number: 12051374Abstract: A display panel includes a first metal layer; a first insulating layer covering the first metal layer; a semiconductor layer disposed on the first insulating layer; a second insulating layer disposed on the first insulating layer to cover the semiconductor layer; and a second metal layer disposed on the second insulating layer, wherein the first metal layer comprises a bottom gate electrode of a driving element, wherein the second metal layer comprises a top gate electrode of the driving element connected to the bottom gate electrode through a first contact hole penetrating the second insulating layer and the first insulating layer, wherein the semiconductor layer comprises a semiconductor channel of the driving element overlapping with the top gate electrode and the bottom gate electrode.Type: GrantFiled: November 10, 2021Date of Patent: July 30, 2024Assignee: LG DISPLAY CO., LTD.Inventors: Seong Hwan Hwang, Byeong Uk Gang, Mun Chae Yoon
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Patent number: 12051726Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes an oxide semiconductor, a first insulator in contact with the oxide semiconductor, and a second insulator in contact with the first insulator. The first insulator includes excess oxygen. The second insulator has a function of trapping or fixing hydrogen. Hydrogen in the oxide semiconductor is bonded to the excess oxygen. The hydrogen bonded to the excess oxygen passes through the first insulator and is trapped or fixed in the second insulator. The excess oxygen bonded to the hydrogen remains in the first insulator as the excess oxygen.Type: GrantFiled: December 14, 2021Date of Patent: July 30, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Daisuke Yamaguchi, Shinobu Kawaguchi, Yoshihiro Komatsu, Toshikazu Ohno, Yasumasa Yamane, Tomosato Kanagawa
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Patent number: 12034054Abstract: A method includes forming a gate dielectric layer and a dummy gate layer; forming a mask over the dummy gate layer; patterning the gate dielectric layer and the dummy gate layer to form a dummy gate structure, the dummy gate structure including a remaining portion of the gate dielectric layer and a remaining portion of the dummy gate layer; epitaxially growing a first spacer layer on the dummy gate structure and the substrate, in which the first spacer layer has a higher growth rate on the exposed surfaces of the dummy gate structure and the substrate than on exposed surfaces of the mask; doping the first spacer layer to form a doped spacer layer having a different lattice constant than the substrate; depositing a second spacer layer over the doped spacer layer; and etching the second spacer layer and the doped spacer layer to form a gate spacer.Type: GrantFiled: July 8, 2021Date of Patent: July 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Chun-Ting Chou
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Patent number: 12025897Abstract: According to an aspect of the present disclosure, a liquid crystal display device includes a lower substrate including a black matrix and a color filter; an upper substrate disposed to be opposite to the lower substrate; a thin film transistor which on the upper substrate to be opposite to the color filter, and including a gate electrode, an active layer, a source electrode, and a drain electrode; at least one insulting layer disposed on the thin film transistor; a pixel electrode disposed on the insulating layer and electrically connected to the drain electrode; and a common electrode spaced apart from the pixel electrode, and the gate electrode includes a first gate conductive layer including a transparent conductive material, a second gate conductive layer including a first transition metal oxide and a second transition metal oxide, and a third gate conductive layer formed of an opaque conductive layer.Type: GrantFiled: October 28, 2022Date of Patent: July 2, 2024Assignee: LG DISPLAY CO., LTD.Inventors: ChangEun Kim, JoongHa Lee, WonGyu Jeong, Jinuk Lee
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Patent number: 12027527Abstract: A display device includes a base substrate; an oxide semiconductor layer disposed on the base substrate; a first gate insulating layer disposed on a first channel region of the oxide semiconductor layer and that overlaps the first channel region thereof; a first upper gate electrode disposed on the first gate insulating layer; and an upper interlayer insulating layer disposed on the first upper gate electrode, the first upper gate electrode, and the oxide semiconductor layer, wherein the upper interlayer insulating layer includes a first upper interlayer insulating layer, a second upper interlayer insulating layer, and a third upper interlayer insulating layer, the first upper interlayer insulating layer includes silicon oxide, each of the second and third upper interlayer insulating layers include silicon nitride, and a hydrogen concentration in the second upper interlayer insulating layer is less than a hydrogen concentration in the third upper interlayer insulating layer.Type: GrantFiled: October 27, 2022Date of Patent: July 2, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Jung Yub Seo, Tetsuhiro Tanaka, Hee Won Yoon, Shin Beom Choi
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Patent number: 11996415Abstract: A display panel and a method of manufacturing the display panel are provided. The display panel includes a substrate and a transistor layer. The transistor array layer includes a first metal layer disposed above the substrate. The first metal layer includes a gate, a second metal layer disposed above the first metal layer. The second metal layer includes a source, a drain, and a metal trace, and at least one repair part disposed on both sides of the metal trace. The repair part and the metal trace are configured to form a signal trace.Type: GrantFiled: July 21, 2020Date of Patent: May 28, 2024Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.Inventors: Zhihao Cao, Wei Tang, Jianlong Huang
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Patent number: 11990551Abstract: The stability of steps of processing a wiring formed using copper or the like is increased. The concentration of impurities in a semiconductor film is reduced. Electrical characteristics of a semiconductor device are improved. A semiconductor device includes a semiconductor film, a pair of first protective films in contact with the semiconductor film, a pair of conductive films containing copper or the like in contact with the pair of first protective films, a pair of second protective films in contact with the pair of conductive films on the side opposite the pair of first protective films, a gate insulating film in contact with the semiconductor film, and a gate electrode overlapping with the semiconductor film with the gate insulating film therebetween. In a cross section, side surfaces of the pair of second protective films are located on the outer side of side surfaces of the pair of conductive films.Type: GrantFiled: February 23, 2021Date of Patent: May 21, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Masami Jintyou, Yasutaka Nakazawa, Yukinori Shima
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Patent number: 11971751Abstract: A method of manufacturing a display device, including: providing an object to be processed; forming a linear portion of the object to be processed by performing a first laser processing for the object to be processed; and forming a curved portion of the object to be processed by performing a second laser processing different from the first laser processing for the object to be processed. A laser processing apparatus, is also provided, including: an irradiation unit applying a laser onto an object to be processed; and a controller controlling an operation of the irradiation unit. The controller controls the irradiation unit to form a linear portion of the object to be processed by applying the laser onto the object according to a first condition and forming a curved portion of the object by applying the laser onto the object according to a second condition different from the first condition.Type: GrantFiled: December 17, 2020Date of Patent: April 30, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Geun Woo Yug, Ku Hyun Kang
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Patent number: 11968901Abstract: The disclosure provides a displaying substrate, a manufacturing method thereof, and a display panel, and relates to the technical field of display. The displaying substrate comprises a first supporting base (1), plurality of vibrating element modules (2), and a display module (3). The display module (3) comprises display units (31), connecting units (32) and hollowed-out units (33). Each connecting unit (32) is located between two adjacent display units (31). Each hollowed-out unit (33) is located between two adjacent display units (31) except an area where the corresponding connecting unit (32) is located. The hollowed-out units (33) are provided with cavities (40) corresponding to the vibrating element modules (2). Orthographic projections of the hollowed-out units (33) on a reference plane cover orthographic projections of the vibrating element modules (2) on the reference plane. The vibrating element modules (2) and the cavities (40) form a transducer.Type: GrantFiled: February 23, 2021Date of Patent: April 23, 2024Assignee: BOE Technology Group Co., Ltd.Inventors: Zhao Cui, Feng Zhang, Zhijun Lv, Wenqu Liu, Liwen Dong, Xiaoxin Song, Detian Meng, Libo Wang, Dongfei Hou, Qi Yao
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Patent number: 11965236Abstract: Methods for forming a nickel silicide material on a substrate are disclosed. The methods include depositing a first nickel silicide seed layer atop a substrate at a temperature of about 15° C. to about 27° C., annealing the first nickel silicide seed layer at a temperature of 400° C. or less such as over 350° C.; and depositing a second nickel silicide layer atop the first nickel silicide seed layer at a temperature of about 15° C. to about 27° C. to form the nickel silicide material.Type: GrantFiled: July 15, 2019Date of Patent: April 23, 2024Assignee: APPLIED MATERIALS, INC.Inventors: Minrui Yu, He Ren, Mehul Naik
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Patent number: 11955537Abstract: A semiconductor device includes a substrate having an insulating surface; a light-transmitting first electrode provided over the substrate; a light-transmitting second electrode provided over the substrate; a light-transmitting semiconductor layer provided so as to be electrically connected to the first electrode and the second electrode; a first wiring electrically connected to the first electrode; an insulating layer provided so as to cover at least the semiconductor layer; a light-transmitting third electrode provided over the insulating layer in a region overlapping with the semiconductor layer; and a second wiring electrically connected to the third electrode.Type: GrantFiled: August 26, 2022Date of Patent: April 9, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Hajime Kimura
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Patent number: 11955559Abstract: Provided are a thin film transistor, a display device, and a thin film transistor manufacturing method, in which variation in characteristics is small. The present invention is provided with: a gate electrode formed on a substrate; a gate insulation film formed so as to cover the gate electrode; a semiconductor layer which is formed on the upper side of the gate insulation film and which includes a polysilicon layer disposed, in a plan view, inside a region defined by the gate electrode; an etching stopper layer disposed on the upper side of the polysilicon layer; and a source electrode and a drain electrode provided on the semiconductor layer so as to be separated from each other, wherein the polysilicon layer has first and second regions which are not covered with the etching stopper layer, and a part of the source electrode exists above the first region and a part of the drain electrode exists above the second region.Type: GrantFiled: August 27, 2021Date of Patent: April 9, 2024Assignee: SAKAI DISPLAY PRODUCTS CORPORATIONInventors: Yoshiaki Matsushima, Shigeru Ishida, Ryohei Takakura, Satoru Utsugi, Nobutake Nodera, Takao Matsumoto, Satoshi Michinaka
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Patent number: 11955492Abstract: According to one embodiment, a display device includes a display panel including a display area for displaying an image, and the display panel includes an insulating substrate, a first electrode, a first organic insulating layer, an inorganic insulating layer, a pixel electrode, a second organic insulating layer, and a pad portion. The inorganic insulating layer includes a first opening for electrically connecting the first electrode to the pixel electrode. The second organic insulating layer includes a second opening for electrically connecting the pixel electrode to the pad portion. The pixel electrode is formed of a transparent conductive material.Type: GrantFiled: September 17, 2021Date of Patent: April 9, 2024Assignee: Japan Display Inc.Inventors: Yoshinori Aoki, Yasuhiro Kanaya, Akihiro Ogawa
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Patent number: 11957028Abstract: A display panel is provided including a substrate including a display area comprising first pixels and a sensor area including second pixels and a transmission portion. A display element layer is disposed on the substrate, the display element layer comprising the first pixels electrically connected to a first thin film transistor and the second pixels electrically connected to a second thin film transistor. A conductive layer is disposed between the second thin film transistor and the substrate, the conductive layer having two or more steps at an edge thereof.Type: GrantFiled: February 18, 2022Date of Patent: April 9, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Injun Bae, Hyunwook Choi, Donghwi Kim, Chulho Kim, Woori Seo, Jin Jeon
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Patent number: 11948784Abstract: Apparatus and methods for improving film uniformity in a physical vapor deposition (PVD) process are provided herein. In some embodiments, a PVD chamber includes a pedestal disposed within a processing region of the PVD chamber, the pedestal having an upper surface configured to support a substrate thereon, a first motor coupled to the pedestal, a lid assembly comprising a first target, a first magnetron disposed over a portion of the first target, and in a region of the lid assembly that is maintained at atmospheric pressure, a first actuator configured to translate the first magnetron in a first direction, a second actuator configured to translate the first magnetron in a second direction, and a system controller that is configured to cause the first magnetron to translate along at least a portion of a first path by causing the first actuator and second actuator to simultaneously translate the first magnetron.Type: GrantFiled: October 21, 2021Date of Patent: April 2, 2024Assignee: APPLIED MATERIALS, INC.Inventors: Harish Penmethsa, Hong S. Yang, Suresh Palanisamy
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Patent number: 11942170Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.Type: GrantFiled: May 20, 2022Date of Patent: March 26, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Seiko Amano, Kouhei Toyotaka, Hiroyuki Miyake, Aya Miyazaki, Hideaki Shishido, Koji Kusunoki
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Patent number: 11915651Abstract: An electroluminescent display including pixels arranged in a matrix is disclosed. Each pixel includes a pixel circuit configured to sample a threshold voltage of a driving element for driving a light emitting element and compensate for a data voltage. The pixel circuit includes a first switch element connected to a data voltage path supplied with the data voltage, a second switch element connected to a reference voltage path supplied with a predetermined reference voltage, a third switch element connected between a gate of the driving element and the first and second switch elements, a fourth switch element connected to an initialization voltage path supplied with a predetermined initialization voltage, and a fifth switch element connected to a power path supplied with a predetermined pixel driving voltage higher than the reference voltage and the initialization voltage.Type: GrantFiled: June 11, 2018Date of Patent: February 27, 2024Assignee: LG Display Co., Ltd.Inventors: Sungsoo Shin, Sohee Choi, Yewon Hong
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Patent number: 11894479Abstract: The present invention provides a photosensitive element, and a preparation method and a display device thereof. The photosensitive element includes a substrate; a first electrode arranged on the substrate; an N-type doped silicon layer arranged on the first electrode; an undoped silicon layer arranged on the N-type doped silicon layer; a molybdenum oxide layer arranged on the undoped silicon layer; an insulating layer arranged on the molybdenum oxide layer and the substrate, wherein a first opening is arranged on the insulating layer to expose the molybdenum oxide layer; and a second electrode arranged on the insulating layer and the molybdenum oxide layer, wherein the second electrode contacts the molybdenum oxide layer through the first opening.Type: GrantFiled: December 31, 2020Date of Patent: February 6, 2024Inventor: Guangshuo Cai
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Patent number: 11877471Abstract: A display apparatus includes a first substrate, a second substrate, and a transistor. The first transistor includes a polymer resin. The second substrate is arranged between the first substrate and the transistor and includes a glass material. A liquidus temperature of the glass material is less than 1000° C. The transistor overlaps at least one of the first substrate and the second substrate and includes a semiconductor layer.Type: GrantFiled: September 15, 2021Date of Patent: January 16, 2024Assignee: Samsung Display Co., Ltd.Inventor: Hun Kim
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Patent number: 11862668Abstract: Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.Type: GrantFiled: July 2, 2021Date of Patent: January 2, 2024Assignee: Micron Technology, Inc.Inventors: Fatma Arzum Simsek-Ege, Masihhur R. Laskar, Nicholas R. Tapias, Darwin Franseda Fan, Manuj Nahar
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Patent number: 11843046Abstract: A high electron mobility transistor (HEMT) includes a buffer layer, a carrier transit layer, a carrier supply layer, a gate, a source electrode and a drain electrode. The buffer layer is on a substrate. The carrier transit layer is on the buffer layer. The carrier supply layer is on the carrier transit layer. The gate is on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the gate, wherein each of the source electrode and the drain electrode includes a conductive layer and a conductive oxide layer stacked from bottom to top.Type: GrantFiled: January 11, 2021Date of Patent: December 12, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Huai-Tzu Chiang, Sheng-Hao Lin, Kuan-Hung Liu
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Patent number: 11844206Abstract: The present invention provides a highly integrated memory cell and a semiconductor device including the same. According to an embodiment of the present invention, the semiconductor device comprises: a plurality of active layers vertically stacked over a substrate; a plurality of bit lines connected to first ends of the active layers, respectively, and extended parallel to the substrate; line-shape air gaps disposed between the bit lines; a plurality of capacitors connected to second ends of the active layers, respectively; and a word line and a back gate facing each other with each of the active layers interposed therebetween, wherein the word line and the back gate are vertically oriented from the substrate.Type: GrantFiled: August 17, 2021Date of Patent: December 12, 2023Assignee: SK hynix Inc.Inventor: Seung Hwan Kim
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Patent number: 11817460Abstract: A thin film transistor includes a gate, a gate insulating layer, an active layer, an ionized amorphous silicon layer, a source and a drain. The gate insulating layer covers the gate. The active layer is disposed on a side of the gate insulating layer away from the gate. The ionized amorphous silicon layer is disposed on a side of the active layer away from the gate, and the ionized amorphous silicon layer is in contact with the gate insulating layer. The source and the drain are disposed on a side of the ionized amorphous silicon layer away from the gate insulating layer, and the source and the drain are coupled to the active layer through the ionized amorphous silicon layer.Type: GrantFiled: March 27, 2020Date of Patent: November 14, 2023Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Chao Luo, Feng Guan, Zhi Wang, Jianhua Du, Yang Lv, Zhaohui Qiang, Chao Li
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Patent number: 11798850Abstract: A semiconductor device including a contact structure is provided. The semiconductor device includes an isolation region defining a lower active region. First and second source/drain regions and first and second gate electrodes are on the lower active region. The first and second source/drain regions are adjacent to each other. First and second gate capping patterns are on the first and second gate electrodes, respectively. First and second contact structures are on the first and second source/drain regions, respectively. A lower insulating pattern is between the first and second source/drain regions. An upper insulating pattern is between the first and second contact structures. Silicon oxide has etching selectivity with respect to an insulating material which the upper insulating pattern, the first gate capping pattern, and the second gate capping pattern are formed of.Type: GrantFiled: August 10, 2021Date of Patent: October 24, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hwi Chan Jun, Chang Hwa Kim, Dae Won Ha
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Patent number: 11764308Abstract: A body layer formed of a semiconductor layer, the body layer comprising, a first region, a second region, and a channel region positioned therebetween; a channel stopper formed on the channel region; source and drain electrodes electrically connected to the first and second regions via first and second contact layers respectively are provided. Each of the first and second contact layers comprises an impurities-containing first amorphous silicon layer; a thickness of each of the first and second regions is less than a thickness of the channel region; and the first and second regions comprise a second amorphous silicon layer containing impurities in a concentration being less than a concentration of impurities contained in the first amorphous silicon layer. This makes it possible to suppress a photoexcited current and improve the aperture ratio in a case that a display apparatus is configured.Type: GrantFiled: February 9, 2021Date of Patent: September 19, 2023Assignee: SAKAI DISPLAY PRODUCTS CORPORATIONInventors: Hiroyuki Ohta, Shogo Sako, Hisayuki Katoh
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Patent number: 11764057Abstract: A method of forming a structure having a coating layer includes the following steps: providing a substrate; coating a fluid on the surface of the substrate, where the fluid includes a carrier and a plurality of silicon-containing nanoparticles; and performing a heating process to remove the carrier and convert the silicon-containing nanoparticles into a silicon-containing layer, a silicide layer, or a stack layer including the silicide layer and the silicon-containing layer.Type: GrantFiled: May 24, 2021Date of Patent: September 19, 2023Assignee: CHE Inc.Inventors: Chuan-Pu Liu, Yin-Wei Cheng, Shih-An Wang, Bo-Liang Peng, Chun-Hung Chen, Jun-Han Huang, Yi-Chang Li
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Patent number: 11744120Abstract: A manufacturing method of a display device includes: forming a transistor on a substrate; forming an organic insulating layer on the transistor; and performing a plasma treatment on the organic insulating layer. The organic insulating layer includes an acryl-based polymer, and the plasma treatment is performed by using helium gas or argon gas.Type: GrantFiled: March 25, 2021Date of Patent: August 29, 2023Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Hyun Min Cho, Tae Sung Kim, Yun Jong Yeo, Ji Youn Nam, Hee Min Yoo
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Patent number: 11737276Abstract: A method of manufacturing a semiconductor device according to the present disclosure includes forming a stack by alternately stacking insulating films and sacrificial films on a substrate; forming, in the stack, a through-hole extending in a thickness direction of the stack; forming a block insulating film, a charge trapping film, a tunnel insulating film, and a channel film on an inner surface of the through-hole in this order; forming, in the stack, a slit extending in the thickness direction of the stack separately from the through-hole; removing the sacrificial films through the slit so as to form a recess between adjacent insulating films; forming a first metal oxide film on an inner surface of the recess; forming, on the first metal oxide film, a second metal oxide film having a crystallization temperature lower than that of the first metal oxide film; and filling the recess with an electrode layer.Type: GrantFiled: May 27, 2021Date of Patent: August 22, 2023Assignee: Tokyo Electron LimitedInventors: Sara Otsuki, Genji Nakamura, Muneyuki Otani, Kazuya Takahashi