Abstract: A thin film transistor having a channel region including a nanoconductor layer. The nanoconductor layer can be a dispersed monolayer of nanotubes or nanowires formed of carbon. The thin film transistor generally includes a gate terminal insulated by a dielectric layer. The nanoconductor layer is placed on the dielectric layer and a layer of semiconductor material is developed over the nanoconductor layer to form the channel region of the thin film transistor. A drain terminal and a source terminal are then formed on the semiconductor layer. At low field effect levels, the operation of the thin film transistor is dominated by the semiconductor layer, which provides good leakage current performance. At high field effect levels, the charge transfer characteristics of the channel region are enhanced by the nanoconductor layer such that the effective mobility of the thin film transistor is enhanced.

Abstract: A thin film transistor substrate including a thin film transistor having a drain electrode with an electrode portion, which overlaps with a semiconductor layer, and an extended portion, which extends from the electrode portion and has a portion overlapping with a storage electrode or storage electrode line. A passivation layer is arranged on the drain electrode, and it has a contact hole that partially exposes the extended portion of the drain electrode without exposing a step in the extended portion caused by the storage electrode or storage electrode line. A pixel electrode is arranged on the passivation layer and is electrically connected with the extended portion of the drain electrode through the contact hole.

Abstract: An object is to provide a method for manufacturing a thin film transistor and a display device with reduced number of masks, in which adverse effects of optical current are suppressed. A manufacturing method comprises forming a stack including, from bottom to top, a light-blocking film, a base film, a first conductive film, a first insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film; performing first etching on the whole thickness of the stack using a first resist mask formed over it; forming a gate electrode layer by side etching the first conductive film in a second etching; forming a second resist mask over the stack; and performing third etching down to the semiconductor film, and partially etching it, using the second resist mask to form a source and drain electrode layer, a source and drain region, and a semiconductor layer.

Abstract: A method and system for setting the direction of pinned layers in a magnetic junction are described. In one aspect, a magnetic field greater than the coercivity of the layers in a pinned layer but less than the coupling field between the layers is applied. In another aspect the pinned layers are switched from an anti-dual state to a dual state using a spin transfer torque current. In another aspect, a magnetic junction having a partial perpendicular anisotropy (PPMA) layer in the pinned layer is provided. In some aspects, the PPMA layer is part of a synthetic antiferromagnetic structure. In some embodiments, a decoupling layer is provided between the PPMA layer and another ferromagnetic layer in the pinned layer.

Abstract: A method of manufacturing an organic thin film transistor, comprising: providing a substrate comprising source and drain electrodes defining a channel region; subjecting at least the channel region to a cleaning treatment step; and depositing organic semiconductive material from solution into the channel region by inkjet printing.

Abstract: A semiconductor device of the present invention includes: a lower electrode (110); a contact layer (130) including a first contact layer (132), a second contact layer (134) and a third contact layer (136) overlapping with a semiconductor layer (120); and an upper electrode (140) including a first upper electrode (142), a second upper electrode (144) and a third upper electrode (146). The second contact layer (134) includes a first region (134a), and a second region (134b) separate from the first region (134a), and the second upper electrode (144) is directly in contact with the semiconductor layer (120) in a region between the first region (134a) and the second region (134b) of the second contact layer (134).

Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks. In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by wet etching in which an etchant is used, and a second etching step is performed by dry etching in which an etching gas is used.

Abstract: A method for manufacturing a thin film transistor is provided. In the method, a gate electrode is formed on a substrate. A crystalline gate insulating layer is formed on an entire surface of the substrate having the gate electrode formed thereon. A microcrystalline silicon layer and a doped amorphous silicon layer are sequentially formed on the crystalline gate insulating layer. A metal layer is deposited on the substrate including the crystalline gate insulating layer, the microcrystalline silicon layer and the doped amorphous silicon layer. Source and drain electrodes, an ohmic contact layer and an active layer are formed by etching predetermined portions of the metal layer and the doped amorphous silicon layer to expose a predetermined portion of the microcrystalline silicon layer.

Abstract: A thin film transistor (TFT), an array substrate including the TFT, and methods of manufacturing the TFT and the array substrate. The TFT includes an active layer, and a metal member that corresponds to a portion of each of the source region and the drain region of the active layer, and is arranged on the active layer, a portion of the metal member contacts the source and drain regions of the active layer and the source and drain electrodes, and portions of the active layer that corresponds to portions below the metal member of the active layer are not doped.

Abstract: A display apparatus including: a plurality of thin film transistors; and an interconnect region, wherein each of the thin film transistors includes a first protective film held in contact with a channel layer and disposed remotely from a gate electrode, a second protective film disposed on the first protective film, and a source and drain electrode assembly including a pair of electrodes held in contact with the channel layer, and the interconnect region includes a first interconnect, a second interconnect disposed in alignment with the first interconnect, and an insulating layer interposed between the first interconnect and the second interconnect and having a stacked structure including a first insulating film joined to the gate insulating film and a second insulating film joined to the second protective film.

Abstract: A thin film transistor (TFT) includes a gate electrode, a gate insulating layer, a first protective pattern, a second protective pattern, a source electrode, a drain electrode, a semiconductor channel layer, and a passivation layer. The first protective pattern and the second protective pattern are disposed on the gate insulating layer above the gate electrode. The source electrode is disposed on the gate insulating layer and the first protective pattern. The drain electrode is disposed on the gate insulating layer and the second protective pattern. The semiconductor channel layer is disposed on the gate insulating layer, the source electrode, and the drain electrode. In an extending direction from the source electrode to the drain electrode, a length of the first protective pattern is shorter than that of the source electrode, and a length of the second protective pattern is shorter than that of the drain electrode.

Abstract: A thin-film transistor array includes first and second bottom-gate transistors, a passivation film, a conductive oxide film below the passivation film, and a relay electrode between a first conductive material in a same layer as a first electrode of the first transistor and a second conductive material in an electroluminescence layer. A first line is in a layer lower than the passivation film and a second line is above the passivation film. A terminal to which an external signal is input is provided in a periphery of the substrate in the same layer as the first electrode. The conductive oxide film covers an upper surface of the terminal and is between the relay electrode and the first conductive material. The relay electrode is formed in a same layer and comprises a same material as the second line.

Abstract: A method of forming a semiconductor structure on a substrate is provided. The method may include preparing a continuous active layer on a region of the substrate and depositing a first raised epitaxial layer on a first region of the continuous active layer. A second raised epitaxial layer is also deposited on a second region of the continuous active layer such that the first raised epitaxial layer is in close proximity to the second raised epitaxial layer. A mask may be used to etch a trench structure into the continuous active layer at both the first and the second raised epitaxial layer, whereby the etched trench structure is filled with isolation material for electrically isolating the first raised epitaxial layer from the second raised epitaxial layer.

Abstract: A liquid crystal display device is provided with high productivity at low cost by reducing manufacturing steps of the liquid crystal display device. A liquid crystal display device with less power consumption and high reliability is provided. Etching of a semiconductor layer and formation of a contact hole that connects a pixel electrode and a drain electrode are performed by one photolithography process and one etching step, whereby the number of photolithography processes is reduced. A liquid crystal display device can be provided with high productivity at low cost by reducing the number of photolithography processes. Further, an oxide semiconductor is used for the semiconductor layer, whereby a liquid crystal display device with less power consumption and high reliability can be provided.

Abstract: A manufacturing method of the array substrate includes the steps: A. A first mask manufacturing process is adopted to from scan lines and thin film transistor (TFT) gates on a surface of a substrate. B. A second mask manufacturing process is adopted to form scan lines and data lines of the array substrate, a source electrode and a drain electrode of TFT and a conducting channel positioned between the source electrode and the drain electrode. C. A photoresistor formed in the second mask manufacturing process is incinerated, and then, an a-Si film is paved on the surface of the array substrate. D. The photoresistor is stripped to form an undoped active layer. E. A third mask manufacturing process is adopted to form a transparent conducting layer on the surface of the drain electrode of the TFT. Only three mask manufacturing process in the present disclosure are needed to manufacture the entire array substrate.

Abstract: It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity. In a method for manufacturing a semiconductor device which includes a thin film transistor where a semiconductor layer including a channel formation region using an oxide semiconductor layer, a source region, and a drain region are formed using an oxide semiconductor layer, heat treatment for reducing impurities such as moisture (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor layer.

Abstract: A thin film transistor array substrate is disclosed. The thin film transistor array substrate includes: gate lines and data lines formed to cross each other in the center of a gate insulation film on a substrate and to define pixel regions; a thin film transistor formed at each intersection of the gate and data lines; a passivation film formed on the thin film transistors; a pixel electrode formed on each of the pixel regions and connected to the thin film transistor through the passivation film; a gate pad connected to each of the gate lines through a gate linker; and a data pad connected to each of the data lines through a data linker. The data pad is formed of a gate pattern, and the data line is formed of a data pattern. The data linker is configured to connect the data pad formed of the gate pattern with the data line formed of the data pattern using a connection wiring.

Abstract: A thin-film transistor substrate includes a gate line, and a gate electrode connected to the gate line, on a base substrate; an insulating layer on the gate electrode, the insulating layer including a first part and a second part, the first part having a hydrophobic property and the second part having a hydrophilic property; a data line extended in a different direction from the gate line, and a source electrode connected to the data line and on the second part of the insulating layer; a drain electrode on the second part of the insulating layer, the drain electrode spaced apart from the source electrode; a semi-conductor pattern overlapping the source electrode, the drain electrode and a gap between the spaced apart source and drain electrodes, where the semi-conductor pattern exposes the first part of the insulating layer; and a pixel electrode in contact with the drain electrode.

Abstract: Disclosed is a method for manufacturing an array substrate of an FFS type TFT-LCD, comprising the steps of: forming a first transparent conductive film, a first metal film and an impurity-doped semiconductor film on a transparent substrate sequentially, and then patterning the stack of the films to form patterns including source electrodes, drain electrodes, data lines and pixel electrodes; forming a semiconductor film and patterning it to form a pattern of the impurity-doped semiconductor layer and a pattern of the semiconductor layer including TFT channels; forming an insulating film and a second metal film, and patterning the stack of the films to form patterns including connection holes of the data lines in a PAD region, gate lines, gate electrodes and common electrode lines; forming a second transparent conductive film, and patterning it to form patterns including the common electrode.

Abstract: Provided are thin film transistor, a method of fabricating the same, a flat panel display device including the same, and a method of fabricating the flat panel display device, that are capable of applying an electric field to a gate line to form a channel region of a semiconductor layer of a thin film transistor using a polysilicon layer crystallized by a high temperature heat generated by Joule heating of a conductive layer. As a result, a process can be simplified using a gate line included in the thin film transistor as the conductive layer, and the channel region of the semiconductor layer can be formed of polysilicon having a uniform degree of crystallinity. The thin film transistor includes a straight gate line disposed in one direction, a semiconductor layer crossing the gate line, and source and drain electrodes connected to source and drain regions of the semiconductor layer.

Abstract: An active device array substrate is provided. First, a substrate having a display area and a sensing area is provided. Then, a first patterned conductor layer is disposed on the display area of the substrate. A gate insulator is disposed on the substrate. A patterned semiconductor layer, a second patterned conductor layer and a patterned photosensitive dielectric layer are disposed on the gate insulator, wherein the second patterned conductor layer includes a source electrode, a drain electrode and a lower electrode, the patterned photosensitive dielectric layer covering the second patterned conductor layer includes an interface protection layer disposed on the source electrode and the drain electrode and a photo-sensing layer disposed on the lower electrode. A passivation layer is then disposed on the substrate. After that, a third patterned conductor layer including a pixel electrode and an upper electrode is disposed on the passivation layer.

Abstract: An approach for patterning and etching without a mask is provided in a manufacturing a thin-film transistor, a gate electrode, a gate insulating layer, a semiconductor layer, an ohmic contact layer and source metal layer of a substrate. A first photoresist pattern including a first photo pattern and a second photo pattern is formed using a digital exposure device by generating a plurality of spot beams, the first photo pattern is formed to a first region of the base substrate and has a first thickness, and the second photo pattern is formed to a second region adjacent to the first region, and has a second thickness and a width in a range of about 50% to about 60% of a diameter of the spot beam. The source metal layer is patterned to form a source electrode and a drain electrode, and the source electrode and the drain electrode are spaced apart from each other in the first region of an active pattern.

Abstract: A thin film transistor (TFT) array substrate and a method for fabricating the thin film transistor (TFT) array substrate is disclosed, wherein a passivation layer is directly subjected to exposing and patterning processes without using any photoresist, thereby simplifying the fabrication process and ensuring reduced preparation costs.

Abstract: Etching of a semiconductor layer including a part over a gate wiring and formation of a contact hole for connection between a pixel electrode and a drain electrode are performed by one-time photolithography step and one-time etching step; thus, the number of photolithography steps is reduced. The exposed part of the gate wiring is covered by an insulating layer, and this insulating layer also functions as a spacer for maintaining a space for a liquid crystal layer. By the reduction in the number of photolithography steps, a liquid crystal display device can be provided at lower cost and higher productivity. Using an oxide semiconductor for the semiconductor layer can realize a liquid crystal display device with low power consumption and high reliability.

Abstract: A method of manufacturing a thin film transistor includes: forming a gate electrode on a substrate; forming a gate insulating layer on the gate electrode; forming an organic semiconductor layer on the gate insulating layer; forming an organic semiconductor pattern by selectively removing part of the organic semiconductor layer by means of a laser ablation method; and forming source and drain electrodes on the organic semiconductor pattern.

Abstract: In a method for manufacturing a transistor including an oxide semiconductor layer, a gate electrode is formed and then an aluminum oxide film, a silicon oxide film, and the oxide semiconductor film are successively formed in an in-line apparatus without being exposed to the air and are subjected to heating and oxygen adding treatment in the in-line apparatus. Then, the transistor is covered with another aluminum oxide film and is subjected to heat treatment, so that the oxide semiconductor film from which impurities including hydrogen atoms are removed and including a region containing oxygen at an amount exceeding that in the stoichiometric composition ratio. The transistor including the oxide semiconductor film is a transistor having high reliability in which the amount of change in threshold voltage of the transistor by the bias-temperature stress (BT test) can be reduced.

Abstract: A display device including an inverter circuit and a switch is provided. The inverter circuit includes a first thin film transistor and a second thin film transistor which have the same conductivity type. The first thin film transistor and the second thin film transistor each include: a gate insulating layer in contact with a gate electrode; a microcrystalline semiconductor layer in contact with the gate insulating layer; a mixed layer in contact with the microcrystalline semiconductor layer; a layer which includes an amorphous semiconductor and is in contact with the mixed layer; and a wiring. A conical or pyramidal microcrystalline semiconductor region and an amorphous semiconductor region filling a space except the conical or pyramidal microcrystalline semiconductor region are included in the mixed layer.

Abstract: A method of fabricating a thin-film transistor (TFT) substrate includes forming a gate electrode on a substrate; forming an insulating film on the gate electrode; forming an amorphous semiconductor pattern on the insulating film; and forming a source electrode separated from a drain electrode on the amorphous semiconductor pattern; forming a light-concentrating layer, which includes a protrusion, on the amorphous semiconductor pattern, the source electrode, and the drain electrode; and crystallizing at least part of the amorphous semiconductor pattern by irradiating light to the protrusion of the light-concentrating layer.

Abstract: A method for manufacturing a flexible semiconductor device includes (i) forming an insulating film on the upper surface of metal foil, (ii) forming an extraction electrode pattern on the upper surface of the metal foil, (iii) forming a semiconductor layer on the insulating film such that the semiconductor layer is in contact with the extraction electrode pattern, (iv) forming a sealing resin layer on the upper surface of the metal foil such that the sealing resin layer covers the semiconductor layer and the extraction electrode pattern, and (v) forming electrodes by etching the metal foil, the metal foil being used as a support for the insulating film, the extraction electrode pattern, the semiconductor layer, and the sealing resin layer formed in (i) to (iv) and used as a constituent material for the electrodes in (v). The metal foil need not be stripped, and a high-temperature process can be used.

Abstract: The invention provides a display device and a method for manufacturing thereof by increasing a material efficiently as well as simplifying steps. Also, the invention provides a technique for forming a pattern such as a wiring, that is used for forming a display device, to have a predetermined shape with an excellent controllability. The method for manufacturing a display device includes the steps of: forming a lyophobic region; selectively irradiating laser beam in the lyophobic region to form a lyophilic region; selectively discharging a composition, that contains a conductive material, in the lyophilic region to form a gate electrode layer; forming a gate insulating layer and a semiconductor layer over the gate electrode layer; discharging a composition containing a conductive material over the semiconductor layer to form a source electrode layer and a drain electrode layer; and forming a pixel electrode layer on the source or drain electrode layer.

Abstract: Provided are a display device, a thin-film transistor (TFT) substrate, and a method of fabricating the TFT substrate. The method includes: forming a gate electrode on a pixel region of a substrate; forming a gate insulating film on the gate electrode; forming a semiconductor layer on the gate insulating film to overlap the gate electrode; forming a source electrode and a drain electrode to overlap the semiconductor layer and thus form a channel region; and forming a data insulating film on the source electrode and the drain electrode and patterning the data insulating film such that part of a contact hole formed in the data insulating film overlaps the channel region.

Abstract: The present invention provides a thin film transistor array panel including an insulating substrate, a gate line formed on the insulating substrate, a gate insulating layer formed on the gate line, a drain electrode and a data line having a source electrode formed on the gate insulating layer wherein the drain electrode faces the source electrode with a gap therebetween, and a pixel electrode connected to the drain electrode. At least one of the gate line, the data line, and the drain electrode includes a first conductive layer made of a conductive oxide and a second conductive layer of Ag that is deposited adjacent to the first conductive layer.

Abstract: It is an object of the present invention to provide a thin film transistor in which an oxide semiconductor film containing indium (In), gallium (Ga), and zinc (Zn) is used and contact resistance of a source or a drain electrode layer is reduced, and a manufacturing method thereof. An IGZO layer is provided over the source electrode layer and the drain electrode layer, and source and drain regions having lower oxygen concentration than the IGZO semiconductor layer are intentionally provided between the source and drain electrode layers and the gate insulating layer, so that ohmic contact is made.

Abstract: To realize a semiconductor device including a capacitor element capable of obtaining a sufficient capacitor without reducing an opening ratio, in which a pixel electrode is flattened in order to control a defect in orientation of liquid crystal. A semiconductor device of the present invention includes a light-shielding film formed on the thin film transistor, a capacitor insulating film formed on the light-shielding film, a conductive layer formed on the capacitor insulating film, and a pixel electrode that is formed so as to be electrically connected to the conductive layer, in which a storage capacitor element comprises the light-shielding film, the capacitor insulating film, and the conductive layer, whereby an area of a region serving as the capacitor element can be increased.

Abstract: A method of forming a film pattern with micro-pattern and a method of manufacturing a thin film transistor liquid crystal display (TFT-LCD) array substrate are provided. The method of manufacturing the film pattern with micro-pattern comprises: depositing a thin film on a substrate; jetting or dropping etchant on the thin film with a predetermined etching pattern by an inkjet print device; etching the thin film by the etchant; and cleaning the thin film to form a film pattern on the substrate.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate, a channel layer, a gate insulation layer, a source, a drain and a silicon-aluminum-oxide layer. The gate is disposed on a substrate. The channel layer is disposed on the substrate. The channel layer overlaps the gate. The gate insulation layer is disposed between the gate and the channel layer. The source and the drain are disposed on two sides of the channel layer. The silicon-aluminum-oxide layer is disposed on the substrate and covers the source, the drain and the channel layer.

Abstract: Disclosed is a display device and an electronic apparatus incorporating the display device. The display device includes a transistor and a planarization film over the transistor. The planarization film has an opening where an edge portion is rounded. The display device further includes a first electrode over the planarization film and an organic resin film over the first electrode. The organic resin film also has an opening where an edge portion is rounded. The organic resin film is located in the opening of the planarization film. The first electrode and the transistor are electrically connected to each other through a conductive film. The first electrode is in contact with a top surface of the conductive film. Over the first electrode, a light-emitting member and a second electrode are provided.

Abstract: A liquid crystal display device including first and second substrates, with a liquid crystal layer sealed therebetween; and first and second electrodes formed, respectively, on the first and second substrates. A first molecule orientation film is formed on the first substrate so as to cover the first electrode and a second molecule orientation film formed on the second substrate so as to cover the second electrode. A polarizer with a light absorption axis P is provided outside of the first substrate, and an analyzer with a light absorption axis A is provided outside of the second substrate. The light absorption axis A crosses the light absorption axis P. A plurality of micro structures are associated with at least one of the first and second electrodes, wherein the micro structures are obliquely arranged with respect to the light absorption axis P and the light absorption axis A.

Abstract: A thin film transistor array panel is provided, which includes a plurality of gate lines, a plurality of common electrodes, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer, a plurality of drain electrodes formed on the semiconductor layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn is not produced on the surfaces of the common electrode.

Abstract: A thin film transistor array panel is provided and includes a gate line, a gate insulating layer covering the gate line, a semiconductor layer disposed on the gate insulating layer, and a data line and a drain electrode disposed on the semiconductor layer. The data line and the drain electrode have a dual-layered structure including a lower layer and an upper layer with the lower layer having a first portion protruded outside the upper layer and the semiconductor layer having a second portion protruded outside the edge of the lower layer.

Abstract: A manufacturing method of an array substrate includes the following steps. A gate electrode and a gate insulator layer are successively formed on a substrate. A semiconductor layer, an etching stop layer, a hard mask layer, and a second patterned photoresist are successively formed on the gate insulator layer. The second patterned photoresist is employed for performing an over etching process to the hard mask layer to form a patterned hard mask layer. The second patterned photoresist is employed for performing a first etching process to the etching stop layer. The second patterned photoresist is then employed for performing a second etching process to the semiconductor layer to form a patterned semiconductor layer. The etching stop layer uncovered by the patterned hard mask layer is then removed for forming a patterned etching stop layer.

Abstract: A thin film transistor (TFT) array substrate and a manufacturing method thereof are provided. The TFT array substrate may include a gate line disposed on a substrate and including a gate line and a gate electrode, an oxide semiconductor layer pattern disposed on the gate electrode, a data line disposed on the oxide semiconductor layer pattern and including a source electrode and a drain electrode of a thin film transistor (TFT) together with the gate electrode, and a data line extending in a direction intersecting the gate line, and etch stop patterns disposed at an area where the TFT is formed between the source/drain electrodes and the oxide semiconductor layer pattern and at an area where the gate line and the data line overlap each other between the gate line and the data line.

Abstract: A manufacturing method of pixel structure includes: sequentially forming a gate, a gate insulation layer, a semiconductor layer and a conductive layer on a substrate; forming a first patterned photoresist layer including multiple first photoresist blocks and multiple second photoresist blocks on the conductive layer; reducing the thickness of the first patterned photoresist layer until the second photoresist blocks are completely removed; forming a pixel electrode layer and a second photoresist layer on a partial pixel electrode layer; removing a part of the pixel electrode layer exposed by the second photoresist layer, a partial conductive layer and a partial semiconductor layer both under the removed pixel electrode layer to define a first electrode block, a second electrode block and a channel region; removing the remained first patterned photoresist layer and second photoresist layer and forming a protective layer and a common electrode layer on a part of the protective layer.

Abstract: A method for forming a conductor structure is provided. The method comprises: (1) providing a substrate; (2) forming a patterned dielectric layer with a first opening which exposes a portion of the substrate; forming a patterned organic material layer on the dielectric layer with a second opening which corresponds to the first opening and expose the exposed portion of the substrate; (3) forming a first barrier layer on the organic material layer and the exposed portion of the substrate; (4) forming a metal layer on the first barrier layer; and (5) removing the organic material layer, the first barrier layer thereon and the metal layer thereon.

Abstract: Disclosed is a method that includes: forming a gate electrode on a substrate, then forming an insulation layer so as to completely cover the gate electrode, thereafter forming a semiconductor layer on the insulation layer, and then forming a crystallization-inducing metal layer on the semiconductor layer; removing the part of at least the crystallization-inducing metal layer that is over a channel region of the semiconductor layer; forming source and drain electrodes at a location which is over source and drain regions respectively located at opposite sides with respect to the channel region of the semiconductor layer and is above the crystallization-inducing metal layer; and heating the crystallization-inducing metal layer so as to form a silicide layer of a crystallization-inducing metal.

Abstract: A method for manufacturing a flexible semiconductor device comprises (i) forming an insulating film on the upper surface of a resin film, (ii) forming a pattern of extraction electrodes on the upper surface of the resin film, (iii) forming a semiconductor layer on the insulating film in such a manner that the semiconductor layer is in contact with the pattern of extraction electrodes, and (iv) forming a sealing resin layer on the upper surface of the resin film in such a manner that the sealing resin layer covers the semiconductor layer and the pattern of extraction electrodes, wherein at least one of the stepsof the above steps (i) to (iv) is carried out by a printing method. With this manufacturing method, various layers can be formed by a simple printing process without using a vacuum process, photolithography, or the like.

Abstract: A threshold voltage of a thin film transistor is adjusted. The thin film transistor is manufactured through the steps of: introducing a semiconductor material gas into a treatment chamber; forming a semiconductor film in the treatment chamber over a gate insulating layer provided covering a gate electrode; evacuating the semiconductor material gas in the treatment chamber; introducing rare gas into the treatment chamber; performing plasma treatment on the semiconductor film in the treatment chamber; forming an impurity semiconductor film over the semiconductor film; processing the semiconductor film and the impurity semiconductor film into island shapes, so that a semiconductor stack is formed; forming source and drain electrodes in contact with an impurity semiconductor layer included in the semiconductor stack. Argon is preferably used as the rare gas. The rare gas element is preferably contained in the semiconductor film at 2.5×1018 cm?3 or more.

Abstract: Disclosed is a method of fabricating a LCD device that includes forming sacrifice layer patterns in a pixel region while forming a gate line, a first storage electrode, and a gate pad on a substrate; sequentially forming a gate insulation film, an amorphous silicon film, an impurity-doped amorphous silicon film, and a source/drain metal film on a substrate, forming a transparent conductive material on the substrate covered with a protection and then patterning the transparent conductive material to form a second storage electrode overlapping the first storage electrode and an electrode pattern having a part overlapping an area of one side edge of the sacrifice layer patterns and the other part formed on the substrate; and simultaneously forming a common electrode and a pixel electrode in the pixel region by performing a lift-off process to remove the sacrifice layer patterns on the substrate where the electrode pattern is formed.

Abstract: A semiconductor device has a planarizing layer that is made of an inorganic film, and has a recessed portion formed in a region thereof in which a conductive film is disposed. A first contact hole penetrating through at least an interlayer insulating film is formed on a first wiring layer, while a second contact hole penetrating through at least the interlayer insulating film is formed on the conductive film so as to run through the inside of the recessed portion.

Abstract: A thin film transistor, including a transparent channel pattern, a transparent gate insulating layer in contact with the channel pattern, a passivation film pattern disposed on the channel pattern, a source/drain coupled to the channel pattern through a via hole in the passivation film pattern, and a gate facing the channel pattern, the gate insulating layer interposed between the gate and the channel pattern, wherein the passivation film pattern includes at least one of polyimide, photoacryl, and spin on glass (SOG).