Amorphous Silicon Or Polysilicon Transistor (epo) Patents (Class 257/E21.412)
  • Patent number: 10950678
    Abstract: A thin film transistor substrate that includes a substrate, a lower gate electrode arranged on the substrate, a semiconductor layer arranged on the substrate and overlapping the lower gate electrode, the semiconductor layer including a channel region interposed between a source region and a drain region, and an upper gate electrode arranged on the substrate and overlapping the semiconductor layer, the upper gate electrode being arranged on an opposite side of the semiconductor layer than the lower gate electrode, wherein at least one of the lower gate electrode and the upper gate electrode is perforated by an aperture to reduce a parasitic capacitance between the upper and lower gate electrodes.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: March 16, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Eunhyun Kim, Taeyoung Kim, Hyehyang Park, Shinhyuk Yang
  • Patent number: 10847558
    Abstract: A solid-state imaging apparatus includes a first substrate that includes a plurality of photoelectric conversion units, a second substrate that includes at least a part of a readout circuit configured to read signals based on electric charges of the plurality of photoelectric conversion units and a peripheral circuit including a control circuit, and a wiring structure that is disposed between the first substrate and the second substrate and includes a pad portion electrically connected to the peripheral circuit via a draw-out wiring and an insulating layer. The wiring structure has, at least at a part thereof, a seal ring disposed in such a way as to surround the photoelectric conversion units and the peripheral circuit.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: November 24, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Masahiro Kobayashi
  • Patent number: 10680116
    Abstract: The semiconductor device includes a first insulating layer, a second insulating layer, an oxide semiconductor layer, and first to third conductive layers. The first conductive layer and the second conductive layer are connected to the oxide semiconductor layer. The second insulating layer includes a region in contact with the oxide semiconductor layer, and the third conductive layer includes a region in contact with the second insulating layer. The oxide semiconductor layer includes first to third regions. The first region and the second region are separated from each other, and the third region is located between the first region and the second region. The third region and the third conductive layer overlap with each other with the second insulating layer located therebetween. The first region and the second region include a region having a higher carbon concentration than the third region.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: June 9, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Masami Jintyou, Yukinori Shima
  • Patent number: 10319827
    Abstract: A high voltage transistor may be formed on the basis of well-established CMOS techniques by using a buried insulating material of an SOI architecture as gate dielectric material, while the gate electrode material may be provided in the form of a doped semiconductor region positioned below the buried insulating layer. The high voltage transistor may be formed with high process compatibility on the basis of a process flow for forming sophisticated fully depleted SOI transistors, wherein, in some illustrative embodiments, the high voltage transistor may also be provided as a fully depleted transistor configuration.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: June 11, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Elliot John Smith, Nigel Chan
  • Patent number: 10276698
    Abstract: A method of forming an electrical device that includes forming a gate dielectric layer over a gate electrode, forming source and drain electrodes on opposing sides of the gate electrode, wherein one end of the source and drain electrodes provides a coplanar surface with the gate dielectric, and positioning a 1D or 2D nanoscale material on the coplanar surface to provide the channel region of the electrical device.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael Engel, Mathias B. Steiner
  • Patent number: 9966415
    Abstract: A complementary thin film transistor and manufacturing method thereof are provided. The complementary thin film transistor has a substrate, an n-type semiconductor layer, a p-type semiconductor layer, a first passivation layer, a first electrode metal layer, and a second electrode metal layer. The n-type semiconductor layer is disposed above the substrate, and comprises a metal oxide material. The p-type semiconductor layer is disposed above the substrate, and comprises an organic semiconductor material. The first passivation layer is disposed between the n-type semiconductor layer and the p-type semiconductor layer, and formed with at least one contacting hole. The first electrode metal layer and the second electrode metal layer are electrically connected with each other through the contacting hole.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: May 8, 2018
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Mian Zeng, Hsiangchih Hsiao, Shengdong Zhang
  • Patent number: 9716119
    Abstract: Disclosed are a manufacturing method of a dual gate TFT substrate and a structure thereof. The manufacturing method of a dual gate TFT substrate includes sequentially manufacturing a bottom gate, a first isolation layer, an island shaped semiconductor layer, and a second isolation layer on a substrate; then, depositing a second metal layer, and implementing a patterning process to the second metal layer with one mask to form a source, a drain and a top gate at the same time; and then, sequentially manufacturing a third isolation layer and a pixel electrode. It can promote the stability of the TFT, reduce the amount of the masks, and shorten the process flow, simplifying the manufacture process and diminishing the production cost. In the structure of the dual gate TFT substrate, the structure is simple, and the stability of the TFT is better, and easy to manufacture.
    Type: Grant
    Filed: May 25, 2015
    Date of Patent: July 25, 2017
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Wenhui Li
  • Patent number: 9419181
    Abstract: According to various embodiments, an electrode may include at least one layer including a chemical compound including aluminum and titanium.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: August 16, 2016
    Assignee: INFINEON TECHNOLOGIES DRESDEN GMBH
    Inventors: Dirk Meinhold, Sven Schmidbauer, Markus Fischer, Norbert Urbansky
  • Patent number: 8946712
    Abstract: A light blocking member having variable transmittance, a display panel including the same, and a manufacturing method thereof. A light blocking member having a variable transmittance according to one exemplary embodiment includes a polymerizable compound, a binder, and a thermochromic material that exhibits a black color at a temperature below a threshold temperature and becomes transparent at a temperature above the threshold temperature.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: February 3, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byung-Duk Yang, Vladimir Urazaev, Sung-Wook Kang
  • Patent number: 8912057
    Abstract: A semiconductor device with an n-type transistor and a p-type transistor having an active region is provided. The active region further includes two adjacent gate structures. A portion of a dielectric layer between the two adjacent gate structures is selectively removed to form a contact opening having a bottom and sidewalls over the active region. A bilayer liner is selectively provided within the contact opening in the n-type transistor and a monolayer liner is provided within the contact opening in the p-type transistor. The contact opening in the n-type transistor and p-type transistor is filled with contact material. The monolayer liner is treated to form a silicide lacking nickel in the p-type transistor.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: December 16, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Derya Deniz
  • Patent number: 8906738
    Abstract: Disclosed herein is a method of manufacturing a thin film transistor having a structure that a gate electrode and an oxide semiconductor layer are disposed with a gate insulating film interposed between the gate electrode and the oxide semiconductor layer, and a source/drain electrode is electrically connected to the oxide semiconductor layer, the method including: continuously depositing an aluminum oxide (Al2O3) layer as a protective film and an aluminum (Al) layer in this order on any of the source/drain electrode, the gate insulating film, and the oxide semiconductor layer by using sputtering.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: December 9, 2014
    Assignee: Sony Corporation
    Inventors: Takahide Ishii, Yoshihiro Oshima
  • Patent number: 8890161
    Abstract: The present invention relates to methods for fabricating a thin film transistor substrate.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: November 18, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Hee-Young Kwack, Mun Gi Park
  • Patent number: 8878175
    Abstract: An object is to reduce a capacitance value of parasitic capacitance without decreasing driving capability of a transistor in a semiconductor device such as an active matrix display device. Further, another object is to provide a semiconductor device in which the capacitance value of the parasitic capacitance was reduced, at low cost. An insulating layer other than a gate insulating layer is provided between a wiring which is formed of the same material layer as a gate electrode of the transistor and a wiring which is formed of the same material layer as a source electrode or a drain electrode.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: November 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8835236
    Abstract: A method for manufacturing an oxide semiconductor thin film transistor (TFT) is provided, which includes the steps below. A source electrode and a drain electrode are provided. A patterned insulating layer is formed to partially cover the source electrode and the drain electrode, and expose a portion of the source electrode and a portion of the drain electrode. An oxide semiconductor layer is formed to contact the portion of the source electrode and the portion of the drain electrode. A gate electrode is provided. A gate dielectric layer positioned between the oxide semiconductor layer and the gate electrode is provided. An oxide semiconductor TFT is also provided herein.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: September 16, 2014
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventor: Hsi-Ming Chang
  • Patent number: 8796768
    Abstract: In an organic light-emitting display device and a method of manufacturing the same, the display device may include: a thin-film transistor including an active layer, a gate electrode including a first electrode which includes nano-Ag on an insulating layer formed on the active layer and a second electrode on the first electrode, a source electrode, and a drain electrode; an organic light-emitting device including a pixel electrode electrically connected to the thin-film transistor and formed of the same layer as, and using the same material used to form, the first electrode, an intermediate layer including an emissive layer, and an opposite electrode covering the intermediate layer and facing the pixel electrode; and a pad electrode formed of the same layer as, and using the same material used to form, the first electrode in a pad area located outside of a light-emitting area.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: August 5, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventor: Chun-Gi You
  • Patent number: 8779428
    Abstract: A transistor includes a first active layer having a first channel region and a second active layer having a second channel region. A first gate of the transistor is configured to control electrical characteristics of at least the first active layer and a second gate is configured to control electrical characteristics of at least the second active layer. A source electrode contacts the first and second active layers. A drain electrode also contacts the first and second active layers.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: July 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eok-su Kim, Sang-yoon Lee, Myung-kwan Ryu
  • Patent number: 8748215
    Abstract: One embodiment is a method for manufacturing a stacked oxide material, including the steps of forming an oxide component over a base component; forming a first oxide crystal component which grows from a surface toward an inside of the oxide component by heat treatment, and leaving an amorphous component just above a surface of the base component; and stacking a second oxide crystal component over the first oxide crystal component. In particular, the first oxide crystal component and the second oxide crystal component have common c-axes. Same-axis (axial) growth in the case of homo-crystal growth or hetero-crystal growth is caused.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: June 10, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8748891
    Abstract: A manufacturing process of an LCD device of the invention includes forming a first substrate provided with a pixel part with thin film transistors and a seal portion arranged around the pixel part, forming a second substrate opposed to the first substrate, filling a liquid crystal layer between the first substrate and the second substrate, and adhering the first substrate to the second substrate with a sealant provided for the seal portion, wherein the forming the first substrate includes forming a semiconductor layer composing the thin film transistor, forming in the seal portion a semiconductor connection layer made of a same material as the semiconductor layer, and forming an organic interlayer insulating film, wherein the forming the semiconductor layer and the forming the semiconductor connection layer are performed in the same step.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: June 10, 2014
    Assignee: NLT Technologies, Ltd.
    Inventors: Hideaki Takamatsu, Fumihiko Matsuno
  • Patent number: 8723240
    Abstract: A manufacturing method for a semiconductor device, the method including forming a thin film transistor by forming a polysilicon thin film on an insulating substrate, forming a gate electrode via a gate insulating film, and forming source/drain regions and a channel region by ion implantation in the polysilicon thin film by using the gate electrode as a mask, forming an interconnection layer on an interlayer dielectric film covering this thin film transistor and forming a first contact to be connected to the thin film transistor through the interlayer dielectric film, forming a silicon hydronitride film on the interlayer dielectric film so as to cover the interconnection layer, forming a lower electrode on this silicon hydronitride film and forming a second contact to be connected to the interconnection layer through the silicon hydronitride film, and forming a ferroelectric layer on the lower electrode.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: May 13, 2014
    Assignee: Gold Charm Limited
    Inventor: Hiroshi Tanabe
  • Patent number: 8669557
    Abstract: The present invention relates to a thin film transistor substrate and a method for fabricating the same which can reduce a number of steps.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: March 11, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Hee-Young Kwack, Mun Gi Park
  • Patent number: 8659026
    Abstract: A high-speed flat panel display has thin film transistors in a pixel array portion in which a plurality of pixels are arranged and a driving circuit portion for driving the pixels of the pixel array portion, which have different resistance values than each other or have different geometric structures than each other. The flat panel display comprises a pixel array portion where a plurality of pixels are arranged, and a driving circuit portion for driving the pixels of the pixel array portion. The thin film transistors in the pixel array portion and the driving circuit portion have different resistance values in their gate regions or drain regions than each other, or have different geometric structures than each other. One thin film transistor has a zigzag shape in its gate region or drain region or has an offset region.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: February 25, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jae-Bon Koo, Ji-Yong Park, Sang-Il Park, Ki-Yong Lee, Ul-Ho Lee
  • Publication number: 20140042427
    Abstract: A method is provided for fabricating a thin-film transistor (TFT). The method includes forming a semiconductor layer over a gate insulator that covers a gate electrode, and depositing an insulator layer over the semiconductor layer, as well as etching the insulator layer to form a patterned etch-stop without losing the gate insulator. The method also includes forming a source electrode and a drain electrode over the semiconductor layer and the patterned etch-stop. The method further includes removing a portion of the semiconductor layer beyond the source electrode and the drain electrode such that a remaining portion of the semiconductor layer covers the gate insulator in a first overlapping area of the source electrode and the gate electrode and a second overlapping area of the drain electrode and gate electrode.
    Type: Application
    Filed: September 27, 2012
    Publication date: February 13, 2014
    Applicant: Apple Inc.
    Inventors: Ming-Chin Hung, Kyung Wook Kim, Young Bae Park, Hao-Lin Chiu, Chun-Yao Huang, Shih Chang Chang
  • Patent number: 8643009
    Abstract: To suppress deterioration in electrical characteristics in a transistor including an oxide semiconductor layer or a semiconductor device including the transistor. In a transistor in which a channel layer is formed using an oxide semiconductor, a silicon layer is provided in contact with a surface of the oxide semiconductor layer. Further, the silicon layer is provided in contact with at least a region of the oxide semiconductor layer, in which a channel is formed, and a source electrode layer and a drain electrode layer are provided in contact with regions of the oxide semiconductor layer, over which the silicon layer is not provided.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: February 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichiro Sakata, Hiromichi Godo, Takashi Shimazu
  • Patent number: 8637844
    Abstract: The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: January 28, 2014
    Assignees: International Business Machines Corporation, Macronix International Co., Ltd., Qimonda AG
    Inventors: Bipin Rajendran, Thomas Happ, Hsiang-Lan Lung, Min Yang
  • Patent number: 8633487
    Abstract: Disclosed is a transistor structure including: a first thin film transistor including, a first gate electrode; a first insulating film; a first semiconductor film; and a first light blocking film, and a second thin film transistor including, a second semiconductor film; the second insulating film; a second gate electrode; and a second light blocking film, wherein the first semiconductor film and the second semiconductor film include a first region and a second region along a thickness direction from the first insulating film side; and degree of crystallization of silicon of one of the first region or the second region is higher than the degree of crystallization of silicon of the other of the first region or the second region.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: January 21, 2014
    Assignee: Casio Computer Co., Ltd.
    Inventor: Kazuto Yamamoto
  • Publication number: 20140001462
    Abstract: A method of fabricating a stable, high mobility metal oxide thin film transistor includes the steps of providing a substrate, positioning a gate on the substrate, and depositing a gate dielectric layer on the gate and portions of the substrate not covered by the gate. A multiple film active layer including a metal oxide semiconductor film and a metal oxide passivation film is deposited on the gate dielectric with the passivation film positioned in overlying relationship to the semiconductor film. An etch-stop layer is positioned on a surface of the passivation film and defines a channel area in the active layer. A portion of the multiple film active layer on opposite sides of the etch-stop layer is modified to form an ohmic contact and metal source/drain contacts are positioned on the modified portion of the multiple film active layer.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 2, 2014
    Inventors: Chan-Long Shieh, Gang Yu, Fatt Foong, Tian Xiao, Juergen Musolf
  • Patent number: 8608971
    Abstract: A method of manufacturing a display substrate includes forming a first metallic pattern including gate and storage conductors and a gate electrode of a switching device on a base substrate, forming a gate insulation layer, forming a second metallic pattern and a channel portion including a source line, source and drain electrodes of the switching device, forming a passivation layer and a photoresist film on the second metallic pattern, patterning the photoresist film to form a first pattern portion corresponding to the gate and source conductors and the switching device, and a second pattern portion formed on the storage line, etching the passivation layer and the gate insulation layer, and forming a pixel electrode using the first pattern portion.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: December 17, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hong-Kee Chin, Sang-Gab Kim, Min-Seok Oh
  • Patent number: 8598584
    Abstract: In the thin-film transistor device: the stacked thickness of either a source electrode or a drain electrode and a corresponding one of silicon layers is the same value or a value close to the same value as the stacked thickness of a first channel layer and a second channel layer; the stacked thickness of the first channel layer and the second channel layer is the same in a region between the source electrode and the drain electrode and above the source electrode and the drain electrode; the first channel layer and the second channel layer are sunken in the region between the source electrode and the drain electrode, following a shape between the source electrode and the drain electrode; and the gate electrode has one region overlapping with the source electrode and an other region overlapping with the drain electrode.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: December 3, 2013
    Assignees: Panasonic Corporation, Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Hisao Nagai, Sadayoshi Hotta, Genshiro Kawachi
  • Patent number: 8580661
    Abstract: A method for hydrogenating poly-si. Poly-si is placed into the interior of a chamber. A filament is placed into the interior of a chamber. The base pressure of the interior of the chamber is evacuated, preferably to 10?6 Torr or less. The poly-si is heated for a predetermined poly-si heating time. The filament is heated by providing an electrical power to the filament. Hydrogen is supplied into the pressurized interior of the chamber comprising the heated poly-si and the heated filament. Atomic hydrogen is produced by the filament at a rate whereby the atomic hydrogen surface density at the poly-si is less than the poly-si surface density. Preferably, the poly-si is covered from the atomic hydrogen produced by the heated filament for a first predetermined covering time. Preferably, the poly-si is then uncovered from the atomic hydrogen produced by the heated filament for a first hydrogenation time.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: November 12, 2013
    Assignee: U.S. Department of Energy
    Inventor: Qi Wang
  • Publication number: 20130240888
    Abstract: A method of fabricating a thin film transistor substrate includes: forming a polymer layer on a glass substrate; forming a passivation layer on the polymer layer; forming a thin film transistor array on the passivation layer; and separating the glass substrate from the polymer layer by irradiating a laser from a rear surface of the glass substrate.
    Type: Application
    Filed: June 27, 2012
    Publication date: September 19, 2013
    Inventors: Yoon-Dong CHO, Jong-Hyun Park, Soo-Young Yoon, Mi-Jung Lee, Jae-kyung Choi
  • Patent number: 8502229
    Abstract: An array substrate including a substrate having a pixel region, a gate line and a gate electrode on the substrate, the gate electrode being connected to the gate line, a gate insulating layer on the gate line and the gate electrode, an oxide semiconductor layer on the gate insulating layer, an auxiliary pattern on the oxide semiconductor layer, and source and drain electrodes on the auxiliary pattern, the source and drain electrodes being disposed over the auxiliary pattern and spaced apart from each other to expose a portion of the auxiliary pattern, the exposed portion of the auxiliary pattern exposing a channel region and including a metal oxide over the channel region, wherein a data line crosses the gate line to define the pixel region and is connected to the source electrode, a passivation layer on the source and drain electrodes and the data line.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: August 6, 2013
    Assignee: LG Display Co., Ltd.
    Inventors: Yong-Yub Kim, Chang-Il Ryoo
  • Publication number: 20130187221
    Abstract: A method of forming a semiconductor device includes performing a first pre-amorphous implantation process on a substrate, where the substrate has a gate stack. The method further includes forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate, and performing a second annealing process on the substrate and the second stress film.
    Type: Application
    Filed: January 23, 2012
    Publication date: July 25, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Yuan Lu, Li-Ping Huang, Han-Ting Tsai, Wei-Ching Wang, Ming-Shuan Li, Hsueh-Jen Yang, Kuan-Chung Chen
  • Patent number: 8492770
    Abstract: A thin film transistor includes a gate electrode formed on a substrate, a semiconductor pattern overlapped with the gate electrode, a source electrode overlapped with a first end of the semiconductor pattern and a drain electrode overlapped with a second end of the semiconductor pattern and spaced apart from the source electrode. The semiconductor pattern includes an amorphous multi-elements compound including a II B element and a VI A element or including a III A element and a V A element and having an electron mobility no less than 1.0 cm2/Vs and an amorphous phase, wherein the VI A element excludes oxygen. Thus, a driving characteristic of the thin film transistor may be improved.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: July 23, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jae-Woo Park, Je-Hun Lee, Seong-Jin Lee, Yeon-Hong Kim
  • Patent number: 8487312
    Abstract: To provide a semiconductor device with a TFT, capable of reducing the electric resistance of a power supply wiring without increasing the off-current. The semiconductor device includes an insulating film with a surface; a semiconductor layer which is formed over the surface of the insulating film and which includes a channel region and a pair of source/drain regions and sandwiching the channel region; and a power supply wiring for supplying power to the source region. A concave portion is formed in the surface of the insulating film. The power supply wiring includes a layer formed from the same layer as the semiconductor layer, and has a first portion formed over the surface of the insulating film and a second portion formed in the concave portion. The bottom of the second portion is covered with an insulator.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: July 16, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Yukio Maki
  • Patent number: 8476124
    Abstract: The method of manufacturing the semiconductor device includes amorphizing a first region and a second region of a semiconductor substrate by an ion implantation, implanting a first impurity and a second impurity respectively in the first region and the second region, activating the implanted impurities to form a first impurity layer and a second impurity layer, epitaxially growing a semiconductor layer above the semiconductor substrate with the impurity layers formed on, growing a gate insulating film above the first region and the second region, and forming a first gate electrode above the gate insulating film in the first region and the second gate electrode above the gate insulating film in the second region.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: July 2, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Junji Oh
  • Patent number: 8450158
    Abstract: A seed crystal which includes mixed phase grains including an amorphous silicon region and a crystallite which is a microcrystal that can be regarded as a single crystal is formed on an insulating film by a plasma CVD method under a first condition that enables mixed phase grains having high crystallinity and high uniformity of grain sizes to be formed at a low density, and then a microcrystalline semiconductor film is formed to be stacked on the seed crystal by a plasma CVD method under a second condition that enables the mixed phase grains to grow to fill a space between the mixed phase grains.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: May 28, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryu Komatsu, Yasuhiro Jinbo, Hidekazu Miyairi
  • Publication number: 20130105797
    Abstract: A method of manufacturing a thin-film semiconductor device according to the present disclosure includes: preparing a substrate; forming a gate electrode above the substrate; forming a first insulating film on the gate electrode; forming a semiconductor thin film that is to be a channel layer, on the first insulating film; forming a second insulating film on the semiconductor thin film; irradiating the second insulating film with a beam so as to increase a transmittance of the second insulating film; and forming a source electrode and a drain electrode above the channel layer.
    Type: Application
    Filed: April 5, 2012
    Publication date: May 2, 2013
    Applicants: C/O PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD., PANASONIC CORPORATION
    Inventors: Hiroshi HAYASHI, Takahiro KAWASHIMA, Genshiro KAWACHI
  • Patent number: 8431496
    Abstract: A threshold voltage of a thin film transistor is adjusted. The thin film transistor is manufactured through the steps of: introducing a semiconductor material gas into a treatment chamber; forming a semiconductor film in the treatment chamber over a gate insulating layer provided covering a gate electrode; evacuating the semiconductor material gas in the treatment chamber; introducing rare gas into the treatment chamber; performing plasma treatment on the semiconductor film in the treatment chamber; forming an impurity semiconductor film over the semiconductor film; processing the semiconductor film and the impurity semiconductor film into island shapes, so that a semiconductor stack is formed; forming source and drain electrodes in contact with an impurity semiconductor layer included in the semiconductor stack. Argon is preferably used as the rare gas. The rare gas element is preferably contained in the semiconductor film at 2.5×1018 cm?3 or more.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: April 30, 2013
    Assignee: Semiconductor Energy Labortory Co., Ltd.
    Inventor: Satoshi Toriumi
  • Patent number: 8426863
    Abstract: A thin film transistor according to one or more embodiments of the present invention includes: an insulation substrate; a gate electrode formed on the substrate; a gate insulating layer formed on the gate electrode; a semiconductor formed on the gate insulating layer and having a pair of openings facing each other; ohmic contact layers formed in the openings and including a conductive impurity; and a source electrode and a drain electrode in contact with their respective ohmic contact layers. An organic light emitting device in accordance with an embodiment includes: a first signal line and a second signal line intersecting each other on an insulation substrate; a switching thin film transistor connected to the first signal line and the second signal line; a driving thin film transistor connected to the switching thin film transistor; and a light emitting diode (LED) connected to the driving thin film transistor.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: April 23, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yong-Hwan Park, Byoung-Seong Jeong, Joon-Hoo Choi, Sang-Ho Moon
  • Publication number: 20130092944
    Abstract: To suppress a decrease in on-state current in a semiconductor device including an oxide semiconductor. Provided is a semiconductor device including the following: an oxide semiconductor film which serves as a semiconductor layer; a gate insulating film including an oxide containing silicon, over the oxide semiconductor film; a gate electrode which overlaps with at least the oxide semiconductor film, over the gate insulating film; and a source electrode and a drain electrode which are electrically connected to the oxide semiconductor film. In the semiconductor device, the oxide semiconductor film overlapping with at least the gate electrode includes a region in which a concentration of silicon distributed from the interface with the gate insulating film toward the inside of the oxide semiconductor film is lower than or equal to 1.1 at. %.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 18, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Semiconductor Energy Laboratory Co., Ltd.
  • Publication number: 20130092924
    Abstract: A miniaturized transistor having excellent electrical characteristics is provided with high yield. Further, a semiconductor device including the transistor and having high performance and high reliability is manufactured with high productivity. In a semiconductor device including a transistor in which an oxide semiconductor film including a channel formation region and low-resistance regions between which the channel formation region is sandwiched, a gate insulating film, and a gate electrode layer whose top surface and side surface are covered with an insulating film including an aluminum oxide film are stacked, a source electrode layer and a drain electrode layer are in contact with part of the oxide semiconductor film and the top surface and a side surface of the insulating film including an aluminum oxide film.
    Type: Application
    Filed: October 1, 2012
    Publication date: April 18, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Semiconductor Energy Laboratory Co., Ltd.
  • Patent number: 8420458
    Abstract: A semiconductor device has a planarizing layer that is made of an inorganic film, and has a recessed portion formed in a region thereof in which a conductive film is disposed. A first contact hole penetrating through at least an interlayer insulating film is formed on a first wiring layer, while a second contact hole penetrating through at least the interlayer insulating film is formed on the conductive film so as to run through the inside of the recessed portion.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: April 16, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Makoto Nakazawa, Mitsunobu Miyamoto
  • Patent number: 8415678
    Abstract: A semiconductor device of the present invention is a semiconductor device including a thin film transistor and a thin film diode. A semiconductor layer (113) of the thin film transistor and a semiconductor layer (114) of the thin film diode are both crystalline semiconductor layers. The semiconductor layer (113) of the thin film transistor and the semiconductor layer (114) of the thin film diode respectively include portions formed by crystallizing the same amorphous semiconductor film. The thickness of the semiconductor layer (114) of the thin film diode is greater than the thickness of the semiconductor layer (113) of the thin film transistor. The difference between the thickness of the semiconductor layer (113) of the thin film transistor and the thickness of the semiconductor layer (114) of the thin film diode is greater than 25 nm.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: April 9, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masaki Yamanaka, Hiroshi Nakatsuji, Naoki Makita
  • Patent number: 8405072
    Abstract: An organic electro-luminescent display and a method of fabricating the same include an organic light emitting diode, a driving transistor which drives the organic light emitting diode, and a switching transistor which controls an operation of the driving transistor, wherein active layers of the switching and driving transistors are crystallized using silicides having different densities such that the active layer of the driving transistor has a larger grain size than the active layer of the switching layer.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: March 26, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-sim Jung, Jong-man Kim, Jang-yeon Kwon, Kyung-bae Park
  • Publication number: 20130069066
    Abstract: Disclosed is a thin film transistor, comprising a first conductive layer, a first insulation layer, an amorphous silicon layer, an ohmic contact layer, a second insulation layer, a second conductive layer, a protective layer and a transparent electrode layer. The present invention also relates to a manufacture method of the thin film transistor. The thin film transistor and the manufacture method of the present invention implements merely three stages of photolithography processes to complete the manufacture of the thin film transistor, and therefore to save the manufacture cost and the process time of the thin film transistor.
    Type: Application
    Filed: September 27, 2011
    Publication date: March 21, 2013
    Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO.,LTD.
    Inventor: Tsunglung Chang
  • Patent number: 8389343
    Abstract: A method for manufacturing a semiconductor device is provided, which comprises at least a steps of forming a gate insulating film over a substrate, a step of forming a microcrystalline semiconductor film over the gate insulating film, and a step of forming an amorphous semiconductor film over the microcrystalline semiconductor film. The microcrystalline semiconductor film is formed by introducing a silicon hydride gas or a silicon halide gas when a surface of the gate insulating film is subjected to hydrogen plasma to generate a crystalline nucleus over the surface of the gate insulating film, and by increasing a flow rate of the silicon hydride gas or the silicon halide gas.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: March 5, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8383434
    Abstract: A method for manufacturing a thin film transistor having high electric characteristics with high productivity. In the method for forming a channel region of a dual-gate thin film transistor including a first gate electrode and a second gate electrode which faces the first gate electrode with the channel region provided therebetween, a first microcrystalline semiconductor film is formed under a first condition for forming a microcrystalline semiconductor film in which a space between crystal grains is filled with an amorphous semiconductor, and a second microcrystalline semiconductor film is formed over the first microcrystalline semiconductor film under a second condition for promoting crystal growth.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: February 26, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Toshiyuki Isa
  • Publication number: 20130037808
    Abstract: A thin-film transistor device which is a bottom-gate thin-film transistor device, includes: a gate electrode formed above a substrate; a gate insulating film formed above the gate electrode; a crystalline silicon thin film formed above the gate insulating film and having a channel region; an amorphous silicon thin film formed above the crystalline silicon thin film including the channel region; and a source electrode and a drain electrode formed above the amorphous silicon thin film, in which an optical bandgap of the amorphous silicon thin film and an off-state current of the thin-film transistor device have a positive correlation.
    Type: Application
    Filed: October 1, 2012
    Publication date: February 14, 2013
    Applicant: PANASONIC CORPORATION
    Inventor: PANASONIC CORPORATION
  • Publication number: 20130032797
    Abstract: The present invention achieves a formation of a metal oxide film of a thin film transistor with a simplified process. The present invention is concerned with a method for manufacturing a field-effect transistor comprising a gate electrode, a source electrode, a drain electrode, a channel layer and a gate insulating layer wherein the channel layer is formed by using a metal salt-containing composition comprising a metal salt, a polyvalent carboxylic acid having a cis-form structure of —C(COOH)?C(COOH)—, an organic solvent and a water wherein a molar ratio of the polyvalent carboxylic acid to the metal salt is in the range of 0.5 to 4.0.
    Type: Application
    Filed: December 19, 2011
    Publication date: February 7, 2013
    Inventors: Koichi Hirano, Shingo Komatsu, Yasuteru Saito, Naoki Ike
  • Patent number: 8367488
    Abstract: A method includes the steps of preparing a multilayer film 80 formed by sequentially stacking a first metal layer 10, an inorganic insulating layer 20, a semiconductor layer 30, and a second metal layer 40; forming a source electrode 42s and a drain electrode 42d comprised of the second metal layer 40 by etching the second metal layer 40; pressure-bonding a resin layer 50 onto a surface of the multilayer film 80 provided with the source electrode 42s and the drain electrode 42d to burry the source electrode 42s and the drain electrode 42d in the resin layer 50; and forming a gate electrode 10g comprised of the first metal layer 10 by etching the first metal layer 10. The inorganic insulating layer 20g functions as a gate insulating film. The semiconductor layer 30 functions as a channel.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: February 5, 2013
    Assignee: Panasonic Corporation
    Inventors: Takashi Ichiryu, Seiichi Nakatani, Koichi Hirano