Lateral Single Gate Single Channel Transistor With Inverted Structure, I.e., Channel Layer Is Formed After Gate (epo) Patents (Class 257/E21.414)
  • Publication number: 20110068388
    Abstract: An object is to provide a high reliability thin film transistor using an oxide semiconductor layer which has stable electric characteristics. In the thin film transistor in which an oxide semiconductor layer is used, the amount of change in threshold voltage of the thin film transistor before and after a BT test is made to be 2 V or less, preferably 1.5 V or less, more preferably 1 V or less, whereby the semiconductor device which has high reliability and stable electric characteristics can be manufactured. In particular, in a display device which is one embodiment of the semiconductor device, a malfunction such as display unevenness due to change in threshold voltage can be reduced.
    Type: Application
    Filed: September 23, 2010
    Publication date: March 24, 2011
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Takahiro TSUJI, Kunihiko SUZUKI
  • Publication number: 20110068338
    Abstract: A metallic wiring film, which is not exfoliated even when exposed to plasma of hydrogen, is provided. A metallic wiring film is constituted by an adhesion layer in which Al is added to copper and a metallic low-resistance layer which is disposed on the adhesion layer and made of pure copper. When a copper alloy including Al and oxygen are included in the adhesion layer and a source electrode and a drain electrode are formed from it, copper does not precipitate at an interface between the adhesion layer and the silicon layer even when being exposed to the hydrogen plasma, which prevents the occurrence of exfoliation between the adhesion layer and the silicon layer. If the amount of Al increases, since widths of the adhesion layer and the metallic low-resistance layer largely differ after etching, the maximum addition amount for permitting the etching to be performed is the upper limit.
    Type: Application
    Filed: September 14, 2010
    Publication date: March 24, 2011
    Applicant: ULVAC, INC.
    Inventors: Satoru TAKASAWA, Satoru Ishibashi, Tadashi Masuda
  • Publication number: 20110068340
    Abstract: A thin film transistor array panel includes an insulating substrate. A gate line is formed on the insulating substrate and has a gate electrode. A gate insulating layer is formed on the gate line. A semiconductor layer is formed on the gate insulating layer and overlaps the gate electrode. Diffusion barriers are formed on the semiconductor layer and contain nitrogen. A data line crosses the gate line and has a source electrode partially contacting the diffusion barriers and a drain electrode partially contacting the diffusion barriers and facing the source electrode. The drain electrode is on the gate electrode. A pixel electrode is electrically connected to the drain electrode.
    Type: Application
    Filed: January 5, 2010
    Publication date: March 24, 2011
    Inventors: Dong-Hoon Lee, Do-Hyun Kim, Chang-Oh Jeong, O-Sung Seo, Xin-Xing Li
  • Patent number: 7910414
    Abstract: A method of fabricating an array substrate includes sequentially forming a first metal layer, a first inorganic insulating layer and an intrinsic amorphous silicon layer on a substrate, the first metal layer including a first metallic material layer and a second metallic material layer; crystallizing the intrinsic amorphous silicon; forming a gate electrode, a gate line, a gate insulating layer and an active layer; forming an interlayer insulating layer including first and second contact holes respectively exposing both sides of the active layer; forming first and second ohmic contact patterns respectively contacting the both sides of the active layers, a source electrode, a drain electrode, and a data line connecting the source electrode; forming a passivation layer on the source electrode, the drain electrode; and forming a pixel electrode on the passivation layer and contacting the drain electrode.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: March 22, 2011
    Assignee: LG Display Co., Ltd.
    Inventors: Hee-Dong Choi, Sang-Gul Lee, Seong-Moh Seo, Jun-Min Lee, Byung-Chul Ahn
  • Patent number: 7910925
    Abstract: The present invention provides an array substrate and a method for manufacturing the same. The array substrate comprises a substrate and a plurality of gate lines parallel to each other and a plurality of data lines parallel to each other formed on the substrate, the gate lines intersecting the data lines to define a plurality of pixel region arranged in a matrix, each pixel region comprising a thin film transistor, a pixel electrode and a thin film diode. With respect to each pixel region in a row, the pixel electrode is connected with the gate line in the present row through the thin film transistor and is connected with the gate line in a previous row through the thin film diode.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: March 22, 2011
    Assignee: Beijing Boe Optoelectronics Technology Co., Ltd.
    Inventor: Zhilong Peng
  • Publication number: 20110063238
    Abstract: A touch display panel is provided and includes a substrate, a plurality of gate lines, a plurality of data lines, a plurality of data output lines, a plurality of thin film transistors, and a plurality of detection capacitors. The gate lines are disposed on the substrate. The data lines are disposed on the substrate. The data lines and the gate lines define a plurality of pixel regions on the substrate. The data output lines are disposed on the substrate, and each data output line is disposed next to one data line. The thin film transistors are respectively disposed in the pixel regions. Each thin film transistor is electrically connected to the corresponding gate line and the corresponding data line. The detection capacitors are respectively disposed in the pixel regions. Each detection capacitor is electrically connected to the corresponding gate line and the corresponding data line.
    Type: Application
    Filed: September 9, 2010
    Publication date: March 17, 2011
    Applicant: Chimei Innolux Corporation
    Inventors: Chia-Mei LIU, Tsai-Lai CHENG, Wei-Lun LIAO, Guan-Hua YEH, Hong-Gi WU
  • Publication number: 20110065220
    Abstract: The present invention provides a thin film transistor array panel comprising: an insulating substrate; a gate line formed on the insulating substrate and having a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; diffusion barriers formed on the semiconductor and containing nitrogen; a data line crossing the gate line and having a source electrode partially contacting the diffusion barriers; a drain electrode partially contacting the diffusion barriers and facing the source electrode on the gate electrode; and a pixel electrode electrically connected to the drain electrode.
    Type: Application
    Filed: November 22, 2010
    Publication date: March 17, 2011
    Inventors: Je-Hun LEE, Beom-Seok Cho, Chang-Oh Jeong, Joo-Han Kim
  • Publication number: 20110057189
    Abstract: A display device includes a lower panel including a lower substrate and a pixel transistor formed on the lower substrate; and an upper panel facing the lower panel, and including an upper substrate, a sensing transistor formed on the upper substrate, and a readout transistor connected to the sensing transistor and transmitting a signal. The readout transistor includes a first lower gate electrode formed on the upper substrate, a first semiconductor layer formed on the first lower gate electrode and overlaps the first gate electrode, and a first source electrode and a first drain electrode disposed on the first semiconductor layer.
    Type: Application
    Filed: April 16, 2010
    Publication date: March 10, 2011
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ki-Hun JEONG, Byeong-Hoon Cho, Jung-Suk Bang, Sang-Youn Han, Woong-Kwon Kim, Sung-Hoon Yang, Suk Won Jung, Dae-Cheol Kim, Kyung-Sook Jeon, Seung Mi Seo
  • Publication number: 20110059562
    Abstract: An object is to provide a manufacturing method of a microcrystalline semiconductor film with favorable quality over a large-area substrate. After forming a gate insulating film over a gate electrode, in order to improve quality of a microcrystalline semiconductor film formed in an initial stage, glow discharge plasma is generated by supplying high-frequency powers with different frequencies, and a lower part of the film near an interface with the gate insulating film is formed under a first film formation condition, which is low in film formation rate but results in a good quality film. Thereafter, an upper part of the film is deposited under a second film formation condition with higher film formation rate, and further, a buffer layer is stacked on the microcrystalline semiconductor film.
    Type: Application
    Filed: November 12, 2010
    Publication date: March 10, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Sachiaki TEDUKA, Satoshi TORIUMI, Makoto FURUNO, Yasuhiro JINBO, Koji DAIRIKI, Hideaki KUWABARA
  • Patent number: 7902549
    Abstract: The present invention relates to a process for vapor depositing a low dielectric insulating film, a thin film transistor using the same, and a preparation method thereof, and more particularly to a process for vapor deposition of low dielectric insulating film that can significantly improve a vapor deposition speed while maintaining properties of the low dielectric insulating film, thereby solving parasitic capacitance problems to realize a high aperture ratio structure, and can reduce a process time by using silane gas when vapor depositing an insulating film by a CVD or PECVD method to form a protection film for a semiconductor device. The present invention also relates to a thin film transistor using the process and preparation method thereof.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: March 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Hoon Yang, Wan-Shick Hong, Kwan-Wook Jung
  • Patent number: 7902002
    Abstract: When a semi-conductor film is irradiated with conventional pulsed laser light, unevenness, which is called as ridge, is caused on the surface of the semiconductor film. In the case of a top-gate type TFT, element characteristics are changed depending on the ridge. In particular, there is a problem in that variation in the plural thin film transistors electrically connected in parallel with one another. According to the present invention, in manufacturing a circuit including plural thin film transistors, the width LP of a region (not including a microcrystal region) that is melted by irradiating a semiconductor film with light of a continuous wave laser is enlarged, and active layers of a plurality of thin film transistors (that are electrically connected in parallel with one another) are arranged in one region.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: March 8, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Koichiro Tanaka
  • Publication number: 20110049524
    Abstract: Provided is a display device including a thin-film transistor and a capacitor element, the thin-film transistor includes: a first insulating film (IN1) which is formed to cover an area where a gate electrode (GT) is formed; a second insulating film (IN2) which is formed on the first insulating film, the second insulating film having an opening (OP) formed in the area in plan view; a semiconductor layer (SCLt) which is formed on the second insulating film to cross the opening, the semiconductor layer including high concentration areas (CN); a third insulating film (IN3) which is formed on the semiconductor layer to expose apart of each of the high concentration areas; and a pair of electrodes (DT, ST) each having electrical connection to the part; and the capacitor element includes a dielectric film which is formed of the same layer and the same material as the third insulating film.
    Type: Application
    Filed: July 28, 2010
    Publication date: March 3, 2011
    Inventor: Yoshiaki TOYOTA
  • Publication number: 20110049510
    Abstract: An object is to provide a display device with excellent display characteristics, where a pixel circuit and a driver circuit provided over one substrate are formed using transistors which have different structures corresponding to characteristics of the respective circuits. The driver circuit portion includes a driver circuit transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using a metal film, and a channel layer is formed using an oxide semiconductor. The pixel portion includes a pixel transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using an oxide conductor, and a semiconductor layer is formed using an oxide semiconductor. The pixel transistor is formed using a light-transmitting material, and thus, a display device with higher aperture ratio can be manufactured.
    Type: Application
    Filed: August 23, 2010
    Publication date: March 3, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Junichiro SAKATA, Masashi TSUBUKU, Kengo AKIMOTO, Miyuki HOSOBA, Masayuki SAKAKURA, Yoshiaki OIKAWA
  • Patent number: 7897439
    Abstract: An electronic device comprising a thin film transistor (TFT) array and manufacturing methods thereof according to various embodiments. Jet-printed material is deposited on selected partially formed transistors to form completed transistors. Thus, a selected number of the TFTs are connected into the circuit while the remainder of the TFTs are not connected. An electronic read-out of the array identifies the specific array by distinguishing the connected TFTs from the unconnected ones. For a TFT array with n elements there are 2n alternative configurations; therefore, a relatively small number of TFTs can uniquely identify a huge number of devices. Such uniquely encoded devices have applications for encryption, identification and personalization of electronic systems.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: March 1, 2011
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Robert A. Street, Ana Claudia Arias
  • Publication number: 20110042674
    Abstract: A production method of a semiconductor element having a channel includes forming a resist pattern film on a thin film formed on a substrate, and pattering the thin film by etching. The production method also includes forming a second resist pattern film by applying a fluid resist material inside a channel groove after channel etching or inside a resist groove formed above a channel region before channel etching. The production method may also include forming a gate electrode, a gate insulating film, a semiconductor film, and a conductive film on an insulating substrate. The method may include applying the fluid resist material inside the channel groove, thereby forming the second resist pattern film, and patterning the semiconductor film using at least the second resist pattern film.
    Type: Application
    Filed: November 1, 2010
    Publication date: February 24, 2011
    Inventors: Yuichi SAITO, Takeshi Hara
  • Publication number: 20110042677
    Abstract: There is provided a flexible semiconductor device. The flexible semiconductor device of the present invention comprises a metal layer comprising a gate electrode, a source electrode and a drain electrode; a metal oxide film made from a metal which constitutes the metal layer and formed over a surface region of the metal layer; and a semiconductor layer formed above the gate electrode via the metal oxide film. In the flexible semiconductor device, uncovered portions, each of which is not covered with the metal oxide film, are locally formed in the surface region of the metal layer; and also electrical connections are formed between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer via the uncovered portions.
    Type: Application
    Filed: November 13, 2009
    Publication date: February 24, 2011
    Inventors: Takeshi Suzuki, Kenichi Hotehama, Koichi Hirano, Seiichi Nakatani
  • Publication number: 20110037070
    Abstract: A thin film transistor substrate includes a substrate including a display area and a peripheral area surrounding the display area, gate lines formed on the substrate including gate electrodes, an auxiliary insulating layer formed on the gate lines, a gate insulating layer formed on the auxiliary insulating layer and the gate lines, a semiconductor layer formed on the gate insulating layer, data lines formed on the semiconductor layer including source electrodes and drain electrodes, a passivation layer formed on the data lines, pixel electrodes formed on the passivation layer and electrically connected to the drain electrode, wherein the boundary line of the auxiliary insulating layer is located at or within the boundary of the gate line.
    Type: Application
    Filed: June 22, 2010
    Publication date: February 17, 2011
    Inventors: SUNG-RYUL KIM, Hyeong-Suk Yoo, Byeong-Hoo Cho, O-Sung Seo, Seong-Hun Kim
  • Publication number: 20110039362
    Abstract: A method of forming a film pattern with micro-pattern and a method of manufacturing a thin film transistor liquid crystal display (TFT-LCD) array substrate are provided. The method of manufacturing the film pattern with micro-pattern comprises: depositing a thin film on a substrate; jetting or dropping etchant on the thin film with a predetermined etching pattern by an inkjet print device; etching the thin film by the etchant; and cleaning the thin film to form a film pattern on the substrate.
    Type: Application
    Filed: August 13, 2010
    Publication date: February 17, 2011
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Chunping LONG, Haoran GAO, Jigang XU
  • Patent number: 7888683
    Abstract: An organic light emitting display and a method for making the same includes protection circuitry to avoid damage from static electricity. The display and method allow performing a lighting test during display manufacturing. The organic light emitting display includes a substrate, a display region on the transparent substrate with a matrix of pixels, and a signal transfer unit on the transparent substrate for transferring lighting test signals to the pixels. The signal transfer unit includes transistors for transferring the lighting test signals and a resistor coupled to drains and gates of the transistors for protecting the transistors against damage from static electricity.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: February 15, 2011
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Hey-Jin Shin, Won-Kyu Kwak
  • Patent number: 7888148
    Abstract: A thin film panel includes a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, a data line, including a source electrode, and a drain electrode formed on the gate insulating layer or the semiconductor layer, and a pixel electrode connected to the drain electrode, wherein at least one of the gate line and the data line and drain electrode includes a first conductive layer made of a molybdenum Mo-niobium Nb alloy and a second conductive layer made of a copper Cu-containing metal.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: February 15, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Sick Park, Bong-Kyun Kim, Chang-Oh Jeong, Jong-Hyun Choung, Sun-Young Hong, Won-Suk Shin, Byeong-Jin Lee
  • Patent number: 7888674
    Abstract: A thin-film transistor substrate includes a gate line, a capacitor dielectric layer, a gate insulation layer, an active pattern, a data line, a protection layer, and a pixel electrode. The gate wiring including a gate electrode, a lower storage electrode, and a gate metal pad is disposed on a substrate. The capacitor dielectric layer is disposed on the lower storage electrode and the gate insulation layer is disposed on the substrate. The active pattern includes an active layer and a dummy active layer disposed on the gate insulation layer in a gate electrode region and a gate metal pad region, respectively. A portion of the upper storage electrode is disposed on the capacitor dielectric layer exposed through a first contact hole in the gate insulation layer.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: February 15, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong-Kweon Heo, Chun-Gi You
  • Patent number: 7883943
    Abstract: A method for manufacturing a thin film transistor and a display device using a small number of masks is provided. A conductive film is formed, a thin-film stack body having a pattern is formed over the conductive film, an opening portion is formed in the thin-film stack body so as to reach the conductive film, a gate electrode layer is formed by processing the conductive film using side-etching, and an insulating layer, a semiconductor layer, and a source and drain electrode layer are formed over the gate electrode layer, whereby a thin film transistor is manufactured. By provision of the opening portion, controllability of etching is improved.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: February 8, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Takafumi Mizoguchi
  • Publication number: 20110024763
    Abstract: A display device which has thin film transistors, wherein a semiconductor layer includes a first layer, second layers and third layers, the first layer has a channel region, the second layers are an impurity layer, the third layers are a low-concentration impurity layer, the second layers have connection portions connected with an electrodes, the third layers are formed to annularly surround the second layers, a channel-region-side edge portion out of edge portions of the third layer is in contact with the first layer, the edge portions of the third layer but the channel-region-side edge portion are in contact with an interlayer insulation film, the second layers have a first region where the second layer overlaps with a gate electrode and a second region where the second layer does not overlap with the gate electrode, and the connection portion is in the second region.
    Type: Application
    Filed: July 28, 2010
    Publication date: February 3, 2011
    Inventors: Takeshi NODA, Toshio Miyazawa, Takuo Kaitoh, Daisuke Sonoda
  • Patent number: 7880167
    Abstract: An object of the present invention is to provide an EL display device having high operation performance and reliability. A third passivation film 45 is disposed under the EL element 203 comprising a pixel electrode (anode) 46, an EL layer 47 and a cathode 48, and diffusion of alkali metals from the EL element 203 formed by ink jet method into TFTs is prevented. Further, the third passivation film 45 prevents penetration of moisture and oxygen from the TFTs, and suppress degradation of the EL element 203 by dispersing the heat generated by the EL element 203.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: February 1, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kunitaka Yamamoto, Toshimitsu Konuma
  • Patent number: 7879662
    Abstract: A thin film transistor showing desirable contact characteristics during contact with indium tin oxide (ITO) or indium zinc oxide (IZO), in which a first conductive pattern including a gate electrode and a second conductive pattern including a source electrode and a drain electrode are formed without an etching process, a TFT substrate including the TFTs, and a method of manufacturing the same. The thin film transistor includes a gate electrode formed of a first conductive layer, a gate insulating layer covering the gate electrode, a semiconductor layer forming a channel on the gate insulating layer; an ohmic contact layer formed on the semiconductor layer, and a source electrode and a drain electrode formed of a second conductive layer and of a third conductive layer. The second conductive layer includes an aluminum-nickel alloy and nitrogen and is formed on the semiconductor layer. The third conductive layer includes an aluminum-nickel alloy and is formed on the second conductive layer.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: February 1, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yang-Ho Bae, Chang-Oh Jeong, Byeong-Beom Kim
  • Publication number: 20110017993
    Abstract: There is provided a TFT substrate including a gate electrode having a thick film part and a thin film part with a smaller film thickness than the thick film part, a semiconductor active film formed above the thick film part and the thin film part of the gate electrode, an ohmic contact film formed on an inside of the semiconductor active film and on the semiconductor active film corresponding to the thin film part on an outside of the thick film part, and an electrode film constituting a source electrode and a drain electrode, having a planar shape identical to or on an inside of the ohmic contact film, and formed on the ohmic contact film.
    Type: Application
    Filed: July 7, 2010
    Publication date: January 27, 2011
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kumi TSUDA, Kazunori Inoue, Masaru Aoki
  • Publication number: 20110018000
    Abstract: Disclosed is a method of fabricating a display device that includes forming a buffer layer; forming a gate electrode of extrinsic polycrystalline silicon, a gate insulating layer, an active layer of intrinsic polycrystalline silicon and an auxiliary active layer of intrinsic amorphous silicon on the buffer layer; forming an ohmic contact layer of extrinsic amorphous silicon and contacting the auxiliary active layer, source and drain electrodes and a data line; patterning a first passivation layer, an insulating interlayer and the gate insulating layer to form a gate contact hole exposing the gate electrode; forming a gate line on the first passivation layer, made of a metal material, and contacting the gate electrode through the gate contact hole; forming a second passivation layer on the gate line; patterning the first and second passivation layers to form a drain contact hole exposing the drain electrode; and forming a pixel electrode on the second passivation layer in the pixel region and contacting the dr
    Type: Application
    Filed: June 10, 2010
    Publication date: January 27, 2011
    Inventors: Hee-Dong CHOI, Hye-Young Choi, Jun-Min Lee
  • Publication number: 20110007234
    Abstract: A thin film transistor liquid crystal display (TFT-LCD) array substrate comprises a gate line, a data line, a pixel electrode and a thin film transistor. The pixel electrode and the thin film transistor are formed in a pixel region defined by intersecting of the gate line and the data line, and the thin film transistor comprises a gate electrode, a semiconductor layer, a source electrode and a drain electrode. Two separate parts of the surface of the semiconductor layer are treated by a surface treatment to form into an ohmic contact layer, and the source electrode and the drain electrode are connected with the semiconductor layer through the ohmic contact layer in the two separate parts, respectively.
    Type: Application
    Filed: July 13, 2010
    Publication date: January 13, 2011
    Applicant: BEIJING BOE OPTOELECTRONICS TECHONOLOGY CO., LTD.
    Inventors: Xiang Liu, Zhenyu Xie, Xu Chen
  • Patent number: 7867796
    Abstract: A method for fabricating an LCD includes: providing a substrate with a thin film transistor (ITT) part defined thereon; forming a metallic film for a gate electrode on the substrate; etching the metallic film through a first printing process to form a gate electrode; sequentially forming a gate insulating layer, a semiconductor layer, and a metallic film for source and drain electrodes on the substrate; selectively etching the metallic film for source and drain electrodes, the semiconductor layer and the gate insulating layer through a second printing process to form a gate insulating layer pattern, a preliminary active pattern and a metallic film pattern which are sequentially stacked such that the gate insulating layer pattern is over-etched from the side of the preliminary active pattern; forming an insulating layer on the substrate with the metallic film pattern; etching the insulating layer to expose the metallic film pattern; forming a transparent conductive film on the metallic film pattern and a remai
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: January 11, 2011
    Assignee: LG Display Co., Ltd.
    Inventors: Seung-Hee Nam, Nam-Kook Kim, Soon-Sung Yoo, Youn-Gyoung Chang
  • Publication number: 20110003442
    Abstract: A method for making a flexible semiconductor device includes the following steps. A rigid substrate is provided. A flexible substrate is provided, and placed on the rigid substrate. A semiconductor device is directly formed on the flexible substrate using a semiconductor process. After the rigid substrate is removed, the flexible semiconductor device is formed.
    Type: Application
    Filed: May 17, 2010
    Publication date: January 6, 2011
    Applicants: TSINGHUA UNIVERSITY, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: XUE-SHEN WANG, QUN-QING LI
  • Publication number: 20100327281
    Abstract: An object is to provide a thin film transistor with small off current, large on current, and high field-effect mobility. A silicon nitride layer and a silicon oxide layer which is formed by oxidizing the silicon nitride layer are stacked as a gate insulating layer, and crystals grow from an interface of the silicon oxide layer of the gate insulating layer to form a microcrystalline semiconductor layer; thus, an inverted staggered thin film transistor is manufactured. Since crystals grow from the gate insulating layer, the thin film transistor can have a high crystallinity, large on current, and high field-effect mobility. In addition, a buffer layer is provided to reduce off current.
    Type: Application
    Filed: June 22, 2010
    Publication date: December 30, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Miyako NAKAJIMA, Hidekazu MIYAIRI, Toshiyuki ISA, Erika KATO, Mitsuhiro ICHIJO, Kazutaka KURIKI, Tomokazu YOKOI
  • Publication number: 20100327351
    Abstract: An object is to reduce the resistance of each member included in a transistor, to improve ON current of the transistor, and to improve performance of an integrated circuit. A semiconductor device including an n-channel FET and a p-channel FET which are provided over a single crystal semiconductor substrate with an insulating layer provided therebetween and are isolated by an element isolation insulating layer. In the semiconductor device, each FET includes a channel formation region including a semiconductor material, a conductive region which is in contact with the channel formation region and includes the semiconductor material, a metal region in contact with the conductive region, a gate insulating layer in contact with the channel formation region, a gate electrode in contact with the gate insulating layer, and a source or drain electrode partly including the metal region.
    Type: Application
    Filed: June 23, 2010
    Publication date: December 30, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Shunpei YAMAZAKI
  • Patent number: 7858415
    Abstract: The present invention provides production methods of a pattern thin film, a semiconductor element and a circuit substrate, capable of eliminating the number of photolithography processes needed for patterning; and a semiconductor element, a circuit substrate, and an electron device obtained by the production methods. The production method of the pattern thin film of the present invention is a production method of a pattern thin film, comprising the steps of: forming a first resist pattern film on a thin film formed on a substrate; forming a second resist pattern film; patterning the thin film using at least the second resist pattern film, wherein in the step of forming the second resist pattern film, a fluid resist material or an organic solvent is applied on a groove of a bank pattern formed using the first resist pattern film.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: December 28, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yuichi Saito, Takeshi Hara
  • Patent number: 7858412
    Abstract: A thin-film transistor (“TFT”) substrate and a method of fabricating the same include: an insulating substrate; gate wiring which is disposed on the insulating substrate and includes a gate line and a gate electrode; a semiconductor pattern which is disposed on the gate electrode; data wiring which is disposed on the semiconductor pattern and includes a data line, a source electrode, and a drain electrode; a passivation layer which includes a first sub-passivation layer and a second sub-passivation layer deposited on the data wiring; and a pixel electrode which is electrically connected to the drain electrode through a contact hole disposed in the passivation layer, wherein the second sub-passivation layer has a lower density than the first sub-passivation layer.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: December 28, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-Han Kim, Ki-Hun Jeong, Seung-Hwan Shim
  • Patent number: 7858455
    Abstract: A method for manufacturing a semiconductor device and a display device each including a thin film transistor which has excellent electric characteristics and high reliability, with high mass productivity. In a display device which includes a channel-etch inversely-staggered thin film transistor in which a microcrystalline semiconductor layer is used for a channel formation region, the microcrystalline semiconductor layer is formed of a stacked layer of a microcrystalline semiconductor film which is formed by a deposition method and can be a nucleus of crystal growth and an amorphous semiconductor film; a conductive film and a semiconductor film which forms a source region and a drain region and to which an impurity imparting one conductivity is added are formed over the amorphous semiconductor film; and the conductive film is irradiated with laser light.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: December 28, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Publication number: 20100320464
    Abstract: A photo-mask includes a first opaque pattern, a second opaque pattern, a transparent single slit, and a translucent pattern. The transparent single slit is disposed between the first opaque pattern and the second opaque pattern, and the width of the transparent single slit is substantially between 1.5 micrometers and 2.5 micrometers. The translucent pattern is connected to the first opaque pattern and the second opaque pattern.
    Type: Application
    Filed: March 3, 2010
    Publication date: December 23, 2010
    Inventors: Chia-Ming Chang, Hsiang-Chih Hsiao
  • Publication number: 20100320467
    Abstract: Disclosed is a method that includes: forming a gate electrode on a substrate, then forming an insulation layer so as to completely cover the gate electrode, thereafter forming a semiconductor layer on the insulation layer, and then forming a crystallization-inducing metal layer on the semiconductor layer; removing the part of at least the crystallization-inducing metal layer that is over a channel region of the semiconductor layer; forming source and drain electrodes at a location which is over source and drain regions respectively located at opposite sides with respect to the channel region of the semiconductor layer and is above the crystallization-inducing metal layer; and heating the crystallization-inducing metal layer so as to form a silicide layer of a crystallization-inducing metal.
    Type: Application
    Filed: November 14, 2008
    Publication date: December 23, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Takaaki Ukeda, Tohru Saitoh, Kazunori Komori, Sadayoshi Hotta
  • Patent number: 7851803
    Abstract: A semiconductor device includes a substrate and a channel region which is formed above the substrate by printing, wherein a relationship L?2a is satisfied where L is a channel length of the channel region and a is a minimum dimension among pattern dimensions and inter-pattern dimensions in the same layer as patterns that define the channel length L; and a relationship W?2b is satisfied where W is a channel width of the channel region and b is a minimum dimension among pattern dimensions and inter-pattern dimensions in the same layer as a pattern that defines the channel width W.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: December 14, 2010
    Assignee: FUJIFILM Corporation
    Inventors: Atsushi Tanaka, Ken-Ichi Umeda, Kohei Higashi, Maki Nangu
  • Patent number: 7851281
    Abstract: A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: December 14, 2010
    Assignee: Panasonic Corporation
    Inventors: Koichi Hirano, Seiichi Nakatani, Shingo Komatsu, Yoshihisa Yamashita, Takashi Ichiryu
  • Patent number: 7851280
    Abstract: An organic electroluminescent display (“OELD”) includes an organic light-emitting diode (“OLED”), a circuit region, and an interlayer dielectric (“ILD”) layer. The OLED is disposed in each of a plurality of pixels arranged on a substrate. The circuit region includes two or more thin film transistors (“TFTs”) and a storage capacitor. The ILD layer has two or more insulating layers and includes a first region disposed between both electrodes of the storage capacitor and a second region covering the TFTs. At least one of the insulating layers has a window exposing the insulating layer directly beneath the at least one insulating layer so that that the ILD layer is thinner in the first region than in the second region. Accordingly, it is possible to reduce an occupation area of the storage capacitor while maintaining the necessary capacitance of the storage capacitor and expanding the area of the luminescent region.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: December 14, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-sim Jung, Jany-yeon Kwon, Jong-man Kim, Kyung-bae Park, Takashi Noguchi
  • Patent number: 7851802
    Abstract: Example embodiments relate to a poly-crystalline silicon (Si) thin film, a thin film transistor (TFT) formed from a poly-crystalline silicon (Si) thin film and methods of manufacturing the same. The method of manufacturing the poly-crystalline Si thin film includes forming an active layer formed of amorphous Si on a substrate, coating a gold nanorod on the active layer, and irradiating infrared rays onto the gold nanorod to crystallize the active layer.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: December 14, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-bae Park, Seon-mi Yoon, Sang-yoon Lee, Jae-young Choi, Hyeon-jin Shin, Myung-kwan Ryu, Tae-sang Kim, Jang-yeon Kwon, Kyung-seok Son, Ji-sim Jung
  • Publication number: 20100308333
    Abstract: A method of manufacturing a thin film transistor capable of simplifying a substrate structure and a manufacturing process is disclosed. The method of manufacturing a thin film transistor array substrate comprising a three mask process. The 3 mask process comprising, forming a gate pattern on a substrate, forming a gate insulating film on the substrate, forming a source/drain pattern and a semiconductor pattern on the substrate, forming a first, second, and third passivation film successively on the substrate.
    Type: Application
    Filed: September 16, 2009
    Publication date: December 9, 2010
    Inventors: Hyeong-Suk YOO, Ho-Jun LEE, Sung-ryul KIM, O-Sung SEO, Hong-Kee CHIN
  • Patent number: 7846787
    Abstract: A method of manufacturing a transistor and a method of manufacturing an organic electroluminescence display are disclosed. When an amorphous silicon layer is crystallized, a silicon oxide layer formed on a polysilicon layer is subsequently patterned. Impurity ions are implanted into first and second regions of the amorphous silicon layer to form first and second doped regions. The silicon oxide layer is patterned so that the silicon oxide layer may be removed from an ohmic contact region of the polysilicon layer, and covers only a channel region of the polysilicon layer.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: December 7, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyu-Sik Cho, Joon-Hoo Choi
  • Publication number: 20100301346
    Abstract: A thin film transistor in which an effect of photo current is small and an On/Off ratio is high is provided. In a bottom-gate bottom-contact (coplanar) thin film transistor, a channel formation region overlaps with a gate electrode, a first impurity semiconductor layer is provided between the channel formation region and a second impurity semiconductor layer which is in contact with a wiring layer. A semiconductor layer which serves as the channel formation region and the first impurity semiconductor layer preferably overlap with each other in a region where they overlap with the gate electrode. The first impurity semiconductor layer and the second impurity semiconductor layer preferably overlap with each other in a region where they do not overlap with the gate electrode.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 2, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hidekazu MIYAIRI, Yasuhiro JINBO, Hiromichi GODO, Takafumi MIZOGUCHI, Shinobu FURUKAWA
  • Publication number: 20100301345
    Abstract: An array substrate and method for manufacturing the same is provided, wherein a data line is composed of first and second segments connected by a contact pad. First and second insulation layers are disposed between the first segment of the data line and a shielding electrode. In addition, the first insulation layer is disposed between the second segment of the data line and a gate line in their overlapping area. Accordingly, the coupling effect between the conductive layers can be reduced. For example, the RC delay problem due to parasitic capacitance between the shielding electrode and the data line is solved. As a result of the design of the two insulator layers between the first segment of the data line and the shielding electrode, the shorting between the conductive layers can also be simultaneously solved and the product yield can be increased.
    Type: Application
    Filed: November 23, 2009
    Publication date: December 2, 2010
    Applicant: AU OPTRONICS CORP.
    Inventors: Hsiang-Lin Lin, Ching-Huan Lin, Chih-Hung Shih, Wei-Ming Huang
  • Publication number: 20100301339
    Abstract: [Object] To provide a method of producing a thin film transistor superior in productivity and capable of preventing variation in transistor characteristics among devices from occurring to improve carrier mobility, and a thin film transistor. [Solving Means] In a method of producing a thin-film transistor according to the present invention, a solid-state green laser is irradiated onto a channel portion of an amorphous silicon film using a source electrode film and a drain electrode film as masks, thereby improving mobility. Since the channel portion of the amorphous silicon film is crystallized by the irradiation of the solid-state green laser, laser oscillation characteristics can be more stable than in a conventional method that uses an excimer laser. Further, laser irradiation onto a large-size substrate at uniform output characteristics in plane becomes possible, with the result that a variation in crystallinity of channel portions among devices can be avoided.
    Type: Application
    Filed: December 12, 2008
    Publication date: December 2, 2010
    Applicant: ULVAC, INC.
    Inventors: Taro Morimura, Toru Kikuchi, Masanori Hashimoto, Shin Asari, Kazuya Saito, Kyuzo Nakamura
  • Publication number: 20100297817
    Abstract: A method for manufacturing a thin film transistor (TFT) is disclosed. The method is achieved by forming and defining a source and a drain of a thin film transistor through two lithographic processes cycles so that the channel length (L) of the thin film transistor can be reduced to 1.5 to 4.0 ?m. Besides, the Ion current of the thin film transistor is increased as the channel length (L) is decreased. Therefore, the component area of the thin film transistor is decreased as the channel width (W) is decreased. Thus, the aperture ratio of the TFT-LCD can be increased due to the decreased component area of the thin film transistor.
    Type: Application
    Filed: August 3, 2010
    Publication date: November 25, 2010
    Applicant: Au Optronics Corp.
    Inventor: Chang-Wei Liu
  • Publication number: 20100295048
    Abstract: A TFT array substrate comprises an insulator base; a first metal layer on the insulator base, a first portion thereof forming a gate electrode of a TFT; a gate insulating layer overlying the first metal layer and the insulator base; an amorphous silicon layer and a first layer of conductive transparent material both on the gate insulating layer; a doped amorphous silicon layer positioned on the amorphous silicon layer; a second metal layer on the doped amorphous silicon layer and the first layer of conductive transparent material, a first portion thereof forming source and drain electrodes of the TFT; a passivation layer on the second metal layer; and a second layer of conductive transparent material on the passivation layer, a first portion thereof forming a pixel electrode, wherein the first layer of conductive transparent material forms a portion of a common electrode of the array substrate.
    Type: Application
    Filed: July 1, 2009
    Publication date: November 25, 2010
    Inventors: Te-Chen Chung, Chia-Te Liao
  • Patent number: 7838351
    Abstract: A thin film transistor manufacturing method includes the steps of: forming a gate electrode, gate insulating film and amorphous silicon film in succession on an insulating substrate; forming a channel protective film only in the region which will serve as a channel region of the amorphous silicon film; and forming an n-plus silicon film and metal layer on top of the channel protective film and amorphous silicon film in succession. The method further includes the step of patterning the amorphous silicon film and n-plus silicon film to selectively leave the region associated with source and drain electrodes, using the channel protective film as an etching stopper to selectively remove the region of the n-plus silicon film and metal layer associated with the channel region so as to form source and drain regions from the n-plus silicon film and also form source and drain electrodes from the metal layer.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: November 23, 2010
    Assignee: Sony Corporation
    Inventors: Motohiro Toyota, Toshiaki Arai
  • Patent number: 7838884
    Abstract: The present invention provides a display device which can prevent the deterioration of a transparent conductive film attributed to a cell reaction without pushing up a cost of a film forming device. The display device includes a first conductive layer which is formed of a transparent conductive film containing indium oxide as a main component, a conductive background layer which is formed on the first conductive layer, a second conductive layer which is formed of a film containing Al as a main component on the background layer, and a third conductive layer which is formed of the same material as the second conductive layer on the second conductive layer. On an interface between the second conductive layer and the third conductive layer, positions of grain boundaries are arranged discontinuously. Further, the background layer is a film which contains any one of Mo, Ti and Ta as a main component. Still further, the third conductive layer is used as a reflective electrode.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: November 23, 2010
    Assignee: Hitachi Displays, Ltd.
    Inventors: Makoto Kurita, Jun Gotoh