Abstract: A method of manufacturing a thin film transistor and a thin film transistor, the method including sequentially forming a gate insulating layer, an amorphous silicon layer and an insulating layer on an entire top surface of a substrate having a gate electrode; patterning the insulating layer to form an etch stopper; and patterning the amorphous silicon layer to form a semiconductor layer.

Abstract: A display device according to the present invention includes: a planarization layer for insulating between a gate electrode etc. and a data wiring, a drain electrode, or the like of the transistor; and a barrier layer that is formed on an upper surface or lower surface of the planarization layer and at the same time, adapted to suppress diffusion of moisture or degassing components from the planarization layer. The display device adopts a device structure effective in reducing the plasma damage on the planarization layer by devising a positional relationship between the planarization layer and the barrier layer. Also, in combination with a novel structure as a structure for a pixel electrode, effects such as an increase in luminance can be provided as well.

Abstract: A light-blocking layer is formed using a first resist mask, and a base film is formed over the light-blocking layer. A first conductive film, a first insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are sequentially formed over the base film, and first etching is performed on the second conductive film, the impurity semiconductor film, the semiconductor film, and the first insulating film using a second resist mask over the second conductive film. Then, second etching in which side-etching is performed is performed on part of the first conductive film to form a gate electrode layer, and source and drain electrode layers, source and drain region layers, and a semiconductor layer are formed using a third resist mask. The first resist mask and the second resist mask are formed using the same photomask. Thus, a thin film transistor is manufactured.

Abstract: A method of manufacturing a thin film transistor includes sequentially forming a gate and at least one insulation layer on a substrate, forming a source electrode and a drain electrode on the at least one insulation layer, and forming a channel layer formed of a semiconductor on a part of the source electrode and the drain electrode, wherein the gate, the source electrode, and the drain electrode are formed by using a hybrid inkjet printing apparatus.

Abstract: A thin film transistor array panel according to the present invention includes: a gate line formed on a substrate and including a gate electrode; a gate insulating layer formed on the gate electrode; a mold layer formed on the gate insulating layer and having an opening overlapping the gate electrode; a semiconductor layer filled in the opening; a data line formed on the mold layer and including a source electrode contacted with the semiconductor layer; a drain electrode contacted with the semiconductor layer on the mold layer and facing the source electrode; a passivation layer formed on the data line and the drain electrode; and a pixel electrode formed on the passivation layer and connected to the drain electrode, wherein the passivation layer, the source electrode, and the drain electrode have at least one through-hole connected to the opening.

Abstract: A thin film transistor (TFT) array substrate and a manufacturing method thereof are provided. The TFT array substrate may include a gate line disposed on a substrate and including a gate line and a gate electrode, an oxide semiconductor layer pattern disposed on the gate electrode, a data line disposed on the oxide semiconductor layer pattern and including a source electrode and a drain electrode of a thin film transistor (TFT) together with the gate electrode, and a data line extending in a direction intersecting the gate line, and etch stop patterns disposed at an area where the TFT is formed between the source/drain electrodes and the oxide semiconductor layer pattern and at an area where the gate line and the data line overlap each other between the gate line and the data line.

Abstract: A method for manufacturing a liquid crystal display includes simultaneously forming a gate electrode and a gate bus line on a transparent dielectric substrate, simultaneously forming a channel layer, an ohmic contact layer, and source/drain electrodes by forming a gate insulation film, an amorphous silicon film, a doped amorphous silicon film, and a metal film on the transparent dielectric substrate on which the gate electrode and the gate bus line are formed and etching the metal film, the amorphous silicon film, and the doped amorphous silicon film, and forming a pixel electrode by forming a protective film and a transparent metal film on the transparent dielectric substrate upon which the source/drain electrodes are formed and finely etching the transparent metal film through a lift-off process using a stripper solution.

Abstract: A method of fabricating metal oxide TFTs on transparent substrates includes the steps of positioning an opaque gate metal area on the front surface of the substrate, depositing transparent gate dielectric and transparent metal oxide semiconductor layers overlying the gate metal and a surrounding area, depositing transparent passivation material on the semiconductor material, depositing photoresist on the passivation material, exposing and developing the photoresist to remove exposed portions, etching the passivation material to leave a passivation area defining a channel area, depositing transparent conductive material over the passivation area, depositing photoresist over the conductive material, exposing and developing the photoresist to remove unexposed portions, and etching the conductive material to leave source and drain areas on opposed sides of the channel area.

Abstract: A method for a thin film transistor array panel includes forming a gate line and a pixel electrode on a substrate, forming a gate insulating layer covering the gate line, forming a data line including a source electrode and a drain electrode on the gate insulating layer, forming an interlayer insulating layer covering the data line and the drain electrode on the gate insulating layer, forming a first opening in the interlayer insulating layer, forming an organic semiconductor in the first opening, forming a passivation layer on the organic semiconductor and the interlayer insulating layer, and forming a second opening in the interlayer insulating layer to expose the pixel electrode.

Abstract: A flexible display device for improving reliability, and a fabricating method thereof are disclosed. In the method of fabricating the flexible display device, an insulating protective layer is formed at one side of a glass substrate. A display device including a thin film transistor array and a pad part, which is connected to the thin film transistor array, is formed on the insulating protective layer. A flexible substrate is attached on the display device. And the glass substrate is removed.

Abstract: A method for fabricating a pixel structure includes providing a substrate having a pixel area. A first metal layer, a gate insulator and a semiconductor layer are formed on the substrate and patterned by using a first half-tone mask or a gray-tone mask to form a transistor pattern, a lower capacitance pattern and a lower circuit pattern. Next, a dielectric layer and an electrode layer both covering the three patterns are sequentially formed and patterned to expose a part of the lower circuit pattern, a part of the lower capacitance pattern and a source/drain region of the transistor pattern. A second metal layer formed on the electrode layer and the electrode layer are patterned by using a second half-tone mask or the gray-tone mask to form an upper circuit pattern, a source/drain pattern and an upper capacitance pattern. A portion of the electrode layer constructs a pixel electrode.

Abstract: A lateral DMOS-transistor is provided that includes a MOS-diode made of a semi-conductor material of a first type of conductivity, a source-area of a second type of conductivity and a drain-area of a second type of conductivity which is separated from the MOS-diode by a drift region made of a semi-conductor material of a second type of conductivity which is at least partially covered by a dielectric gate layer which also covers the semi-conductor material of the MOS-diode. The dielectric gate-layer comprises a first region of a first thickness and a second region of a second thickness. The first region covers the semi-conductor material of the MOS-diode and the second region is arranged on the drift region. A transition takes place from the first thickness to the second thickness such that an edge area of the drift region which is oriented towards the MOS-diode is arranged below the second area of the gate layer. The invention also relates to a method for the production of these types of DMOS-transistors.

Abstract: A method for manufacturing a thin-film device includes forming a separation layer on a substrate, forming a base insulating layer on the separation layer, forming a thin-film device layer on the base insulating layer, bonding a transfer layer including the base insulating layer and the thin-film device layer to a transfer body with an adhesive, causing intralayer delamination or interfacial delamination in the separation layer, and removing the transfer layer from the substrate. The thin-film device layer includes a first wiring sublayer which is located at the bottom of the thin-film device layer and which is in contact with the base insulating layer, a dielectric sublayer which is in contact with a surface of the first wiring sublayer, a semiconductor sublayer electrically insulated from the first wiring sublayer with the dielectric sublayer, and a second wiring sublayer formed subsequently to the semiconductor sublayer.

Abstract: The present invention relates to a thin film transistor substrate and a method for fabricating the same, which can shorten a process time, prevent a scratch from taking place at an alignment film, and increase black luminance. The thin film transistor substrate includes a thin film transistor formed on a substrate, a protective film formed to flatten a step of the thin film transistor and have an uneven surface with repetitive projected patterns and recessed patterns, a pixel electrode formed on the protective film to maintain an uneven shape of the protective film, and an alignment film formed both on the protective film and the pixel electrode to maintain the uneven shapes of the protective film and the pixel electrode.

Abstract: Disclosed is a thin film transistor including: a gate insulating layer covering a gate electrode; a microcrystalline semiconductor region over the gate insulating layer; a pair of amorphous semiconductor region over the microcrystalline semiconductor; a pair of impurity semiconductor layers over the amorphous semiconductor regions; and wirings over the impurity semiconductor layers. The microcrystalline semiconductor region has a surface having a projection and depression on the gate insulating layer side. The microcrystalline semiconductor region includes a first microcrystalline semiconductor region which is not covered with the amorphous regions and a second microcrystalline semiconductor region which is in contact with the amorphous semiconductor regions. A thickness d1 of the first microcrystalline semiconductor region is smaller than a thickness d2 of the second microcrystalline semiconductor region and d1 is greater than or equal to 30 nm.

Abstract: A thin film transistor substrate and a method of manufacturing the thin film transistor substrate comprises forming a gate line and a data line intersecting each other with a gate insulating layer interposed and defining a pixel area on the substrate, a thin film transistor electrically connected to the gate line and the data line, and a stepped-structure occurring pattern overlapping at least one of the gate line and the data line; forming a passivation layer having a stepped-structure portion formed by the stepped-structure occurring pattern on the substrate; forming a photoresist pattern having a second stepped-structure portion corresponding to the stepped-structure portion on the passivation layer; patterning the passivation layer using the photoresist pattern as a mask; forming a transparent conductive layer on the substrate; and removing the photoresist pattern where the transparent conductive layer is covered by a stripper penetrating through the stepped-structure portion of the photoresist pattern an

Abstract: The present invention discloses a thin film transistor (TFT), a method for manufacturing the TFT, and a display substrate using the TFT that may prevent degradation of the characteristics of an oxide semiconductor contained in the TFT by blocking external light from entering a channel region of the oxide semiconductor.

Abstract: A thin film transistor array panel is provided and includes a gate line, a gate insulating layer covering the gate line, a semiconductor layer disposed on the gate insulating layer, and a data line and a drain electrode disposed on the semiconductor layer. The data line and the drain electrode have a dual-layered structure including a lower layer and an upper layer with the lower layer having a first portion protruded outside the upper layer and the semiconductor layer having a second portion protruded outside the edge of the lower layer.

Abstract: A thin film transistor array substrate and a fabricating method thereof are disclosed. The thin film transistor array substrate protects a thin film transistor without a protective film and accordingly reduces the manufacturing cost. In the thin film transistor array substrate, a gate electrode is connected to a gate line. A source electrode is connected to a data line crossing the gate line to define a pixel area. A drain electrode is opposed to the source electrode with a channel therebetween. A semiconductor layer is in the channel. A pixel electrode in the pixel area contacts the drain electrode over substantially the entire overlapping area between the two. A channel protective film is provided on the semiconductor layer corresponding to the channel to protect the semiconductor layer.

Abstract: A thin film transistor substrate, wherein the moving area of electrons between source and drain electrodes of a thin film transistor (TFT) is minimized, the moving distance of electrons is increased, and the sizes of capacitors defined by a gate electrode together with the respective source and drain electrodes are identical to each other so that an off current generated when the TFT is off can be minimized; a method of manufacturing the thin film transistor substrate; and a mask for manufacturing the thin film transistor substrate. Accordingly, it is possible to minimize an off current induced due to a phenomenon of electron trapping by light.

Abstract: A semiconductor device includes an oxide semiconductor layer including a crystalline region over an insulating surface, a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer over the gate insulating layer in a region overlapping with the crystalline region. The crystalline region includes a crystal whose c-axis is aligned in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

Abstract: A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film.

Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.

Abstract: Disclosed is a method of fabricating a LCD device that includes forming sacrifice layer patterns in a pixel region while forming a gate line, a first storage electrode, and a gate pad on a substrate; sequentially forming a gate insulation film, an amorphous silicon film, an impurity-doped amorphous silicon film, and a source/drain metal film on a substrate, forming a transparent conductive material on the substrate covered with a protection and then patterning the transparent conductive material to form a second storage electrode overlapping the first storage electrode and an electrode pattern having a part overlapping an area of one side edge of the sacrifice layer patterns and the other part formed on the substrate; and simultaneously forming a common electrode and a pixel electrode in the pixel region by performing a lift-off process to remove the sacrifice layer patterns on the substrate where the electrode pattern is formed.

Abstract: A thin film transistor, a display device including the same, and a method of manufacturing the display device, the thin film transistor including a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; a semiconductor layer on the gate insulating layer; and source/drain electrodes electrically connected with the semiconductor layer, wherein the gate electrode has a thickness of about 500 ? to about 1500 ? and the gate insulating layer has a thickness of about 1600 ? to about 2500 ?.

Abstract: A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film.

Abstract: A method for making a semiconductor apparatus including the steps of: forming a laminate structure of an insulating film made of a metal oxide and a semiconductor thin film on a substrate; forming a light absorption layer on top of the laminate structure; and irradiating an energy beam of a wavelength capable of being absorbed by the light absorption layer on the light absorption layer and simultaneously crystallizing the insulating film and the semiconductor thin film by means of heat generated in the light absorption layer.

Abstract: Provided are a display device, a thin-film transistor (TFT) substrate, and a method of fabricating the TFT substrate. The method includes: forming a gate electrode on a pixel region of a substrate; forming a gate insulating film on the gate electrode; forming a semiconductor layer on the gate insulating film to overlap the gate electrode; forming a source electrode and a drain electrode to overlap the semiconductor layer and thus form a channel region; and forming a data insulating film on the source electrode and the drain electrode and patterning the data insulating film such that part of a contact hole formed in the data insulating film overlaps the channel region.

Abstract: A liquid crystal display device including 1st and 2nd substrates. A linearly extending scan electrode and a linearly extending signal electrode are formed on the 1st substrate, wherein the scan electrode extends in a direction crossing an extension direction of the signal electrode. A liquid crystal layer is between the 1st and 2nd substrates, and a pixel electrode is formed on the 1st substrate. The pixel electrode is electrically connected to both the scan and signal electrodes. The pixel electrode is divided into at least two regions such that at least two domains of different liquid crystal orientation directions are defined within a single pixel. A 1st and a 2nd of the at least two regions are not aligned in parallel with either the extension direction of the scan electrode or the extension direction of the signal electrode. The 1st and 2nd regions each include a micro-cutout pattern.

Abstract: A manufacturing method of a thin film transistor (TFT) includes forming a gate electrode including a metal that can be combined with silicon to form silicide on a substrate and forming a gate insulation layer by supplying a gas which includes silicon to the gate electrode at a temperature below about 280° C. The method further includes forming a semiconductor on the gate insulation layer, forming a data line and a drain electrode on the semiconductor and forming a pixel electrode connected to the drain electrode.

Abstract: A method of fabricating an array substrate includes forming a gate line and a gate electrode; forming a gate insulating layer, an intrinsic amorphous silicon layer, an inorganic material insulating layer and a heat transfer layer on the gate line and the gate electrode; irradiating a laser beam onto the heat transfer layer to crystallize the intrinsic amorphous silicon layer into a polycrystalline silicon layer; removing the heat transfer layer; patterning the inorganic insulating material layer using a buffered oxide etchant to form an etch-stopper corresponding to the gate electrode forming an impurity-doped amorphous silicon layer and a metal layer on the etch-stopper and the polycrystalline silicon layer; patterning the metal layer to form a data line, a source electrode and a drain electrode and forming a pixel electrode on the passivation layer.

Abstract: A method of manufacturing a thin film transistor array panel includes forming gate lines including gate electrodes on an insulation substrate; forming a gate insulating layer, semiconductor layer, and etch stop layer on the gate lines; etching and patterning the etch stop and semiconductor layers at the same time using photolithography; ashing and partially removing a photoresist film pattern used in the patterning of the etch stop and semiconductor layers; etching the etch stop layer exposed by removed portions of the photoresist film pattern to form etch stop members; depositing ohmic contact and data metal layers onto the etch stop members, etching the ohmic contact and data metal layers at the same time using photolithography to form data lines having source and drain electrodes, and ohmic contact members below the source and drain electrodes; forming a passivation layer on the data lines and drain electrodes; and forming pixel electrodes on the passivation layer.

Abstract: A method for manufacturing a pixel structure is provided. First, a first mask process is performed to form a patterned first metal layer on a substrate, wherein the patterned first metal layer includes a gate. Next, a second mask process is performed to form a patterned insulating layer and a patterned semiconductor layer over the gate, wherein the patterned insulating layer is disposed on the patterned first metal layer, and the patterned semiconductor layer is disposed on the patterned insulating layer. Then, a third mask process is performed to define a thin film transistor (TFT) and a pixel electrode connected thereto and to form a passivation layer to cover the TFT.

Abstract: An array substrate for a display device includes a gate electrode on a substrate; a gate insulating layer on the gate electrode and having the same plane area and the same plane shape as the gate electrode; an active layer on the gate insulating layer and exposing an edge of the gate insulating layer; an interlayer insulating layer on the active layer and including first and second active contact holes, the first and second active contact holes respectively exposing both sides of the active layers; first and second ohmic contact layers contacting the active layer through the first and second active contact holes, respectively; a source electrode on the first ohmic contact layer; a drain electrode on the second ohmic contact layer; a data line on the interlayer insulating layer and connected to the source electrode; a first passivation layer on the source electrode, the drain electrode and the data line, the first passivation layer, the interlayer insulating layer and the gate insulating layer have a first gat

Abstract: A method of forming a polycrystalline silicon layer, a thin film transistor (TFT), an organic light emitting diode (OLED) display device having the same, and methods of fabricating the same. The method of forming a polycrystalline silicon layer includes providing a substrate, forming a buffer layer on the substrate, forming an amorphous silicon layer on the buffer layer, forming a groove in the amorphous silicon layer, forming a capping layer on the amorphous silicon layer, forming a metal catalyst layer on the capping layer, and annealing the substrate and crystallizing the amorphous silicon layer into a polycrystalline silicon layer.

Abstract: A method of forming a thin-film transistor array substrate is provided. A first mask is used to define a source, a drain and a channel on a substrate. A dielectric layer is formed to cover the source, the drain, the channel and the substrate. A second mask is used to define a patterned photoresist and the dielectric layer. A transparent conductive layer is formed to cover the patterned photoresist and the substrate. A lift-off process is performed to remove the patterned photoresist and a portion of the transparent conductive layer disposed on the patterned photoresist. A third mask is used to define a gate disposed on the dielectric layer.

Abstract: An etchant, a method for fabricating a multi-layered interconnection line using the etchant, and a method for fabricating a thin film transistor (TFT) substrate using the etchant. The etchant for the multi-layered line comprised of molybdenum/copper/molybdenum nitride illustratively includes 10-20 wt % hydrogen peroxide, 1-5 wt % organic acid, a 0.1-1 wt % triazole-based compound, a 0.01-0.5 wt % fluoride compound, and deionized water as the remainder.

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention comprises a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, and a data line formed on the semiconductor layer, wherein the data line comprises a lower data layer, an upper data layer, a data oxide layer, and a buffer layer, wherein the upper data layer and the buffer layer comprise a same material.

Abstract: The invention provides a display device and a method for manufacturing thereof by increasing a material efficiently as well as simplifying steps. Also, the invention provides a technique for forming a pattern such as a wiring, that is used for forming a display device, to have a predetermined shape with an excellent controllability. The method for manufacturing a display device includes the steps of: forming a lyophobic region; selectively irradiating laser beam in the lyophobic region to form a lyophilic region; selectively discharging a composition, that contains a conductive material, in the lyophilic region to form a gate electrode layer; forming a gate insulating layer and a semiconductor layer over the gate electrode layer; discharging a composition containing a conductive material over the semiconductor layer to form a source electrode layer and a drain electrode layer; and forming a pixel electrode layer on the source or drain electrode layer.

Abstract: To realize a semiconductor device including a capacitor element capable of obtaining a sufficient capacitor without reducing an opening ratio, in which a pixel electrode is flattened in order to control a defect in orientation of liquid crystal. A semiconductor device of the present invention includes a light-shielding film formed on the thin film transistor, a capacitor insulating film formed on the light-shielding film, a conductive layer formed on the capacitor insulating film, and a pixel electrode that is formed so as to be electrically connected to the conductive layer, in which a storage capacitor element comprises the light-shielding film, the capacitor insulating film, and the conductive layer, whereby an area of a region serving as the capacitor element can be increased.

Abstract: The present invention relates to a thin film transistor substrate and method for fabricating the same which can secure an alignment margin and reduce the number of mask steps. A thin transistor substrate according to the present invention includes a gate line and a data line crossing each other to define a pixel, a gate metal pattern under the data line, a thin film transistor having a gate electrode, a source electrode and a drain electrode in the pixel, and a pixel electrode connected to the drain electrode of the thin film transistor by a connection electrode, wherein the data line has a plurality of first slits to disconnect the gate metal pattern from the gate line.

Abstract: An array substrate includes a substrate, a gate line on the substrate, a data line crossing the gate line to define a pixel region, a thin film transistor connected to the gate and data lines, a pixel electrode in the pixel region, and a common electrode including first, second, third, fourth and fifth portions, wherein the first and second portions are disposed at both sides of the data line, each of the third and fourth portions is connected to the first and second portions, and the fifth portion is connected to the second portion and is extended into a next pixel region adjacent to the pixel region.

Abstract: A photoresist composition includes an alkali-soluble resin, a dissolution inhibitor including a quinone diazide compound, a first additive including a benzenol compound represented by the following Chemical Formula 1, a second additive including an acrylic copolymer represented by the following Chemical Formula 2 and an organic solvent. Accordingly, heat resistance of a photoresist pattern may be improved, and the photoresist pattern may be readily stripped. As a result, crack formation in the photoresist pattern may be reduced and/or prevented.

Abstract: A display panel having a first region, a second region and a third region is provided. The display panel includes an active device array substrate, an opposite substrate, a display medium between the active device array substrate and the opposite substrate, and spacers arranged between the active device array substrate and the opposite substrate for maintaining a cell gap. The active device array substrate includes an active device array in the first region, a pad in the second region, a driving circuit in the third region, and a first alignment layer covering the first region, the second region and the third region. A thickness of the first alignment layer in the third region corresponding to the driving circuit is increased to be greater than those in the first region and the second region for buffering the pressure applied by the spacers.

Abstract: The present invention relates to a thin-film transistor in a liquid crystal display device and a method of fabricating the same, and the thin-film transistor may be configured by including a first gate electrode formed on an insulating substrate; a first gate insulation film formed on the insulating substrate including the first gate electrode; an active layer formed on the first gate insulation film; source/drain electrodes formed on the active layer and arranged at both sides of the first gate electrode; a second gate insulation film formed on the active layer and the first gate insulation film including the source/drain electrodes and provided with a contact hole for exposing part of the drain electrode; a second gate electrode overlapped with the first gate electrode on the second gate insulation film; and a pixel electrode electrically connected to the drain electrode through the contact hole.

Abstract: A thin film transistor (TFT) and a method of fabricating the same are disclosed. The TFT includes a substrate, a gate electrode disposed over the substrate, a gate insulating layer disposed over the gate electrode, a semiconductor layer disposed over the gate insulating layer and including a polycrystalline silicon (poly-Si) layer, an ohmic contact layer disposed over a predetermined region of the semiconductor layer, an insulating interlayer disposed over substantially an entire surface of the substrate including the ohmic contact layer, and source and drain electrodes electrically connected to the ohmic contact layer through contact holes formed in the interlayer insulating layer. A barrier layer is interposed between the semiconductor layer and the ohmic contact layer. Thus, when an off-current of a bottom-gate-type TFT is controlled, degradation of characteristics due to a leakage current may be prevented using a simple process.

Abstract: A semiconductor device having a pair of impurity doped second semiconductor layers, formed on a first semiconductor layer having a channel formation region therein, an outer edge of the first semiconductor film being at least partly coextensive with an outer edge of the impurity doped second semiconductor layers. The semiconductor device further includes source and drain electrodes formed on the pair of impurity doped second semiconductor layers, wherein the pair of impurity doped second semiconductor layers extend beyond inner sides edges of the source and drain electrodes so that a stepped portion is formed from an upper surface of the source and drain electrodes to a surface of the first semiconductor film.

Abstract: A method for doping polysilicon improves a doping profile during plasma doping and includes forming a silicon layer using two separate operations. After forming a first silicon layer, thermal annealing is performed to crystallize the first silicon layer, such that the uniformity of a doping concentration according to the depth of a layer inside is improved during plasma doping. Additionally, a doping concentration at the interface between a polysilicon layer and a gate oxide layer is increased. A by-product deposition layer is reduced, which is formed on the surface of a polysilicon layer due to the increase of a doping concentration in a polysilicon layer. As a result, the dopant loss, which is caused by the removing and cleansing of an ion implantation barrier used during doping, is reduced.

Abstract: An array structure, which includes a TFT, a passivation layer, a pixel electrode, a first connecting layer and a first spacer is provided. The TFT includes a gate, a source and a drain. The passivation layer overlays the TFT. The pixel electrode is located on the passivation layer. The first connecting layer is located on the pixel electrode and electrically connected to the pixel electrode and the drain. The first spacer is located on the first connecting layer.

Abstract: An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.