Abstract: A nonvolatile memory device includes a channel vertically extending from a substrate and comprising a first region that is doped with first impurities and a second region that is disposed under the first region, a plurality of memory cells and a selection transistor stacked over the substrate along the channel, and a diffusion barrier interposed between the first region and the second region, wherein a density of the first impurities is higher than a density of impurities of the second region.

Abstract: A semiconductor device having a super junction and a method of manufacturing the semiconductor device capable of obtaining a high breakdown voltage are provided, whereby charge balance of the super junction is further accurately controlled in the semiconductor device that is implemented by an N-type pillar and a P-type pillar. The semiconductor device includes a semiconductor substrate; and a blocking layer including a first conductive type pillar and a second conductive type pillar that extend in a vertical direction on the semiconductor substrate and that are alternately arrayed in a horizontal direction, wherein, in the blocking layer, a density profile of a first conductive type dopant may be uniform in the horizontal direction, and the density profile of the first conductive type dopant may vary in the vertical direction.

Abstract: Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; disposing gate material in the gate trench; forming a body in the epitaxial layer; forming a source in the body; forming an active region contact trench that has a varying trench depth; and disposing a contact electrode within the active region contact trench. Forming the active region contact trench includes performing a first etch to form a first contact trench depth associated with a first region, and performing a second etch to form a second contact trench depth associated with a second region. The first contact trench depth is substantially different from the second contact trench depth.

Abstract: Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.

Abstract: A non-volatile memory device includes a channel that extends from a substrate in a vertical direction and includes a first portion including an impurity doped region and a second portion disposed under the first portion; and a plurality of memory cells and a selection transistor that are stacked over the substrate along the channel, where the impurity doped region includes a second impurity doped region that forms a side surface and an upper surface of the first portion and a first impurity doped region that covers the second impurity doped region, and a bandgap energy of the second impurity doped region is lower than a bandgap energy of the first impurity doped region.

Abstract: A trenched power semiconductor device on a lightly doped substrate is provided. Firstly, a plurality of trenches including at least a gate trench and a contact window are formed on the lightly doped substrate. Then, at least two trench-bottom heavily doped regions are formed at the bottoms of the trenches. These trench-bottom heavily doped regions are then expanded to connect with each other by using thermal diffusion process so as to form a conductive path. Afterward, the gate structure and the well are formed above the trench-bottom heavily doped regions, and then a conductive structure is formed in the contact window to electrically connect the trench-bottom heavily doped regions to an electrode.

Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes vertical pillars formed by etching a semiconductor substrate and junction regions which are located among the neighboring vertical pillars and spaced apart from one another in a zigzag pattern. As a result, the semiconductor device easily guarantees an electrical passage between the semiconductor substrate and the vertical pillars, such that it substantially prevents the floating phenomenon from being generated, resulting in the prevention of deterioration of the semiconductor device.

Abstract: A shielded gate trench metal oxide semiconductor filed effect transistor (MOSFET) having high switching speed is disclosed. The inventive shielded gate trench MOSFET includes a shielded electrode spreading resistance placed between a shielded gate electrode and a source metal to enhance the performance of the shielded gate trench MOSFET by adjusting doping concentration of poly-silicon in gate trenches to a target value. Furthermore, high cell density is achieved by employing the inventive shielded gate trench MOSFET without requirement of additional cost.

Abstract: A method for fabricating a super-junction semiconductor power device with reduced Miller capacitance includes the following steps. An N-type substrate is provided and a P-type epitaxial layer is formed on the N-type substrate. At least a trench is formed in the P-type epitaxial layer followed by forming a buffer layer on interior surface in the trench. An N-type dopant layer is filled into the trench and then the N-type dopant layer is etched to form a recessed structure at an upper portion of the trench. A gate oxide layer is formed, and simultaneously, dopants in the N-type dopant layer diffuse into the P-type epitaxial layer, forming an N-type diffusion layer. Finally, a gate conductor is filled into the recessed structure and an N-type source doped region is formed around the gate conductor in the P-type epitaxial layer.

Abstract: A closed cell trench MOSFET structure having a drain region of a first conductivity type, a body of a second conductivity type, a trenched gate, and a plurality of source regions of the first conductivity type is provided. The body is located on the drain region. The trenched gate is located in the body and has at least two stripe portions and a cross portion. A bottom of the stripe portions is located in the drain region and a bottom of the cross portion is in the body. The source regions are located in the body and at least adjacent to the stripe region of the trenched gate.

Abstract: Methods of fabricating three-dimensional semiconductor memory devices including forming a plate stack structure with insulating layers and sacrificial layers stacked alternatingly on a substrate, forming first and second trenches separating the plate stack structure into a plurality of mold structures, the first trench being between the second trenches, forming first vertical insulating separators in the first and second trenches, forming semiconductor patterns penetrating the mold structure and being spaced apart from the first and second trenches, removing the first vertical insulating separator from the second trench to expose the sacrificial layers, removing the sacrificial layers exposed by the second trench to form recess regions partially exposing the semiconductor patterns and the first vertical insulating separator, and forming conductive patterns in the recess regions.

Abstract: A device includes a substrate having a first region and a second region. The first region comprises a first field effect transistor having a horizontal channel region within the substrate, a gate overlying the horizontal channel region, and a first dielectric covering the gate of the first field effect transistor. The second region of the substrate includes a second field effect transistor comprising a first terminal extending through the first dielectric to contact the substrate, a second terminal overlying the first terminal and having a top surface, and a vertical channel region separating the first and second terminals. The second field effect transistor also includes a gate on the first dielectric and adjacent the vertical channel region, the gate having a top surface that is co-planar with the top surface of the second terminal.

Abstract: In one embodiment, the present invention includes a semiconductor power device. The semiconductor power device comprises a trenched gate and a trenched field region. The trenched gate is disposed vertically within a trench in a semiconductor substrate. The trenched field region is disposed vertically within the trench and below the trenched gate. A lower portion of the trenched field region tapers to disperse an electric field.

Abstract: A method for forming a semiconductor device is provided. The method includes providing a wafer-stack having a main horizontal surface, an opposite surface, a buried dielectric layer, a semiconductor wafer extending from the buried dielectric layer to the main horizontal surface, and a handling wafer extending from the buried dielectric layer to the opposite surface; etching a deep vertical trench into the semiconductor wafer at least up to the buried dielectric layer, wherein the buried dielectric layer is used as an etch stop; forming a vertical transistor structure comprising forming a first doped region in the semiconductor wafer; forming a first metallization on the main horizontal surface in ohmic contact with the first doped region; removing the handling wafer to expose the buried dielectric layer; and masked etching of the buried dielectric layer to partly expose the semiconductor wafer on a back surface opposite to the main horizontal surface.

Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.

Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type, disposed on a surface of the first semiconductor region, and having an impurity concentration higher than that of the first semiconductor region; a trench that penetrates the second semiconductor region to reach the first semiconductor region; a first electrode disposed inside the trench via an insulating film; a first recess portion disposed deeper than an upper end of the first electrode, in a surface layer of the second semiconductor region, so as to be in contact with the trench; and a second electrode embedded in the first recess portion.

Abstract: A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: Illustrative embodiments of a vertical tunneling field effect transistor are disclosed which may comprise a semiconductor body including a source region doped with a first dopant type and a pocket region doped with a second dopant type, where the pocket region is formed above the source region. The transistor may also comprise an insulated gate formed above the source and pocket regions, the insulated gate being configured to generate electron tunneling between the source and pocket regions if a voltage is applied to the insulated gate. The transistor may further comprise a lateral tunneling barrier formed to substantially prevent electron tunneling between the source region and a drain region of the semiconductor body, where the drain region is doped with the second dopant type.

Abstract: In accordance with an embodiment, a method of forming a semiconductor structure can include forming a source region of a first conductivity type in a well region of a second conductivity type within a semiconductor region, and forming a first diffusion barrier region disposed between the source region and the well region. The method can include forming a heavy body region of the second conductivity type in the well region and forming a second diffusion bather region having a portion on a side of the heavy body region with a thickness different than a thickness of a portion on a bottom portion of the heavy body region. The method can also include forming a gate electrode, and forming a dielectric insulating the gate electrode from the semiconductor region.

Abstract: A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in the trenches that define the mesa. A second conductive region is formed in the portion of the trenches that define the mesa. The second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region. A first electrical contact is made to the second conductive regions and a second electrical contact to the first conductive region in the shield electrode pickup trenches. One or more Schottky diodes are formed within the mesa.

Abstract: This invention discloses an inverted field-effect-transistor (iT-FET) semiconductor device that includes a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate. The semiconductor power device further comprises a trench-sidewall gate placed on sidewalls at a lower portion of a vertical trench surrounded by a body region encompassing a source region with a low resistivity body-source structure connected to a bottom source electrode and a drain link region disposed on top of said body regions thus constituting a drift region. The drift region is operated with a floating potential said iT-FET device achieving a self-termination.

Abstract: The embodiments of the present disclosure disclose a trench-gate MOSFET device and the method for making the trench-gate MOSFET device. The trench-gate MOSFET device comprises a curving dopant profile formed between the body region and the epitaxial layer so that the portion of the body region under the source metal contact has a smaller vertical thickness than the other portion of the body region. The trench-gate MOSFET device in accordance with the embodiments of the present disclosure has improved UIS capability compared with the traditional trench-gate MOSFET device.

Abstract: An MOSFET includes a silicon carbide substrate, an active layer, a gate oxide film, and a gate electrode. The active layer includes a body region where an inversion layer is formed at a region in contact with the gate oxide film by application of voltage to the gate electrode. The body region includes a low concentration region arranged at a region where an inversion layer is formed, and containing impurities of low concentration, and a high concentration region adjacent to the low concentration region in the carrier mobile direction in the inversion layer, arranged in a region where the inversion layer is formed, and containing impurities higher in concentration than in the low concentration region.

Abstract: A method of fabricating a semiconductor device according to the present invention includes forming a first trench and a second trench by etching the first trench further, in an epitaxial layer formed over a substrate, extending a width of the second trench, forming an oxidize film by oxidizing the extended second trench, and filling an electrode material in the first trench and the second trench including the oxidized film formed therein. The method of fabricating a semiconductor device according to the present invention enables to fabricate a semiconductor device that improves the withstand voltage between a drain and a source and reduce the on-resistance.

Abstract: A semiconductor device including an isolation layer structure including a doped polysilicon layer pattern doped with first and second impurities of first and second conductivity types at lower and upper portions thereof, the doped polysilicon layer pattern being on an inner wall of a first trench on a substrate including an active region in which the first trench is not formed and a field region including the first trench, and an insulation structure filling a remaining portion of the first trench; a gate structure on the active region; a well region at a portion of the active region adjacent to lower portions of the doped polysilicon layer pattern and being doped with third impurities of the second conductivity type; and a source/drain at a portion of the active region adjacent to upper portions of the doped polysilicon layer pattern and being doped with fourth impurities of the first conductivity type.

Abstract: Angled ion implants are utilized to form doped regions in a semiconductor pillar formed in an opening of a mask. The pillar is formed to a height less than the height of the mask. Angled ion implantation can be used to form regions of a semiconductor device such as a body tie region, a halo region, or current terminal extension region of a semiconductor device implemented with the semiconductor pillar.

Abstract: A closed cell trench MOSFET structure having a drain region of a first conductivity type, a body of a second conductivity type, a trenched gate, and a plurality of source regions of the first conductivity type is provided. The body is located on the drain region. The trenched gate is located in the body and has at least two stripe portions and a cross portion. A bottom of the stripe portions is located in the drain region and a bottom of the cross portion is in the body. The source regions are located in the body and at least adjacent to the stripe region of the trenched gate.

Abstract: A method of manufacturing a semiconductor device includes forming a channel region, forming a buffer layer on the channel region, and heat-treating the channel region by using a gas containing halogen atoms.

Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a semiconductor substrate that includes a cell region and a peripheral circuit area. The method for forming the semiconductor includes forming a guard pattern of an insulation material. The guard pattern is located at an edge part between the cell region and the peripheral circuit region and is buried in the semiconductor substrate. As a result, the semiconductor device prevents oxidation of the guard pattern, such that a cell gate oxidation integrity (GOI) failure is improved and an IDD failure is prevented from being generated.

Abstract: A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line.

Abstract: A method for forming a transistor having insulated gate electrodes and insulated shield electrodes within trench regions includes forming dielectric stack overlying a substrate. The dielectric stack includes a first layer of one material overlying the substrate and a second layer of a different material overlying the first layer. Trench regions are formed adjacent to the dielectric stack. After the insulated shield electrodes are formed, the method includes removing the second layer and then forming the insulated gate electrodes. Portions of gate electrode material are removed to form first recessed regions, and spacers are formed within the first recessed regions. Enhancements regions are then formed in the gate electrode material self-aligned to the spacers.

Abstract: A vertical structure non-volatile memory device in which a gate dielectric layer is prevented from protruding toward a substrate; a resistance of a ground selection line (GSL) electrode is reduced so that the non-volatile memory device is highly integrated and has improved reliability, and a method of manufacturing the same are provided. The method includes: sequentially forming a polysilicon layer and an insulating layer on a silicon substrate; forming a gate dielectric layer and a channel layer through the polysilicon layer and the insulating layer, the gate dielectric layer and the channel layer extending in a direction perpendicular to the silicon substrate; forming an opening for exposing the silicon substrate, through the insulating layer and the polysilicon layer; removing the polysilicon layer exposed through the opening, by using a halogen-containing reaction gas at a predetermined temperature; and filling a metallic layer in the space formed by removing the polysilicon layer.

Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

Abstract: A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a corresponding data/bit line. The access transistors have a pillar extending generally upward with a source region formed so as to be in electrical communication with the corresponding data/bit line and a drain region formed generally at an upper portion of the pillar and a surround gate structure substantially completely encompassing the pillar in lateral directions and extending substantially the entire vertical extent of the pillar and word lines extending generally in a second direction and in electrical contact with a corresponding surround gate structure at at least a first surface thereof such that bias voltage applied to a given word line is communicated substantially uniformly in a laterally symmetric extent about the corresponding pillar via the surround gate structure.

Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

Abstract: A vertical thin film transistor and a method for manufacturing the same and a display device including the vertical thin film transistor and a method for manufacturing the same are disclosed. The vertical thin film transistor is applied to a substrate. In the present invention, a gate layer of the vertical thin film transistor is formed to have a plurality of concentric annular structures and the adjacent concentric annular structures are linked. By the concentric annular structures of the gate electrode layer, resistance to stress and an on-state current of the vertical thin film transistor can be increased.

Abstract: To provide a semiconductor device which prevents defects and achieves miniaturization. A projecting portion or a trench (a groove portion) is formed in an insulating layer and a channel formation region of a semiconductor layer is provided in contact with the projecting portion or the trench, so that the channel formation region is extended in a direction perpendicular to a substrate. Thus, miniaturization of the transistor can be achieved and an effective channel length can be extended. In addition, before formation of the semiconductor layer, an upper-end corner portion of the projecting portion or the trench with which the semiconductor layer is in contact is subjected to round chamfering, so that a thin semiconductor layer can be formed with good coverage.

Abstract: The invention discloses a novel MOSFET device and its implementation method, the device comprising: a substrate; a gate stack structure, on either side of which is eliminated a conventional isolation spacer; source/drain regions located in the substrate on opposite sides of the gate stack structure; epitaxially grown metal silicide located on the source/drain regions; characterized in that, the epitaxially grown metal silicide is in direct contact with a channel region controlled by the gate stack structure, thereby eliminating the high resistance region below the conventional isolation spacer. At the same time, the epitaxially grown metal silicide can withstand a second high-temperature annealing used for improving the performance of a high-k gate dielectric material, which further improves the performance of the device.

Abstract: Disclosed herein is a semiconductor device including: a first conductivity type semiconductor base body; a first conductivity type pillar region; second conductivity type pillar regions; element and termination regions provided in the first and second conductivity type pillar regions, transistors being formed in the element region, and no transistors being formed in the termination region; body regions; a gate insulating film; gate electrodes; source regions; and body potential extraction regions, wherein voids are formed in the second conductivity type pillar regions of the termination region.

Abstract: To provide a highly reliable semiconductor device. To provide a semiconductor device which prevents a defect and achieves miniaturization. An oxide semiconductor layer in which the thickness of a region serving as a source region or a drain region is larger than the thickness of a region serving as a channel formation region is formed in contact with an insulating layer including a trench. In a transistor including the oxide semiconductor layer, variation in threshold voltage, degradation of electric characteristics, and shift to normally on can be suppressed and source resistance or drain resistance can be reduced, so that the transistor can have high reliability.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of memory cells arranged in a matrix, a plurality of word lines for selecting a plurality of memory cells, and a plurality of bit lines for selecting a plurality of memory cells. Of the plurality of bit lines, first bit lines and second bit lines are arranged in different layers.

Abstract: A method of fabricating a semiconductor device using a recess channel array is disclosed. A substrate is provided having a first region and a second region, including a first transistor in the first region including a first gate electrode partially filling a trench, and source and drain regions that are formed at both sides of the trench, and covered by a first insulating layer. A first conductive layer is formed on the substrate. A contact hole through which the drain region is exposed is formed by patterning the first conductive layer and the first insulating layer. A contact plug is formed that fills the contact hole. A bit line is formed that is electrically connected to the drain region through the contact plug, and simultaneously a second gate electrode is formed in the second region by patterning the first conductive layer.

Abstract: The present invention refers to a semiconductor device especially a tunneling filed effect transistor (TFET) using narrow bandgap material as the source electrode material. A Semiconductor device which is a tunneling field effect transistor type semiconductor device, in which the source material is characterized as narrow band-gap material; meanwhile, there is a u-groove channel. The narrow band-gap material results in a raise of driving current and the u-groove channel reduced drain leakage current. The TFET disclosed in to present invention has the advantages of low leakage current, high drive current, and high integration density. The static power consumption is also reduced by using the present invention. The integration density is improved as well.

Abstract: In a manufacturing method of a semiconductor device, a trench is defined in a semiconductor substrate, and an adjuster layer having a first conductivity type impurity concentration higher than a drift layer is formed at a portion of the semiconductor substrate adjacent to a bottom wall of the trench. A channel layer is formed by introducing second conductivity type impurities to a portion of the semiconductor substrate adjacent to a sidewall of the trench and between the adjustment layer and a main surface of the semiconductor substrate while restricting the channel layer from extending in a depth direction of the trench by the adjustment layer.

Abstract: A semiconductor device including a first doped region of a first conductivity type, a second doped region of a second conductivity type, a gate, and a dielectric layer is provided. The first doped region is located in a substrate and has a trench. The second doped region is located at the bottom of the trench to separate the first doped region into a source doped region and a drain doped region. A channel region is located between the source doped region and the drain doped region. The gate is located in the trench. The dielectric layer covers the sidewall and the bottom of the trench and separates the gate and the substrate.

Abstract: It is an object to allow an inverter to be made up using a single island-shaped semiconductor, so as to provide a semiconductor device comprising a highly-integrated SGT-based CMOS inverter circuit.

Abstract: Methods and resulting device structures for power trench transistor fabrication, wherein a reachup pillar from the field plate trench is left in place to define the location of a self-aligned contact to the field plate.

Abstract: A semiconductor device includes a step-type recess pattern formed in a substrate, a gate electrode buried in the recess pattern and having a gap disposed between the gate electrode and upper sidewalls of the recess pattern, an insulation layer filling the gap, and a source and drain region formed in a portion of the substrate at two sides of the recess pattern. The semiconductor device is able to secure a required data retention time by suppressing the increase of leakage current caused by the reduction of a design rule.