Abstract: Some embodiments include methods of forming electrical contacts. A row of semiconductor material projections may be formed, with the semiconductor material projections containing repeating components of an array, and with a terminal semiconductor projection of the row comprising a contact location. An electrically conductive line may be along said row, with the line wrapping around an end of said terminal semiconductor projection and bifurcating into two branches that are along opposing sides of the semiconductor material projections. Some of the semiconductor material of the terminal semiconductor projection may be replaced with dielectric material, and then an opening may be extended into the dielectric material. An electrical contact may be formed within the opening and directly against at least one of the branches. Some embodiments include memory arrays.

Abstract: The present invention is related to a depletion or enhancement mode metal transistor in which the channel regions of a transistor device comprises a thin film metal or metal composite layer formed over an insulating substrate.

Abstract: A semiconductor device having integrated MOSFET and Schottky diode includes a substrate having a MOSFET region and a Schottky diode region defined thereon; a plurality of first trenches formed in the MOSFET region; and a plurality of second trenches formed in the Schottky diode region. The first trenches respectively including a first insulating layer formed over the sidewalls and bottom of the first trench and a first conductive layer filling the first trench serve as a trenched gate of the trench MOSFET. The second trenches respectively include a second insulating layer formed over the sidewalls and bottom of the second trench and a second conductive layer filling the second trench. A depth and a width of the second trenches are larger than that of the first trenches; and a thickness of the second insulating layer is larger than that of the first insulating layer.

Abstract: The method includes the steps of: forming a planar semiconductor layer on an oxide film formed on a substrate and then forming a pillar-shaped first-conductive-type semiconductor layer on the planar semiconductor layer; forming a second-conductive-type semiconductor layer in a portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode made of a metal, around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode; forming a sidewall-shaped dielectric film on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer.

Abstract: According to one embodiment, in a semiconductor device, a first semiconductor layer of a first conductivity type has a first impurity concentration. A second semiconductor layer of the first conductivity type is formed on the first semiconductor layer and has a second impurity concentration lower than the first impurity concentration. A field plate electrode is formed in a lower portion of a trench formed in the second semiconductor layer through a first insulating film so as to bury the lower portion of the trench. A second insulating film is formed in the upper portion of the trench so as to be in contact with the top surface of the field plate electrode. A gate electrode is formed in the upper portion of the trench through a gate insulating film so as to bury the upper portion of the trench to sandwich the second insulating film.

Abstract: In one embodiment a method of forming a compressive polycrystalline semiconductive material layer is disclosed. The method comprises forming a polycrystalline semiconductive seed layer over a substrate and forming a silicon layer by depositing silicon directly on the polycrystalline silicon seed layer under amorphous process conditions at a temperature below 600 C.

Abstract: In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.

Abstract: A semiconductor device includes: a semiconductor substrate configured to include a plurality of trenches therein; a plurality of buried bit lines each configured to fill a portion of each trench; a plurality of active pillars each formed in an upper portion of each buried bit line; a plurality of vertical gates each configured to surround each active pillar; and a plurality of word lines configured to couple neighboring vertical gates with each other.

Abstract: A trench MOSFET structure with ultra high cell density is disclosed, wherein the source regions and the body regions are located in different regions to save the mesa area between every two adjacent gate trenches in the active area. Furthermore, the inventive trench MOSFET is composed of stripe cells to further increase cell packing density and decrease on resistance Rds between the drain region and the source region.

Abstract: A method of producing a semiconductor device including a MOS transistor, includes the steps of forming, on a top surface of at least one of semiconductor pillars, an epitaxial layer having a top surface larger in area than the top surface of the at least one of the semiconductor pillars and forming a source region or a drain region so as to be at least partially in the epitaxial layer.

Abstract: A method and structure implant a first-type impurity within a substrate to form a channel region within the substrate adjacent a top surface of the substrate; form a gate stack on the top surface of the substrate above the channel region; and implant a second-type impurity within the substrate to form source and drain regions within the substrate adjacent the top surface. The channel region is positioned between the source and drain regions. The second-type impurity has an opposite polarity with respect to the first-type impurity. The method and structure implant a greater concentration of the first-type impurity, relative to a concentration of the first-type impurity within the channel region, to form a primary body doping region within the substrate below (relative to the top surface) the channel region; and to form secondary body doping regions within the substrate below (relative to the top surface) the source and drain regions.

Abstract: In a SiC-based MISFET and a manufacturing process thereof, after the introduction of an impurity, extremely-high-temperature activation annealing is required. Accordingly, it is difficult to frequently use a self-alignment process as performed in a silicon-based MISFET manufacturing process. This results in the problem that, to control the characteristics of a device, a high-accuracy alignment technique is indispensable. In accordance with the present invention, in a semiconductor device such as a SiC-based vertical power MISFET using a silicon-carbide-based semiconductor substrate and a manufacturing method thereof, a channel region, a source region, and a gate structure are formed in mutually self-aligned relation.

Abstract: A semiconductor device includes a semiconductor substrate in which a first trench is formed and a second trench is formed at the middle portions of the first trench; and a first ion implantation layer that is formed on the surface of the semiconductor substrate and on the bottom of the first trench, the portions formed on the bottom of the first trench being spaced from each other by the second trench. A gate is formed from the bottom of the both side walls of the first trench to the middle portions thereof; a drift region is formed at both side walls of the first trench over the second trench; and a second ion implantation layer formed on the inner surface of the second trench.

Abstract: A semiconductor device and its method of fabrication are described. A trench formed in a semiconductor substrate is partially filling said trench with a semiconductor material that lines a bottom and sides of the trench, leaving a gap in a middle of the trench running lengthwise along the trench. A first portion of the semiconductor material located below the gap is doped with dopants of a first conductivity type. The gap is filled with a dielectric material. Second portions of the semiconductor material located on the sides of the trench on both sides of the dielectric material are doped with dopants of a second conductivity type. The doping forms a P—N—P or N—P—N structure running lengthwise along the trench with differently doped regions located side by side across a width of the trench.

Abstract: A method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing raised source/drain regions on the source/drain regions, the grown raised source/drain regions including III-V semiconductor material, and growing metal contacts on the grown raised source/drain regions. Another method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing metal contacts on the source/drain regions.

Abstract: A recessed gate FET device includes a substrate having an upper and lower portions, the lower portion having a reduced concentration of dopant material than the upper portion; a trench-type gate electrode defining a surrounding channel region and having a gate dielectric material layer lining and including a conductive material having a top surface recessed to reduce overlap capacitance with respect to the source and drain diffusion regions formed at an upper substrate surface at either side of the gate electrode. There is optionally formed halo implants at either side of and abutting the gate electrode, each halo implants extending below the source and drain diffusions into the channel region. Additionally, highly doped source and drain extension regions are formed that provide a low resistance path from the source and drain diffusion regions to the channel region.

Abstract: A semiconductor device includes a drift region, a well region extending above the drift region, an active trench including sidewalls and a bottom, the active trench extending through the well region and into the drift region and having at least portions of its sidewalls and bottom lined with dielectric material. The device further includes a shield disposed within the active trench and separated from the sidewalls of the active trench by the dielectric material, a gate disposed within the active trench above the first shield and separated therefrom by inter-electrode dielectric material, and source regions formed in the well region adjacent the active trench. The gate is separated from the sidewalls of the active trench by the dielectric material. The shield and the gate are made of materials having different work functions.

Abstract: Trench portions (10) are formed in a well (5) in order to provide unevenness in the well (5). A gate electrode (2) is formed via an insulating film (7) on the upper surface and inside of the trench portions (10). A source region (3) is formed on one side of the gate electrode (2) in a gate length direction while a drain region (4) on another side. Both of the source region (3) and the drain region (4) are formed down to near the bottom portion of the gate electrode (2). By deeply forming the source region (3) and the drain region (4), current uniformly flows through the whole trench portions (10), and the unevenness formed in the well (5) increase the effective gate width to decrease the on-resistance of a semiconductor device 1 and to enhance the drivability thereof.

Abstract: A semiconductor device includes a step-type recess pattern formed in a substrate, a gate electrode buried in the recess pattern and having a gap disposed between the gate electrode and upper sidewalls of the recess pattern, an insulation layer filling the gap, and a source and drain region formed in a portion of the substrate at two sides of the recess pattern. The semiconductor device is able to secure a required data retention time by suppressing the increase of leakage current caused by the reduction of a design rule.

Abstract: Disclosed are semiconductor devices with breakdown voltages that are more controlled and stable after repeated exposure to breakdown conditions than prior art devices. The disclosed devices can be used to provide secondary circuit functions not previously contemplated by the prior art.

Abstract: This invention discloses an inverted field-effect-transistor (iT-FET) semiconductor device that includes a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate. The semiconductor power device further comprises a trench-sidewall gate placed on sidewalls at a lower portion of a vertical trench surrounded by a body region encompassing a source region with a low resistivity body-source structure connected to a bottom source electrode and a drain link region disposed on top of said body regions thus constituting a drift region. The drift region is operated with a floating potential said iT-FET device achieving a self-termination.

Abstract: A 3D stacked AND-type flash memory structure comprises several horizontal planes of memory cells arranged in a three-dimensional array, and each horizontal plane comprising several word lines and several of charge trapping multilayers arranged alternately, and the adjacent word lines spaced apart from each other with each charge trapping multilayer interposed between; a plurality of sets of bit lines and source lines arranged alternately and disposed vertically to the horizontal planes; and a plurality of sets of channels and sets of insulation pillars arranged alternatively, and disposed perpendicularly to the horizontal planes, wherein one set of channels is sandwiched between the adjacent sets of bit lines and source lines.

Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device, includes forming a stacked body on a substrate by alternately stacking a first insulating film and a second insulating film, making a through-hole extending in a stacking direction of the first insulating film and the second insulating film to pierce the stacked body, forming at least a portion of a blocking insulating film, a charge trap film, and a tunneling dielectric film of a MONOS on an inner surface of the through-hole, forming a channel semiconductor on the tunneling dielectric film, making a trench in the stacked body, removing the second insulating film by performing etching via the trench, and filling a conductive material into a space made by the removing of the second insulating film.

Abstract: A vertical channel transistor array includes a plurality of embedded bit lines, a plurality of bit line contacts, a plurality of embedded word lines, and a current leakage isolation structure. An active area of a vertical channel transistor is defined by the semiconductor pillars. The embedded bit lines are disposed in parallel in a semiconductor substrate and extended in a column direction. Each of the bit line contacts is respectively disposed at a side of one of the embedded bit lines. The embedded word lines are disposed in parallel above the embedded bit lines and extended in a row direction. Besides, the embedded word lines and the semiconductor pillars in the same row are connected but spaced by a gate dielectric layer. The current leakage isolation structure is disposed at ends of the embedded bit lines to prevent current leakage between the adjacent bit line contacts.

Abstract: A method for forming a stressed channel field effect transistor (FET) with source/drain buffers includes etching cavities in a substrate on either side of a gate stack located on the substrate; depositing source/drain buffer material in the cavities; etching the source/drain buffer material to form vertical source/drain buffers adjacent to a channel region of the FET; and depositing source/drain stressor material in the cavities adjacent to and over the vertical source/drain buffers.

Abstract: An insulated-gate field-effect transistor (100) provided along an upper surface of a semiconductor body contains a pair of source/drain zones (240 and 242) laterally separated by a channel zone (244). A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. Each source/drain zone includes a main portion (240M or 242M) and a more lightly doped lateral extension (240E or 242E) laterally continuous with the main portion and extending laterally under the gate electrode. The lateral extensions, which terminate the channel zone along the upper semiconductor surface, are respectively largely defined by a pair of semiconductor dopants of different atomic weights. With the transistor being an asymmetric device, the source/drain zones constitute a source and a drain. The lateral extension of the source is then more lightly doped than, and defined with dopant of higher atomic weight, than the lateral extension of the drain.

Abstract: A method of producing a semiconductor device according to the present invention includes: a step of implanting an impurity into a semiconductor layer 2 by using a first implantation mask layer 30, thereby forming a body region 6; a step of implanting an impurity by using the first implantation mask layer 30 and a second implantation mask layer 31, thereby forming a contact region 7 within the body region 6; a step of forming a third implantation mask layer 32, and thereafter selectively removing the second implantation mask layer 31; a step of forming a side wall 34 on a side face of the first implantation mask layer 30; and a step of implanting an impurity to form a source region 8 within the body region 6.

Abstract: A method and structures are provided for implementing vertical transistors utilizing wire vias as gate nodes. The vertical transistors are high performance transistors fabricated up in the stack between the planes of the global signal routing wire, for example, used as vertical signal repeater transistors. An existing via or a supplemental vertical via between wire planes provides both an electrical connection and the gate node of the novel vertical transistor.

Abstract: A method of forming an accumulation-mode field effect transistor includes forming a channel region of a first conductivity type in a semiconductor region of the first conductivity type. The channel region may extend from a top surface of the semiconductor region to a first depth within the semiconductor region. The method also includes forming gate trenches in the semiconductor region. The gate trenches may extend from the top surface of the semiconductor region to a second depth within the semiconductor region below the first depth. The method also includes forming a first plurality of silicon regions of a second conductivity type in the semiconductor region such that the first plurality of silicon regions form P-N junctions with the channel region along vertical walls of the first plurality of silicon regions.

Abstract: A method of forming a semiconductor device comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate, forming a first region of the first conductivity type in the semiconductor layer, and forming a control region over the semiconductor layer and over part of the first region. A mask layer is formed over the semiconductor layer and outlines a first portion of a surface of the semiconductor layer over part of the first region. Semiconductor material of a second conductivity type is provided to the outlined first portion to provide a second region in the semiconductor layer.

Abstract: A fabrication method of trenched metal-oxide-semiconductor device is provided. A pattern layer with a plurality of openings is formed on a semiconductor base, and then a spacer is formed on the sidewall of the opening to define the gate trench. After the gate electrode formed in the gate trench, a dielectric structure is formed on the gate electrode by filling dielectric material into the opening. Then, the pattern layer and the spacer are removed and a dielectric layer is formed on the dielectric structure. The portion of the dielectric layer on the sidewall of the dielectric structure defines the source regions. After the source regions are formed in the well, another dielectric layer is formed on the dielectric layer to define the heavily doped regions adjacent to the source regions.

Abstract: A field-effect transistor involves a drain electrode, a drift region, a body region, a source region, a gate insulator layer, and a gate electrode. The drift region is disposed above the drain electrode. The body region extends down into the drift region from a first upper semiconductor surface. The source region is ladder-shaped and extends down in the body region from a second upper semiconductor surface. The first and second upper semiconductor surfaces are substantially planar and are not coplanar. A first portion of the body region is surrounded laterally by a second portion of the body region. The second portion of the body region and the drift region meet at a body-to-drift boundary. The body-to-drift boundary has a central portion that is non-planar. A gate insulator layer is disposed over the source region and a gate electrode is disposed over the gate insulator.

Abstract: A non-volatile memory device including a memory string including a plurality of memory cells coupled in series. The non-volatile memory device includes the memory string including a first semiconductor layer and a second conductive layer with a memory gate insulation layer therebetween, a first selection transistor comprising a second semiconductor layer coupled with one end of the first semiconductor layer, a second selection transistor comprising a third semiconductor layer coupled with the other end of the first semiconductor layer, and a fourth semiconductor layer contacting the first semiconductor layer in a region where the second conductive layer is not disposed.

Abstract: A method is disclosed of manufacturing a vertical transistor which comprises providing a substrate including a vertical stack of regions including a source region separated from a drain region by a channel region; forming a trench in said substrate, said trench at least partially extending into said vertical stack of regions; lining said trench with a stack comprising a gate dielectric liner, an etch protection layer and a further insulating layer; filling the remainder of the trench with a shield electrode material; exposing a top portion of the shield electrode material by removing the further insulating layer to a first depth in said trench; forming a inter electrode dielectric on the exposed shield electrode material; removing the etch protection layer to the first depth from said trench; and forming a gate electrode in said trench between the inter electrode dielectric liner and the exposed portion of the gate dielectric liner.

Abstract: The invention provides a method for forming a transistor, which includes: providing a substrate, a semiconductor layer being formed on the substrate; forming a dummy gate structure on the semiconductor layer; forming a source region and a drain region in the substrate and the semiconductor layer and at opposite sides of the dummy gate structure; forming an interlayer dielectric layer on the semiconductor layer; removing the dummy gate structure for forming an opening in the interlayer dielectric layer; non-crystallizing the semiconductor layer exposed in the opening for forming a channel layer; annealing the channel layer so that the channel layer and the substrate have same crystal orientation; and forming a metal gate structure in the opening, the metal gate being formed on the channel layer. Saturation current of the transistor is raised, and the performance of a semiconductor device is promoted.

Abstract: A nonvolatile memory device includes a channel protruding in a vertical direction from a substrate, a plurality of interlayer dielectric layers and gate electrode layers which are alternately stacked over the substrate along the channel, and a memory layer formed between the channel and a stacked structure of the interlayer dielectric layers and gate electrode layers. Two or more gate electrode layers of the plurality of gate electrode layers are coupled to an interconnection line to form a selection transistor.

Abstract: A memory structure having a floating body is provided, which includes a substrate including an active area and an isolation structure surrounding the active area, a first source/drain region in the substrate in the active area, a first floating body in the substrate above the first source/drain region, a second floating body on the first floating body, a second source/drain region on the second floating body, and a trench-type gate structure in the substrate and beside the first floating body. A method of fabricating a memory structure having a floating body is also provided.

Abstract: A novel semiconductor power transistor is presented. The semiconductor structure is simple and is based on a multi-gate vertical MOS configuration with multi semiconductor pillars, so that the control on the carrier transport is enhanced and the specific on-resistance per area is reduced. Furthermore, due to its particular geometry, the parasitic resistances due to the source/drain junctions, are also drastically reduced with respect to standard CMOS technologies. It offers the advantage of extremely lower on-resistance for the same silicon area while improving on its dynamic performances. The novel structure does not require Silicon On Insulator technologies and can be built using the standard Bulk CMOS process technology. This characteristic improves the thermal properties of the device which are extremely important in power applications.

Abstract: In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor.

Abstract: A double-gate vertical channel transistor (DGVC) structure is described which is particularly well suited for Dynamic RAM (DRAM) memory (e.g., capacitorless DRAM) wherein the memory cell occupies a small cell area of 4F2, and provides beneficial retention properties including immunity to disturbances. The vertical transistors are arranged in an alternating gate-facing orientation, with a common source formed on a first end and separate drains on their second ends. Word lines comprise alternating front gates and back gates shared by columns of gate-facing transistors on each side of it. The DGVC cell provides enhanced scalability allowing the continued scaling of DRAM technology and can be fabricated using low-cost semiconductor materials and existing fabrication techniques. Fabrication techniques and array biasing are also described for the DGVC cell arrays.

Abstract: An SiC semiconductor device includes a substrate, a drift layer, a base region, a source region, a trench, a gate oxide film, a gate electrode, a source electrode and a drain electrode. The substrate has a Si-face as a main surface. The source region has the Si-face. The trench is provided from a surface of the source region to a portion deeper than the base region and extends longitudinally in one direction and has a Si-face bottom. The trench has an inverse tapered shape, which has a smaller width at an entrance portion than at a bottom, at least at a portion that is in contact with the base region.

Abstract: In a first method for manufacturing a semiconductor device, an opening is formed in a substrate. A tungsten film is formed on the substrate so as to fill up inside the opening, and then the tungsten film is annealed. The tungsten film is etched back so that the tungsten film remains inside the opening. In a second method for manufacturing a semiconductor device, a laminate body comprising a tungsten film and an insulating film on the tungsten film is formed on a substrate. The laminate body is annealed, and then the laminate body is etched back.

Abstract: The present invention includes a semiconductor substrate, a gate electrode which is provided on the semiconductor substrate, a source electrode and a drain elect rode which are provided on the semiconductor substrate to sandwich the gate electrode, and a recess provided below edges of the gate electrode at least on a drain electrode side.

Abstract: A method of processing a semiconductor structure may include preparing a vertical channel memory structure for filling of a physical isolation trench formed therein. The physical isolation trench may be formed between active structures adjacent to each other and extending in a first direction. The active structures may have channels adjacent to sides of the active structures that are opposite to sides of the active structures that are adjacent to the physical isolation trench. The method may further include filling the physical isolation trench in connection with application of a multi-dielectric layer (ex. an oxide-nitride-oxide (ONO) layer), a polysilicon liner and/or an oxide film. A corresponding apparatus and method for integrating such a structure with a planar periphery are also provided.

Abstract: A vertical channel transistor includes a plurality of active pillar patterns extending perpendicularly from the top surface of the substrate toward an upper part. A gate insulating layer is deposited on the side wall of the active pillar pattern and serves as an ion diffusion barrier between the pillar patterns and surrounding lower gate electrodes. The resultant pillar pattern structure is encapsulated with a metal. The resultant pillar pattern is surrounded on all sides by a specified height by a sacrificial layer of Spin-On Dielectric (SOD). The metal layer is etched-back to the height of the sacrificial layer, thus forming the lower gate electrodes. A spacer layer of an insulating mater is deposited surrounding the upper part of the pillar patterns and the sacrificial layer is removed exposing a part of the lower gate electrodes. The exposed gate electrode is etched to facilitate semiconductor integration.

Abstract: In a method of forming an asymmetric recess, an asymmetric recessed gate structure filling the asymmetric recess, a method of forming the asymmetric recessed gate structure, a semiconductor device having the asymmetric recessed gate structure and a method of manufacturing the semiconductor device, a semiconductor substrate is etched to form a first sub-recess having a first central axis. A second sub-recess is formed under the first sub-recess. The second sub-recess is in communication with the first sub-recess. The second sub-recess has a second central axis substantially parallel with the first central axis. The second central axis is spaced apart from the first central axis.

Abstract: Methods of fabricating semiconductor devices may include forming first trenches in a substrate to define fin patterns and forming buried dielectric patterns filling lower regions of the first trenches. The first trenches extend in parallel. A gate dielectric layer is formed on upper inner sidewalls of the first trenches, and a gate conductive layer filling the first trenches is formed on the substrate including the gate dielectric layer. The gate conductive layer, the gate dielectric layer and the fin patterns are patterned to form second trenches crossing the first trenches and defining active pillars. Semiconductor devices may also be provided.

Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device prevents separation between the channel region and the semiconductor substrate to prevent the floating body effect and to guarantee a sufficient overlap between a gate and a junction region. The semiconductor device includes a vertical pillar including a vertical channel, a diffusion control layer contained in the vertical pillar, and a junction region formed close to the diffusion control layer in the vertical pillar.

Abstract: A SiC MISFET, in which a source region and a drain region (3, 4) are formed in a one-conductivity-type SiC semiconductor region (2), in which a recess (5) with a predetermined depth is formed in a portion of the SiC semiconductor region sandwiched between the source and drain regions, with the recess having two side faces in contact with the source and drain regions, and a bottom face connecting the two side faces, and in which portions (3a, 4a) of the source and drain regions adjacent to the vicinity of both ends of the bottom face of the recess are thinner than other portions.

Abstract: A semiconductor device 100 includes: a silicon carbide layer 102; a source region 104 of a first conductivity type disposed in the silicon carbide layer; a body region 103 of a second conductivity type disposed at a position in contact with the source region 104 in the silicon carbide layer; a contact region 105 of the second conductivity type formed in the body region; a drift region 102d of the first conductivity type disposed in the silicon carbide layer; and a source electrode 109 in ohmic contact with the source region 104 and the contact region 105, wherein: a side wall of the source electrode 109 is in contact with the source region 104; a lower surface of the source electrode 109 is in contact with the contact region 105 and is not in contact with the source region 104; and at least a portion of the source region 104 overlaps the contact region 105 as viewed from a direction perpendicular to a principle surface of a substrate 101.