Producing Ion Implantation (epo) Patents (Class 257/E21.473)
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Publication number: 20120153295Abstract: Radiation detector. The detector includes an ionic junction having an ionically bonded wide band gap material having a first region dominated by positively charged ionic defects in intimate contact with a second region dominated by negatively charged ionic defects forming depleted regions on both sides of the junction resulting in a built-in electric field. The detector also includes an ionic junction having a first ionically bonded wide band gap material dominated by positively charged ionic defects in intimate contact with a second ionically bonded wide band gap material dominated by negatively charged ionic defects forming depleted regions on both sides of the junction resulting in a built-in electric field. Circuit means are provided to establish a voltage across the junction so that radiation impinging upon the junction will cause a current to flow in the circuit.Type: ApplicationFiled: February 25, 2011Publication date: June 21, 2012Applicant: Massachusetts Institute of TechnologyInventors: Harry L. Tuller, Sean R. Bishop
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Patent number: 8198659Abstract: A semiconductor device and a method of manufacturing a semiconductor device. A method of manufacturing a semiconductor device may include forming a gate electrode over a semiconductor substrate, a second conductive type ion implantation region at opposite sides of a gate electrode, a second conductive type ion implantation region as a first conductive type second ion implantation region by implanting a first conductive type impurity over opposite sides of said gate electrode, and/or forming a first conductive type first ion implantation region that substantially surrounds a first conductive type second ion implantation region. A method of manufacturing a semiconductor device may form an N type MOSFET and/or a P type MOSFET using a single photolithography process for each N+ source/drain photolithography process and/or P+ source/drain photolithography process.Type: GrantFiled: November 18, 2009Date of Patent: June 12, 2012Assignee: Dongbu HiTek Co., Ltd.Inventor: Kyung-Wook Kwon
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Publication number: 20120137971Abstract: A template used for printing is implanted to change the properties of the materials it is composed of. This template may have multiple surfaces that define indentations. The ion species that is implanted may be C, N, H, F, He, Ar, B, As, P, Ge, Ga, Si, Zn, and Al and is configured to render the implanted regions hydrophobic in one instance. This will reduce adhesion of a polymer to the template during a printing process. The implant may be at a plurality of angles so all surfaces of the template are implanted. In other instances, a film on the surface of the template is knocked in or hardened using the ion species.Type: ApplicationFiled: December 20, 2010Publication date: June 7, 2012Applicant: VANRIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Patrick M. MARTIN, Ludovic Godet
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Patent number: 8183636Abstract: One or more embodiments relate to a static random access memory cell comprising: a first inverter including a first n-channel pull-down transistor coupled between a first node and a ground voltage; a second inverter including a second n-channel pull-down transistor coupled between a second node and the ground voltage; a first n-channel access transistor coupled between a first bit line and the first node of the first inverter, a fin of the first n-channel access transistor having a lower charge carrier mobility than a fin of the first n-channel pull-down transistor; and a second n-channel access transistor coupled between a second bit line and the second node of the second inverter, a fin of the second n-channel access transistor having a lower charge carrier mobility than a fin of the second n-channel pull-down transistor.Type: GrantFiled: March 28, 2011Date of Patent: May 22, 2012Assignee: Infineon Technologies AGInventors: Joerg Berthold, Christian Pacha, Klaus Arnim Von
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Publication number: 20120122305Abstract: An electronic device includes a drift layer having a first conductivity type, a buffer layer having a second conductivity type, opposite the first conductivity type, on the drift layer and forming a P-N junction with the drift layer, and a junction termination extension region having the second conductivity type in the drift layer adjacent the P-N junction. The buffer layer includes a step portion that extends over a buried portion of the junction termination extension. Related methods are also disclosed.Type: ApplicationFiled: December 28, 2011Publication date: May 17, 2012Inventors: Qingchun Zhang, Anant K. Agarwal
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Publication number: 20120108043Abstract: A resist pattern is formed by coating a first positive resist composition comprising a polymer comprising 20-100 mol % of aromatic group-containing recurring units and adapted to turn alkali soluble under the action of an acid onto a substrate to form a first resist film, coating a second positive resist composition comprising a C3-C8 alkyl alcohol solvent which does not dissolve the first resist film on the first resist film to form a second resist film, exposing, baking, and developing the first and second resist films simultaneously with a developer.Type: ApplicationFiled: October 24, 2011Publication date: May 3, 2012Applicant: SHIN-ETSU CHEMICAL CO., LTD.Inventors: Jun Hatakeyama, Kenji Funatsu
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Patent number: 8163622Abstract: A method for creating NAND flash memory. Source implantations are performed at a first implantation angle to areas between stacked gate structures of a NAND string. Drain implantations are performed at a second implantation angle to areas between the stacked gate structures. The source implantation can include n-type and p-type materials implanted under different angles, and the drain implantation can include n-type and p-type materials implanted under different angles. Or, the source implantation can include multiple n-type implantations under different angles, and the drain implantation can include multiple n-type implantations under different angles.Type: GrantFiled: February 10, 2011Date of Patent: April 24, 2012Assignee: SanDisk Technologies Inc.Inventors: Gerrit Jan Hemink, Shinji Sato
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Patent number: 8163636Abstract: Method of preparing p-type doped ZnO or p-type doped ZnMgO, in which the following successive steps are carried out: a) implantation of O+ oxygen ions in an n-type doped ZnO or an n-type doped ZnMgO; b) first annealing at a temperature less than or equal to 1200° C. under oxygen for a time greater than or equal to 5 minutes; c) implantation of at least one ion of an element chosen among the elements of group I or the elements of group V of the periodic table; d) second annealing. The p-type doped ZnO or ZnMgO obtained by this method may be used in an optoelectronic device such as a light emitting diode.Type: GrantFiled: March 24, 2009Date of Patent: April 24, 2012Assignee: Commissariat a l'Energie AtomiqueInventor: Céline Chevalier
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Publication number: 20120094419Abstract: A method includes: forming a transfer gate on a semiconductor substrate; forming a first ion implantation region on a first side of the transfer gate; forming a second ion implantation region on the first side of the transfer gate such that the second ion implantation region encloses the first ion implantation region; forming a third ion implantation region along a surface of the semiconductor substrate; and forming a floating diffusion region at a second side of the transfer gate.Type: ApplicationFiled: September 22, 2011Publication date: April 19, 2012Applicant: Intellectual Ventures II LLCInventor: Youn-Sub Lim
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Publication number: 20120086057Abstract: A semiconductor memory device includes a gate insulating layer formed over a semiconductor substrate; a first conductive layer pattern for select transistors and memory cells formed on the gate insulating layer; a dielectric layer formed on the first conductive layer pattern; a second conductive layer pattern formed on the dielectric layer on the first conductive layer pattern for the memory cells; and select lines made of material having lower resistance than the second conductive layer pattern and coupled to the first conductive layer pattern for the select transistors.Type: ApplicationFiled: October 4, 2011Publication date: April 12, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Jin Gu KIM
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Publication number: 20120061767Abstract: A semiconductor device includes core transistors for forming a logic circuit, and I/O transistors for forming an input/output circuit. A distance from the main surface to a lowermost part of an n-type impurity region NR of the I/O n-type transistor is longer than that from the main surface to a lowermost part of an n-type impurity region NR of the core n-type transistor. A distance from the main surface to a lowermost part of a p-type impurity region PR of the I/O p-type transistor is longer than that from the main surface to a lowermost part of a p-type impurity region of the core p-type transistor. A distance from the main surface to the lowermost part of the n-type impurity region of the I/O n-type transistor is longer than that from the main surface to the lowermost part of the p-type impurity region of the I/O p-type transistor.Type: ApplicationFiled: July 19, 2011Publication date: March 15, 2012Inventor: Yuichi HIRANO
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Patent number: 8105926Abstract: A semiconductor region having an upper surface and a side surface is formed on a substrate. A first impurity region is formed in an upper portion of the semiconductor region. A second impurity region is formed in a side portion of the semiconductor region. The resistivity of the second impurity region is substantially equal to or smaller than that of the first impurity region.Type: GrantFiled: August 10, 2010Date of Patent: January 31, 2012Assignee: Panasonic CorporationInventors: Yuichiro Sasaki, Katsumi Okashita, Keiichi Nakamoto, Hiroyuki Ito, Bunji Mizuno
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Publication number: 20120015510Abstract: A method of fabricating a semiconductor device includes forming a mask pattern for defining a region of a semiconductor substrate. A field stop dopant layer will be formed in the defined region. Dopant ions are implanted into the defined region of the semiconductor substrate at a tilt angle of approximately 4.4° to 7°.Type: ApplicationFiled: July 19, 2011Publication date: January 19, 2012Applicant: Hynix Semiconductor Inc.Inventors: Min Yong LEE, Yong Soo Jung
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Publication number: 20120007172Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes an active region formed to be sloped or tilted by ?° (where 0°<?°<90°) from the bottom of a semiconductor substrate, at least one gate that is formed over the sloped active region and has a surface parallel to the bottom of the semiconductor substrate, and a landing plug that is coupled to the active region and is located between the gates. As a result, the area of the active region is increased thus increasing a channel width, so that the operation of the semiconductor device can be improved as the integration degree of the semiconductor device is rapidly increased.Type: ApplicationFiled: July 5, 2011Publication date: January 12, 2012Applicant: Hynix Semiconductor Inc.Inventor: Seung Wan KIM
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Patent number: 8063453Abstract: A gate of a semiconductor device includes a substrate, and a polysilicon layer over the substrate, wherein the polysilicon layer is doped with first conductive type impurities having a concentration that decreases when receding from the substrate and counter-doped with second conductive type impurities having a concentration that increases when receding from the substrate.Type: GrantFiled: December 30, 2008Date of Patent: November 22, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jae-Geun Oh, Jin-Ku Lee, Min-Ae Ju
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Publication number: 20110275203Abstract: A method of fabricating a semiconductor device includes forming a mask pattern for defining a region of a semiconductor substrate. An impurity layer for adjusting the threshold voltage of a cell will be formed in the defined region. Dopant ions are implanted into the defined region of the semiconductor substrate at a tilt angle of approximately 4.4° to 7°.Type: ApplicationFiled: July 19, 2011Publication date: November 10, 2011Applicant: Hynix Semiconductor Inc.Inventors: Min Yong Lee, Yong Soo Jung
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Publication number: 20110275204Abstract: A method of fabricating a semiconductor device includes forming a mask pattern for defining a region of a semiconductor substrate. An impurity layer for suppressing punch-through will be formed in the defined region. Dopant ions are implanted into the defined region of the semiconductor substrate at a tilt angle of approximately 4.4° to 7°.Type: ApplicationFiled: July 19, 2011Publication date: November 10, 2011Applicant: Hynix Semiconductor Inc.Inventors: Min Yong LEE, Yong Soo Jung
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Publication number: 20110275202Abstract: A semiconductor device in one embodiment has a first connection region, a second connection region and a semiconductor volume arranged between the first and second connection regions. Provision is made, within the semiconductor volume, in the vicinity of the second connection region, of a field stop zone for spatially delimiting a space charge zone that can be formed in the semiconductor volume, and of an anode region adjoining the first connection region. The dopant concentration profile within the semiconductor volume is configured such that the integral of the ionized dopant charge over the semiconductor volume, proceeding from an interface of the anode region which faces the second connection region, in the direction of the second connection region, reaches a quantity of charge corresponding to the breakdown charge of the semiconductor device only near the interface of the field stop zone which faces the second connection region.Type: ApplicationFiled: July 20, 2011Publication date: November 10, 2011Inventors: Anton MAUDER, Hans-Joachim Schulze, Frank Hille, Holger Schulze, Manfred Pfaffenlehner, Carsten Schäffer, Franz-Josef Niedernostheide
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Publication number: 20110263109Abstract: In an electrooptical device including an electrooptical modulating layer between a first substrate 101 and a second substrate 105, all edges 107 to 109 of the first substrate 101 and the second substrate 105, except an edge where IC chips 110 and 111 are attached, are trued up each other between the first substrate 101 and the second substrate 105. By this, it is possible to make the area of the first substrate 101 minimum.Type: ApplicationFiled: July 7, 2011Publication date: October 27, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Yoshiharu HIRAKATA, Takeshi FUKUNAGA
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Publication number: 20110254133Abstract: New photoresist are provided that comprises an Si-containing component and that are particularly useful for ion implant lithography applications. Photoresists of the invention can exhibit good adhesion to underlying inorganic surfaces such as SiON, silicon oxide, silicon nitride and other inorganic surfaces.Type: ApplicationFiled: December 15, 2010Publication date: October 20, 2011Applicant: Rohm and Haas Electronic Materials LLCInventor: Gerhard POHLERS
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Publication number: 20110233656Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer of a first conductivity type, first semiconductor pillar regions of the first conductivity type and second semiconductor pillar regions of a second conductivity type, a semiconductor region of the first conductivity type, a base region of the second conductivity type, a source region, a first main electrode, a second main electrode and a control electrode. The second semiconductor pillar region includes a plurality of semiconductor regions of the second conductivity type. A difference is provided between peak values of impurity concentration profiles of an uppermost and a lowermost semiconductor regions of the plurality of semiconductor regions, and in the alternately arranging direction of the first and second semiconductor pillar regions, maximum width of the uppermost semiconductor region is generally equal to or narrower than maximum width of the lowermost semiconductor region.Type: ApplicationFiled: March 16, 2011Publication date: September 29, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi OHTA, Yasuto Sumi, Klyoshi Kimura
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Publication number: 20110233713Abstract: A Schottky diode includes a deep well formed in a substrate, an isolation layer formed in the substrate, a first conductive type guard ring formed in the deep well along an outer sidewall of the isolation layer and located at a left side of the isolation layer, a second conductive type well formed in the deep well along the outer sidewall of the isolation layer and located at a right side of the isolation layer, an anode electrode formed over the substrate and coupled to the deep well and the guard ring, and a cathode electrode formed over the substrate and coupled to the well. A part of the guard ring overlaps the isolation layer.Type: ApplicationFiled: October 4, 2010Publication date: September 29, 2011Inventor: Jin-Yeong Son
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Publication number: 20110193100Abstract: A method of manufacturing an SiC semiconductor device according to the present invention includes the steps of (a) by using a single mask, etching regions of an SiC semiconductor layer which serve as an impurities implantation region and a mark region, to form recesses, (b) by using the same mask as in the step (a), performing ion-implantation in the recesses of the regions which serve as the impurities implantation region and the mark region, at least from an oblique direction relative to a surface of the SiC semiconductor layer and (c) positioning another mask based on the recess of the region which serves as the impurities implantation region or the mark region, and performing well implantation in a region containing the impurities implantation region.Type: ApplicationFiled: October 25, 2010Publication date: August 11, 2011Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Noriaki TSUCHIYA, Yoichiro Tarui
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Patent number: 7994033Abstract: The present invention provides a semiconductor apparatus for improving a switching speed and a withstand voltage, and a manufacturing method of the semiconductor apparatus.Type: GrantFiled: June 1, 2010Date of Patent: August 9, 2011Assignee: Panasonic CorporationInventor: Ryo Yoshii
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Publication number: 20110170337Abstract: A device includes a first transistor including a fin and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor. In a method, the fin of the first transistor is treated to have a lower charge carrier mobility than the fin of the second transistor.Type: ApplicationFiled: March 28, 2011Publication date: July 14, 2011Inventors: Jörg Berthold, Christian Pacha, Klaus von Arnim
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Patent number: 7968955Abstract: A gate of a semiconductor device includes a substrate, and a polysilicon layer over the substrate, wherein the polysilicon layer is doped with first conductive type impurities having a concentration that decreases when receding from the substrate and counter-doped with second conductive type impurities having a concentration that increases when receding from the substrate.Type: GrantFiled: December 30, 2008Date of Patent: June 28, 2011Assignee: hynix Semiconductor Inc.Inventors: Jae-Geun Oh, Jin-Ku Lee, Min-Ae Ju
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Publication number: 20110115009Abstract: A method for forming a semiconductor device is disclosed. The method includes providing a substrate prepared with a second gate structure. An inter-gate dielectric is formed on the substrate and over the second gate. A first gate is also formed. The first gate is adjacent to and separated from the second gate by the inter-gate dielectric. The substrate is patterned to form a split gate structure with the first and second adjacent gates. The split gate structure is provided with an e-field equalizer adjacent to the first gate. The e-field equalizer improves uniformity of e-field across the first gate during operation.Type: ApplicationFiled: November 19, 2009Publication date: May 19, 2011Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Shyue Seng TAN, Lee Wee TEO, Chunshan YIN
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Patent number: 7929321Abstract: A DC-to-DC converter includes a high-side transistor and a low-side transistor wherein the high-side transistor is implemented with a high-side enhancement mode MOSFET. The low side-transistor further includes a low-side enhancement MOSFET shunted with a depletion mode transistor having a gate shorted to a source of the low-side enhancement mode MOSFET. A current transmitting in the DC-to-DC converter within a time-period between T2 and T3 passes through a channel region of the depletion mode MOSFET instead of a built-in diode D2 of the low-side MOSFET transistor. The depletion mode MOSFET further includes trench gates surrounded by body regions with channel regions immediately adjacent to vertical sidewalls of the trench gates wherein the channel regions formed as depletion mode channel regions by dopant ions having electrical conductivity type opposite from a conductivity type of the body regions.Type: GrantFiled: August 22, 2008Date of Patent: April 19, 2011Assignee: Force-Mos Technology CorpInventor: Fwu-Iuan Hshieh
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Publication number: 20110073922Abstract: A semiconductor device manufacturing method includes the steps of ion-implanting a p-type or an n-type impurity into a Si layer portion to become a p-type or an n-type contact region of a semiconductor device, forming a metal film for a contact on a surface of the contact region without performing heat treatment for activating implanted ions after the ion-implanting step, and forming a silicide of a metal of the metal film by causing the metal to react with the Si layer portion by heating. It is desired to simultaneously perform the step of forming the silicide and the step of activating the implanted ions by heat treatment after the metal film is formed.Type: ApplicationFiled: April 17, 2009Publication date: March 31, 2011Inventors: Tadahiro Ohmi, Akinobu Teramoto, Hiroaki Tanaka, Tatsunori Isogai
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Patent number: 7915128Abstract: A transistor suitable for high-voltage applications and a method of manufacture is provided. A first device is formed by depositing a dielectric layer and a conductive layer over a substrate. A hard mask is deposited over the conductive layer and patterned using photolithography techniques. The photoresist material is removed prior to etching the underlying conductive layer and dielectric layer. The hard mask is also used as an implant mask. Another mask may be deposited and formed over the conductive layer to form other devices in other regions of the substrate. The other mask is preferably removed from over the hard mask prior to etching the conductive layer and the dielectric layer.Type: GrantFiled: February 29, 2008Date of Patent: March 29, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu Wen Chen, Fu-Hsin Chen, Ming-Ren Tsai, William Wei-Yuan Tien
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Publication number: 20110049628Abstract: A fin-semiconductor region (13) is formed on a substrate (11). A first impurity which produces a donor level or an acceptor level in a semiconductor is introduced in an upper portion and side portions of the fin-semiconductor region (13), and oxygen or nitrogen is further introduced as a second impurity in the upper portion and side portions of the fin-semiconductor region (13).Type: ApplicationFiled: January 20, 2010Publication date: March 3, 2011Inventors: Tomohiro Okumura, Takayuki Kai, Yuichiro Sasaki
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Patent number: 7884001Abstract: Embodiments relate to an image sensor and a method of manufacturing an image sensor. According to embodiments, an image sensor may include a gate over a semiconductor substrate, a first impurity region over the semiconductor substrate, a second impurity region over the semiconductor substrate, the second impurity region being shallower than the first impurity region, and a third impurity region formed in the first impurity region, and bent toward the gate at a predetermined angle. According to embodiments, the third impurity region may be an n-type impurity region. According to embodiments, an area of a photodiode may be increased and a transfer efficiency of electrons generated from a photodiode may be increased.Type: GrantFiled: December 27, 2008Date of Patent: February 8, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Joung-Ho Lee
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Patent number: 7825015Abstract: The present invention provides a method for implanting ions in a semiconductor device capable of compensating for a difference in threshold voltages between a central portion and edge portions of a substrate generated while performing uniform ion implantation to entire surfaces of a substrate and another method for fabricating a semiconductor device capable of improving distribution of transistor parameters inside a substrate by forming a nonuniform channel doping layer or by forming a nonuniform junction profile.Type: GrantFiled: December 30, 2004Date of Patent: November 2, 2010Assignee: Hynix Semiconductor, Inc.Inventors: Yong-Sun Sohn, Seung-Woo Jin, Min-Yong Lee, Kyoung-Bong Rouh
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Patent number: 7825478Abstract: Polarity dependent switches for resistive sense memory are described. A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically connects to the bit contact. The source contact and the bit contact are asymmetrically implanted with dopant material.Type: GrantFiled: March 20, 2009Date of Patent: November 2, 2010Assignee: Seagate Technology LLCInventors: Chulmin Jung, Maroun Georges Khoury, Yong Lu, Young Pil Kim
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Publication number: 20100248441Abstract: A structure, memory devices using the structure, and methods of fabricating the structure. The structure includes: an array of nano-fins, each nano-fin comprising an elongated block of semiconductor material extending axially along a first direction, the nano-fins arranged in groups of at least two nano-fins each, wherein ends of nano-fins of each adjacent group of nano-fins are staggered with respect to each other on both a first and a second side of the array; wherein nano-fins of each group of nano-fins are electrically connected to a common contact that is specific to each group of nano-fins such that the common contacts comprise a first common contact on the first side of the array and a second common contact on the second side of the array; and wherein each group of nano-fins has at least two gates that electrically control the conductance of nano-fins of the each group of nano-fins.Type: ApplicationFiled: June 7, 2010Publication date: September 30, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kailash Gopalakrishnan, Rohit Sudhir Shenoy
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Publication number: 20100240202Abstract: The present invention provides a semiconductor apparatus for improving a switching speed and a withstand voltage, and a manufacturing method of the semiconductor apparatus.Type: ApplicationFiled: June 1, 2010Publication date: September 23, 2010Applicant: Panasonic CorporationInventor: Ryo YOSHII
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Publication number: 20100240201Abstract: A first species and a second species are implanted into a conductor of a substrate, which may be copper. The first species and second species may be implanted sequentially or at least partly simultaneously. Diffusion of the first species within the conductor of the substrate is prevented by the presence of the second species. In one particular example, the first species is silicon and the second species is nitrogen, although other combinations are possible.Type: ApplicationFiled: April 14, 2010Publication date: September 23, 2010Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATE,INC.Inventors: Heyun YIN, George D. Papasouliotis, Vikram Singh
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Publication number: 20100240200Abstract: A substrate processing system includes a processing chamber that performs a preset process on a plurality of substrates in a batch-type manner; a substrate mounting table, installed within the processing chamber, configured to mount the plurality of substrates on a concentric circle and configured to be rotatable forward and backward; substrate accommodation units configured to accommodate the plurality of substrates in multi-stages in a vertical direction; substrate holders and configured to transfer the substrates between the substrate accommodation units and the processing chamber; elevating mechanisms configured to move the substrate accommodation units up and down. Unprocessed substrates are mounted on the substrate mounting table while the substrate mounting table is being rotated in one direction.Type: ApplicationFiled: March 16, 2010Publication date: September 23, 2010Applicant: TOKYO ELECTRON LIMITEDInventors: Hiromitsu Sakaue, Takashi Horiuchi
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Publication number: 20100213535Abstract: Semiconductor devices having reduced parasitic current and methods of malting the semiconductor devices are provided. Further provided are memory devices having reduced adjacent wordline disturb. The memory devices contain wordlines formed over a semiconductor substrate, wherein at least one wordline space is formed between the wordlines. Adjacent wordline disturb is reduced by implanting one or more of indium, boron, and a combination of boron and indium in the surface of the at least one wordline space.Type: ApplicationFiled: February 23, 2009Publication date: August 26, 2010Applicant: SPANSION LLCInventors: Gulzar A. Kathawala, Zhizheng Liu, Kuo Tung Chang, Lei Xue
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Publication number: 20100210095Abstract: Methods of forming polarity dependent switches for resistive sense memory are described. Methods for forming a memory unit include implanting dopant material more heavily in a source contact than a bit contact of a semiconductor transistor, and electrically connecting a resistive sense memory cell to the bit contact. The resistive sense memory cell is configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell.Type: ApplicationFiled: May 5, 2010Publication date: August 19, 2010Applicant: SEAGATE TECHNOLOGY LLCInventors: Chulmin Jung, Maroun Georges Khoury, Yong Lu, Young Pil Kim
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Publication number: 20100208517Abstract: A memory architecture that employs one or more semiconductor PIN diodes is provided. The memory employs a substrate that includes a buried bit/word line and a PIN diode. The PIN diode includes a non-intrinsic semiconductor region, a portion of the bit/word line, and an intrinsic semiconductor region positioned between the non-intrinsic region and the portion of the bit/word line.Type: ApplicationFiled: February 13, 2009Publication date: August 19, 2010Applicant: Spansion LLCInventors: Wai Lo, Christie Marrian, Tzu-Ning Fang, Sameer Haddad
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Publication number: 20100181657Abstract: A nonvolatile memory cell includes: a rail-shaped first conductor formed at a first height above a substrate; a rail-shaped second conductor formed above the first conductor; and a vertically oriented first pillar comprising a p-i-n first diode; wherein the first pillar is disposed between the second conductor and the first conductor; wherein the first diode comprises an intrinsic or lightly doped region; and wherein the intrinsic or lightly doped region has a first thickness of about 300 angstroms or greater. Numerous additional aspects are provided.Type: ApplicationFiled: June 10, 2009Publication date: July 22, 2010Applicant: SanDisk 3D LLCInventors: S. Brad Herner, Steven J. Radigan
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Patent number: 7745334Abstract: By performing sophisticated anneal techniques, such as laser anneal, flash anneal and the like, for a metal silicide formation, such as nickel silicide, the risk of nickel silicide defects in sensitive device regions, such as SRAM pass gates, may be significantly reduced. Also, the activation of dopants may be performed in a highly localized manner, so that undue damage of gate insulation layers may be avoided when activating and re-crystallizing drain and source regions.Type: GrantFiled: April 18, 2007Date of Patent: June 29, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Patrick Press, Karla Romero, Martin Trentzsch, Karsten Wieczorek, Thomas Feudel, Markus Lenski, Rolf Stephan
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Publication number: 20100148125Abstract: A method is provided of forming a semiconductor device. A substrate is provided having a dielectric layer formed thereover. The dielectric layer covers a protected region of the substrate, and has a first opening exposing a first unprotected region of the substrate. A first dopant is implanted into the first unprotected region through the first opening in the dielectric layer, and into the protected region through the dielectric layer.Type: ApplicationFiled: December 16, 2008Publication date: June 17, 2010Applicant: Texas Instruments IncorporatedInventors: Seetharaman Sridar, Marie Denison, Sameer Pendharkar
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Patent number: 7732309Abstract: Methods for implanting ions into a substrate by a plasma immersion ion implanting process are provided. In one embodiment, the method for implanting ions into a substrate by a plasma immersion ion implantation process includes providing a substrate into a processing chamber, supplying a gas mixture including a reacting gas and a reducing gas into the chamber, and implanting ions from the gas mixture into the substrate. In another embodiment, the method includes providing a substrate into a processing chamber, supplying a gas mixture including reacting gas and a hydrogen containing reducing gas into the chamber, and implanting ions from the gas mixture into the substrate.Type: GrantFiled: December 8, 2006Date of Patent: June 8, 2010Assignee: Applied Materials, Inc.Inventors: Shijian Li, Kartik Ramaswamy, Biagio Gallo, Dong Hyung Lee, Majeed A. Foad
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Publication number: 20100117160Abstract: Polarity dependent switches for resistive sense memory are described. A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically connects to the bit contact. The source contact and the bit contact are asymmetrically implanted with dopant material.Type: ApplicationFiled: March 20, 2009Publication date: May 13, 2010Applicant: SEAGATE TECHNOLOGY LLCInventors: Chulmin Jung, Maroun Georges Khoury, Yong Lu, Young Pil Kim
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Publication number: 20100090347Abstract: The present disclosure is directed to the preparation of a semiconductor substrate, and metallization of a contact area on the substrate to produce a contact in a semiconductor device. The method includes pre-treating the substrate by ultra fast laser treatment of a contact area, and depositing an interconnect metal layer on the contact area to create a contact. The process may include depositing a layer of dielectric-forming material on the substrate and removing a portion of the dielectric material from the substrate to reveal a contact area, prior to laser treating and metallization.Type: ApplicationFiled: October 9, 2008Publication date: April 15, 2010Inventors: Stephen D. Saylor, Susan Alie
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Publication number: 20100084720Abstract: A gate of a semiconductor device includes a substrate, and a polysilicon layer over the substrate, wherein the polysilicon layer is doped with first conductive type impurities having a concentration that decreases when receding from the substrate and counter-doped with second conductive type impurities having a concentration that increases when receding from the substrate.Type: ApplicationFiled: December 30, 2008Publication date: April 8, 2010Applicant: Hynix Semiconductor Inc.Inventors: Jae-Geun Oh, Jin-Ku Lee, Min-Ae Ju
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Publication number: 20100087046Abstract: An object is to provide a method for manufacturing an SOI substrate, by which defective bonding can be prevented. An embrittled layer is formed in a region of a semiconductor substrate at a predetermined depth; an insulating layer is formed over the semiconductor substrate; the outer edge of the semiconductor substrate is selectively etched on the insulating layer side to a region at a greater depth than the embrittled layer; and the semiconductor substrate and a substrate having an insulating surface are superposed on each other and bonded to each other with the insulating layer interposed therebetween. The semiconductor substrate is heated to be separated at the embrittled layer while a semiconductor layer is left remaining over the substrate having an insulating surface.Type: ApplicationFiled: December 7, 2009Publication date: April 8, 2010Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Hideto Ohnuma
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Patent number: 7691700Abstract: One aspect of the inventors' concept relates to a method of forming a semiconductor device. In this method, a gate structure is formed over a semiconductor body. A source/drain mask is patterned over the semiconductor body implanted source and drain regions are formed that are associated with the gate structure. After forming the implanted source and drain regions, a multi-stage implant is performed on the source and drain regions that comprises at least two implants where the dose and energy of the first implant varies from the dose and energy of the second implant. Other methods and devices are also disclosed.Type: GrantFiled: June 27, 2007Date of Patent: April 6, 2010Assignee: Texas Instruments IncorporatedInventors: Manoj Mehrotra, Stan Ashburn, Shaoping Tang