Abstract: A method for manufacturing a CMOS image sensor is provided. A metal line can be formed over a semiconductor substrate including a transistor structure. Dangling bonding on the surface of the semiconductor substrate can be removed after forming the metal line by injecting a preset amount of hydrogen (H) atoms on the surface of the semiconductor substrate. Then, a thermal treatment can be performed on the resulting structure.

Abstract: A non-uniform ion implantation apparatus comprises a wide ion beam generator configured to generate a plurality of wide ion beams to irradiate at least two regions on the entire area of a wafer, and a wafer rotating device configured to rotate the wafer in a predetermined direction while the wide ion beams generated by the wide ion beam generator are irradiated to the wafer. Among the wide ion beams, at least one wide ion beam has a different dose from that of at least one different wide ion beam. Since the wide ion beams are irradiated at different doses to the wafer, a smooth circular border is formed between the regions to which the impurity ions are implanted to different concentrations. Since the position of the wafer is suitably changed for the wide ion beams, it is possible to control disposition of the regions implanted with the impurity ions of different concentrations.

Abstract: A method of preventing toxic gas formation after an implantation process is disclosed. Certain dopants, when implanted into films disposed on a substrate, may react when exposed to moisture to form a toxic gas and/or a flammable gas. By in-situ exposing the doped film to an oxygen containing compound, dopant that is shallowly implanted into the layer stack reacts to form a dopant oxide, thereby reducing potential toxic gas and/or flammable gas formation. Alternatively, a capping layer may be formed in-situ over the implanted film to reduce the potential generation of toxic gas and/or flammable gas.

Abstract: A method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising performing front end processing, performing a first bitline implant, or pocket implants, or both into the first bitline spacings to establish buried first bitlines within the substrate, depositing a layer of the spacer material over the charge trapping dielectric and the polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the polysilicon layer features to define second bitline spacings between adjacent memory cells, performing a deep arsenic implant into the second bitline spacings to establish a second bitline within the structure that is deeper than the first bit line, removing the sidewall spacers and performing back end processing.

Abstract: In a method of producing a semiconductor element in a substrate, a plurality of carbide precipitates is formed in the substrate, doping atoms are implanted into the substrate, thereby forming crystal defects in the substrate, the substrate is heated, such that at least a part of the crystal defects is eliminated using the carbide precipitates, and the semiconductor element is formed using the doping atoms.

Abstract: A MOS transistor including a gate insulation layer and a gate electrode layer on a channel region of a semiconductor substrate. A gate spacer layer is formed on a sidewall of the electrode layer and the insulation layer. The transistor includes a deep extended source/drain region, a first source/drain region that is deeper than the extended source/drain region, and a second source/drain region that is shallower than the extended source/drain region.

Abstract: A semiconductor device is provided comprising a main electrode (4) and a dielectric (3) in contact with the main electrode (4), the main electrode (4) comprising a material having a work function and a work function modulating element (6) for modulating the work function of the material of the main electrode (4) towards a predetermined value. The main electrode (4) furthermore comprises a diffusion preventing dopant element (5) for preventing diffusion of the work function modulating element (6) towards and/or into the dielectric (3). Methods for forming such a semiconductor device are also described.

Abstract: Methods for implanting ions into a substrate by a plasma immersion ion implanting process are provided. In one embodiment, the method for implanting ions into a substrate by a plasma immersion ion implantation process includes providing a substrate into a processing chamber, supplying a gas mixture including a reacting gas and a reducing gas into the chamber, and implanting ions from the gas mixture into the substrate. In another embodiment, the method includes providing a substrate into a processing chamber, supplying a gas mixture including reacting gas and a hydrogen containing reducing gas into the chamber, and implanting ions from the gas mixture into the substrate.

Abstract: A method of reducing hot carrier degradation and a semiconductor structure so formed are disclosed. One embodiment of the method includes depositing a silicon nitride layer over a transistor device, ion implanting a species into the silicon nitride layer to drive hydrogen from the silicon nitride layer, and annealing to diffuse the hydrogen into a channel region of the transistor device. The species may be chosen from, for example: germanium (Ge), arsenic (As), xenon (Xe), nitrogen (N), oxygen (O), carbon (C), boron (B), indium (In), argon (Ar), helium (He), and deuterium (De). The ion implantation modulates atoms in the silicon nitride layer such as hydrogen, nitrogen and hydrogen-nitrogen bonds such that hydrogen can be controllably diffused into the channel region.

Abstract: A method for doping impurities into a device layer is provided. The method includes providing a carbonized dopant layer over a device layer, wherein the carbonized dopant layer comprises one or more dopant impurities, and heat treating the carbonized dopant layer to thermally diffuse the dopant impurities into the device layer.

Abstract: Techniques for low-temperature ion implantation are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for low-temperature ion implantation. The apparatus may comprise a wafer support mechanism to hold a wafer during ion implantation and to facilitate movement of the wafer in at least one dimension. The apparatus may also comprise a cooling mechanism coupled to the wafer support mechanism. The cooling mechanism may comprise a refrigeration unit, a closed loop of rigid pipes to circulate at least one coolant from the refrigeration unit to the wafer support mechanism, and one or more rotary bearings to couple the rigid pipes to accommodate the movement of the wafer in the at least one dimension.

Abstract: A plasma enhanced physical vapor deposition process deposits an amorphous carbon layer on an ion-implanted wafer for use in dynamic surface annealing of the wafer with an intense line beam of a laser wavelength. The deposition process is carried out at a wafer temperature below the dopant clustering threshold temperature, and includes introducing the wafer into a chamber having a carbon-containing target overlying the wafer, and furnishing a carrier gas into the chamber. The process further includes generating a wafer bias voltage and applying target source power to the carbon-containing target sufficient to produce ion bombardment of the carbon-containing target. The wafer bias voltage is set to a level at which the amorphous carbon layer that is deposited has a desired extinction coefficient at the laser wavelength.

Abstract: A strained-silicon film is disclosed. A silicon-germanium film is made by ion implantation of germanium into an epitaxial silicon layer, preferably at a temperature in the range of 200 C to 400 C. The wafer is annealed in situ or optionally after implantation. A silicon film is applied to the silicon-germanium film in a conventional manner to create the strained-silicon substrate.

Abstract: A semiconductor device includes: a semiconductor layer; an insulating film provided on the semiconductor layer; and a charge storage layer provided on the insulating film. The semiconductor layer has a channel formation region in its surface portion. The insulating film contains silicon, germanium, and oxygen. The charge storage layer is capable of storing charge supplied from the semiconductor layer through the insulating film. A method of manufacturing a semiconductor device includes: forming a silicon oxide film on a surface of a semiconductor layer; introducing germanium into the silicon oxide film; forming an insulating film containing silicon, germanium, and oxygen by heat treatment under oxidizing atmosphere; and forming a charge storage layer on the insulating film, the charge storage layer being capable of storing charge supplied from the semiconductor layer through the insulating layer.

Abstract: Techniques for temperature-controlled ion implantation are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for temperature-controlled ion implantation. The apparatus may comprise at least one thermal sensor adapted to measure a temperature of a wafer during an ion implantation process inside an end station of an ion implanter. The apparatus may also comprise a thermal conditioning unit coupled to the end station. The apparatus may further comprise a controller in communication with the thermal sensor and the thermal conditioning unit, wherein the controller compares the measured temperature to a desired wafer temperature and causes the thermal conditioning unit to adjust the temperature of the wafer based upon the comparison.

Abstract: An electrode on a semiconductor substrate includes a polysilicon layer, a silicon-implanted layer on the polysilicon layer, a tungsten nitride layer on the silicon-implanted layer, a tungsten nitride layer on the silicon-implanted layer, and a tungsten layer on the tungsten nitride layer. The layer between the polysilicon layer and the tungsten nitride layer may be either a tungsten silicon nitride layer or a silicon-germanium layer.

Abstract: An apparatus and method for controlling the net doping in the active region of a semiconductor device in accordance with a gate length is provided. A compensating dopant is chosen to be a type of dopant which will electrically neutralize dopant of the opposite type in the substrate. By implanting the compensating dopant at relatively high angle and high energy, the compensating dopant will pass into and through the gate region for short channels and have little or no impact on the total dopant concentration within the gate region. Where the channel is of a longer length, the high implant angle and the high implant energy cause the compensating dopant to lodge within the channel thereby neutralizing a portion of the dopant of the opposite type.

Abstract: Some example embodiments of the invention provide a method to improve the performance of MOS devices by increasing the stress in the channel region. An example embodiment for a NMOS transistor is to form a tensile stress layer over a NMOS transistor. A heavy ion implantation is performed into the stress layer and then an anneal is performed. This increases the amount of stress from the stress layer that the gate retains/memorizes thereby increasing device performance.

Abstract: Embodiments relate to a method for forming a semiconductor device in which a first oxide layer may be deposited over a surface of a semiconductor substrate including high-voltage (HV) and low-voltage (LV) wells, the first oxide layer having a predetermined thickness corresponding to a high-voltage (HV) area of the well. A first photoresist pattern may be formed over a surface of the first oxide layer. An etching process may be performed using the first photoresist pattern as a mask, so that the first oxide layer is selectively etched until the semiconductor substrate is partially exposed, to form a first oxide layer pattern. A second oxide layer may be deposited over a surface of the semiconductor substrate including the first oxide layer pattern using the first photoresist pattern as a mask, the second oxide layer having a predetermined thickness corresponding to a low-voltage (LV) area of the well. The first photoresist pattern may be removed.

Abstract: A method for forming doped metal-semiconductor compound regions in a substrate is disclosed. In one aspect, a method for forming silicide regions in a substrate comprises partially regrowing an upper amorphous region on top of a crystalline part of the substrate, after having doped the upper amorphous region, to form a regrown region, thereby leaving a remaining upper amorphous region in between the regrown region and the major surface of the substrate. The remaining upper amorphous region is used for forming the metal-semiconductor compound.

Abstract: Devices and methods for junction formation in manufacturing a semiconductor device are disclosed. The devices have shallow junction depths far removed from end-of range defects. The method comprises forming an amorphous region in a crystalline semiconductor such as silicon down to a first depth, followed by implantation of a substitutional element such as carbon to a smaller depth than the first depth. The region is then doped with suitable dopants, e.g. phosphorus or boron, and the amorphous layer recrystallized by a thermal process.

Abstract: The present invention provides a method for forming low-defect density changed-orientation Si by amorphization/templated recrystallization (ATR) processes in which regions of Si having a first crystal orientation are amorphized by ion implantation and then recrystallized into the orientation of a template layer having a different orientation. More generally, the invention relates to the high temperature annealing conditions needed to eliminate the defects remaining in Si-containing single crystal semiconductor materials formed by ion-implant-induced amorphization and templated recrystallization from a layer whose orientation may be the same or different from the amorphous layer's original orientation. The key component of the inventive method is a thermal treatment for minutes to hours in the the temperature range 1250-1330° C. to remove the defects remaining after the initial recrystallization anneal.

Abstract: A method for doping a fin-based semiconductor device is disclosed. In one aspect, the method comprises patterning at least one fin, each fin comprising a top surface and a left sidewall surface and a right sidewall surface. The method further comprises providing a first target surface being the right sidewall of a first block of material. The method further comprises scanning a first primary ion beam impinging on the first target surface with an incident angle ? different from zero degrees and thereby inducing a first secondary ion beam, and doping at least the left sidewall surface and possibly the top surface of the fin opposite to the first target surface with the first secondary ion beam.

Abstract: A method for manufacturing a non-volatile memory device is provided, including the step of performing an ion implantation process to form an impurity area in a field oxide area formed on a substrate, where the ion implantation process is performed at least two times while varying ion implantation angles relative to the substrate.

Abstract: A method for manufacturing doped substrates using a continuous large area scanning implantation process is disclosed. In one embodiment, the method includes providing a movable track member. The movable track member is provided in a chamber. The chamber includes an inlet and an outlet. In a specific embodiment, the movable track member can include one or more rollers, air bearings, belt member, and/or movable beam member to provide one or more substrates for a scanning process. The method may also include providing a first substrate. The first substrate includes a first plurality of tiles. The method maintains the first substrate including the first plurality of tiles in a vacuum. The method includes transferring the first substrate including the first plurality of tiles from the inlet port onto the movable track member. The first plurality of tiles are subjected to a scanning implant process. The method also includes maintaining a second substrate including a second plurality of tiles in the vacuum.

Abstract: Provided is a method of fabricating a lateral double diffused MOSFET. In the method, ions are implanted onto a substrate to form a body region of the LDMOS transistor using a photoresist pattern as an ion implantation mask. Herein, the photoresist can be patterned to have a slope of with an angle in the range of 87° to 88°.

Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. In the method, a field oxide layer can be formed in a semiconductor substrate so as to define and active electrode including a gate oxide layer and a gate poly is formed in the active region. An etch groove is formed between the gate electrode and the field oxide layer. Dopant ions are implanted between the gate electrode and the field oxide layer so as to form a source/drain region.

Abstract: Embodiments of the present invention include methods for forming an ultra-shallow junction in a substrate. In one embodiment, the method includes providing a silicon substrate, co-implanting the silicon substrate with carbon and a dopant to form a doped silicon substrate, and exposing the silicon substrate to a short time thermal anneal. In certain embodiments, the silicon substrate is exposed to a rapid thermal anneal after co-implanting the silicon substrate but prior to exposing the silicon substrate to a short time thermal anneal. In certain embodiments, the pre-amorphization implant is performed on the silicon substrate prior to implanting the silicon substrate with carbon and a dopant. In certain embodiments, the silicon substrate is a monocrystalline silicon substrate.

Abstract: Provided is a method for fabricating a semiconductor device. In the method, a poly layer on a semiconductor substrate is etched to a predetermined depth. Ions are implanted into the poly layer at a predetermined angle. The poly layer is etched again to expose a portion of the semiconductor substrate. Therefore, stress is applied to the poly gate instead of the barrier layer, so that the barrier layer is not opened during contact etching because effects of the barrier layer thickness can be solved. Also, stress is applied to a poly gate directly contacting a channel region of the semiconductor substrate to allow tensile force caused by the stress of the poly gate to directly induce tensile force to the channel region, and thus increase mobility, so that device characteristics can be remarkably enhanced.

Abstract: A transistor device having a conformal depth of impurities implanted by isotropic ion implantation into etched junction recesses. For example, a conformal depth of arsenic impurities and/or carbon impurities may be implanted by plasma immersion ion implantation in junction recesses to reduce boron diffusion and current leakage from boron doped junction region material deposited in the junction recesses. This may be accomplished by removing, such as by etching, portions of a substrate adjacent to a gate electrode to form junction recesses. The junction recesses may then be conformally implanted with a depth of arsenic and carbon impurities using plasma immersion ion implantation. After impurity implantation, boron doped silicon germanium can be formed in the junction recesses.

Abstract: A method of fabricating polysilicon lines and polysilicon gates, the method of including: forming a dielectric layer on a top surface of a substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysilicon layer with N-dopant species, the N-dopant species essentially contained within the polysilicon layer; implanting the polysilicon layer with a nitrogen containing species, the nitrogen containing species essentially contained within the polysilicon layer.

Abstract: A silicon wafer includes a principal face for forming electronic devices; an end region; and a tapered region which is located between the principal face and the end region, in which the thickness of the silicon wafer is gradually reduced, and which has a slope that makes an angle of greater than zero degree and less than 9.5 degrees or an angle of greater than 19 degrees with the principal face. An SOI wafer prepared by forming a buried oxide layer in a silicon wafer includes a principal face, end region, and tapered region that are substantially the same as those described above. A method for manufacturing an SOI wafer includes the steps of implanting oxygen ions into a silicon wafer; and heat-treating the resulting silicon wafer such that a buried oxide layer is formed in the silicon wafer.

Abstract: An epitaxial layer is formed on a high-resistance semiconductor substrate containing interstitial oxygen at a high concentration, and then a heat treatment is performed to the semiconductor substrate at a high temperature in an oxidizing atmosphere. Accordingly, a stratiform region of SiO2 is formed by deposition at an interface between the epitaxial layer and the semiconductor substrate. As a result, an apparent SOI substrate for an SOI semiconductor device can be manufactured at a low cost.

Abstract: The present invention is generally directed to various methods of using ion implantation techniques to control various metal formation processes. In one illustrative embodiment, the method comprises forming a metal seed layer above a patterned layer of insulating material, the patterned layer of insulating material defining a plurality of field areas, deactivating at least a portion of the metal seed layer in areas where the metal seed layer is positioned above at least some of the field areas, and performing a deposition process to deposit a metal layer above the metal seed layer. In some embodiments, the metal may be comprised of copper, platinum, nickel, tantalum, tungsten, cobalt, etc. Portions of the metal seed layer may be deactivated by implanting ions into portions of the metal seed layer positioned above at least some of the field areas. The implanted ions may be comprised of nitrogen, carbon, silicon, hydrogen, etc.